Intersil Corporation 82C86H Datasheet
82C86H
March 1997
Features
• Full Eight Bit Bi-Directional Bus Interface
• Industry Standard 8286 Compatible Pinout
• High Drive Capability
- B Side I
- A Side I
• Three-State Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA
• Operating Temperature Range
- C82C86H . . . . . . . . . . . . . . . . . . . . . . . . . 0
- I82C86H. . . . . . . . . . . . . . . . . . . . . . . . -40
- M82C86H. . . . . . . . . . . . . . . . . . . . . . -55
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
OL
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA
OL
o
C to +70oC
o
C to +85oC
o
C to +125oC
CMOS Octal Bus Transceiver
Description
The Intersil 82C86H is a high performance CMOS Octal
Transceiver manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C86H provides a full
eight-bit bi-directional bus interface in a 20 lead package. The
Transmit (T) control determines the data direction. The active
low output enable (
80C88 and other microprocessors. The 82C86H has gated
inputs, eliminating the need for pull-up/pull-down resistors and
reducing overall system operating power dissipation.
Ordering Information
PART NUMBER
CP82C86H-5 CP82C86H 20 Ld
IP82C86H-5 IP82C86H -40oC to +85oC E20.3
CS82C86H-5 CS82C86H 20 Ld
IS82C86H-5 IS82C86H -40oC to +85oC N20.35
CD82C86H-5 CD82C86H 20 Ld
ID82C86H-5 ID82C86H -40oC to +85oC F20.3
MD82C86H-5/B - -55oC to
59628757701RA
MR82C86H-5/B - 20 Pad
596287577012A
OE) permits simple interface to the 80C86,
PACK-
AGE TEMP. RANGE
0oC to +70oC E20.3
PDIP
0oC to +70oC N20.35
PLCC
0oC to +70oC F20.3
CERDIP
+125oC
- SMD # F20.3
-55oC to
CLCC
- SMD # J20.A
+125oC
PKG.
NO.5MHz 8MHz
F20.3
J20.A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
4-317
File Number 2977.1
Pinouts
82C86H82C86H
82C86H (PDIP, CERDIP)
TOP VIEW
1
A
0
2
A
1
3
A
2
4
A
3
5
A
4
6
A
5
A
7
6
8
A
7
9
OE
10
GND
82C86H (PLCC, CLCC)
TOP VIEW
20
V
CC
B
19
0
18
B
1
17
B
2
16
B
3
15
B
4
14
B
5
13
B
6
12
B
7
T
11
4
A
3
A
5
4
6
A
5
A
7
6
A
8
7
A2A1A
9
OE
0
10 11 12 13
T
GND
CC
V
7B6
B
0
B
193 2 201
H = Logic One
18
17
16
15
14
L = Logic Zero
B
1
I = Input Mode
B
2
O = Output Mode
X = Don’t Care
B
3
Hi-Z = High Impedance
B
4
B
5
PIN DESCRIPTION
A
0-A7
B
0-B7
TRUTH TABLE
T
OE A B
X H Hi-Z Hi-Z
HL IO
LLOI
PIN NAMES
Local Bus Data I/O Pins
System Bus Data I/O Pins
T Transmit Control Input
OE Active Low Output Enable
4-318
82C86H
82C86H
Functional Diagram
A0
B0
A1
A2
A3
A4
A5
A6
A7
OE
B1
B2
B3
B4
B5
B6
B7
T
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
V
and GND when the signal is at or near the input switch-
CC
ing threshold. Additionally, if the driving signal becomes high
impedance (“float” condition), it could create an indeterminate logic state at the inputs and cause a disruption in
device operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the de vice is
disabled (
inputs disconnect the input circuitry from the V
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from V
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
D.C. input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V
V
IL
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the transparent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
OE = logic one for the 82C86H/87H). These gated
and
CC
to GND occurs during input transitions and invalid
CC
or maximum
IH
conditions. This is due to the operation of the input cir-
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C86H/87H data
sheet is determined by:
ICLdv dt⁄()=
Assuming that all outputs change state at the same time and
that dv/dt is constant;
VCC 80%×()
------------------------------------ -
=
IC
L
tR tF⁄
where tR = 20ns, V
= 5.0V, CL = 300pF on each eight out-
CC
puts.
12–
I 80 300 10
480mA=
DATA IN
DATA IN
××()5.0V 0.8×()20 109–×()⁄×=
V
CC
P
STB
OE
FIGURE 2. 82C86H/87H GATED INPUTS
N
FIGURE 1. 82C82/83H
V
CC
P
N
V
CC
P
P
N
N
V
CC
P
P
N
N
This current spike may cause a large negative voltage spike
on V
which could cause improper operation of the device.
CC
To filter out this noise, it is recommended that a 0.1µF
ceramic disc capacitor be placed between V
CC
each device, with placement being as near to the device as
possible.
(EQ. 1)
(EQ. 2)
(EQ. 3)
INTERNAL
DAT A
INTERNAL
DAT A
and GND at
4-319
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