Intersil Corporation 82C85 Datasheet

82C85

March 1997

Features

• Generates the System Clock For CMOS or NMOS Microprocessors and Peripherals

• Complete Control Over System Operation for Very Low System Power

- Stop-Oscillator

- Low Frequency

- Stop-Clock

- Full Speed Operation

• DC to 25MHz Operation (DC to 8MHz System Clock)

• Generates 50% and 33% Duty Cycle Clocks (Synchronized)

• Uses a Parallel Mode Crystal Circuit or External Frequency Source

• TTL Compatible Inputs/Outputs

• 24 Lead Slimline Dual-In-Line or 28 Pad Square LCC Package Options

• Single 5V Power Supply

• Operating Temperature Range

- C82C85 . . . . . . . . . . . . . . . . . . . . . . . . . .0

- I82C85 . . . . . . . . . . . . . . . . . . . . . . . . . -40

- M82C85 . . . . . . . . . . . . . . . . . . . . . . . -55

C to +70oC

C to +85oC

C to +125oC

Ordering Information

PART NUMBER PACKAGE TEMP. RANGE PKG. NO.

CS82C85 28 Ld PLCC 0oC to +70oC N28.45 IS82C85 -40oC to +85oC N28.45 CD82C85 24 Ld CERDIP 0oC to +70oC F24.3 ID82C85 -40oC to +85oC F24.3 MD82C85/B -55oC to +125oC F24.3 MR82C85/B 28 Pad CLCC -55oC to +125oC J28.A

CMOS Static Clock Controller/Generator

Description

The Intersil 82C85 Static CMOS Clock Controller/Generator provides complete control of static CMOS system operating modes and supports full speed, slow, stop-clock and stop-oscillator operation. While directly compatible with the Intersil 80C86 and 80C88 16-bit Static CMOS Microprocessor Family, the 82C85 can also be used for general system clock control.

For static system designs, separate signals are provided on the 82C85 for stop (S0, S1, control of the crystal oscillator and system clocks. A single control line (

SLO/FST) determines 82C85 fast (cr ystal/EFI frequency divided by 3) or slow (crystal/EFI frequency divided by 768) mode operation. Automatic maximum mode 80C86 and 80C88 software HALT instr uction decode logic in the 82C85 enables software-based clock control. Restart logic insures valid clock start-up and complete synchronization of system clocks.

The 82C85 is manufactured using the Intersil advanced Scaled SAJI IV CMOS process. In addition to clock control circuitry, the 82C85 also contains a crystal controlled oscillator (up to 25MHz), clock generation logic, complete “Ready” synchronization and reset logic. This permits the designer to tailor the system power-performance product to provide optimum performance at low power levels.

S2/STOP) and start (START)

Pinouts

24 LEAD CERDIP

TOP VIEW

ASYNC

EFI

OSC

RES

RESET

S2/STOP

READY

4-297

PCLK AEN1

RDY1

RDY2

AEN2

CLK

GND CLK50 START

1 2 3 4 5 6 7 8

9 10 11 12

CSYNC

READY

SLO/FST

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207

28 LEAD PLCC, CLCC

TOP VIEW

PCLK

AEN1

3 2

RDY1

6 7

RDY2

AEN2

CLK

GND

12 13

CLK50

14 151617

START

CSYNC

28 27 26

SLO/FST

ASYNC

EFI

F/C

OSC

RES

RESET

S2/STOP

File Number 2976.1

82C85

Pin Descriptions

DIP PIN

SYMBOL

X1 X2

EFI 20 I EXTERNAL FREQUENCY IN: When F/C is HIGH, CLK is generated from the EFI input signal. This

F/C 19 I FREQUENCY/CRYSTAL SELECT: F/C selects either the crystal oscillator or the EFI input as the

START 11 I A low-to-high transition on START will restart the CLK, CLK50 and PCLK outputs after the appro-

S2/STOP

SLO/FST 12 I SLO/FST is a level-triggered input. When HIGH, the CLK and CLK50 outputs run at the maximum

CLK 8 O PROCESSOR CLOCK: CLK is the clock output used by the 80C86 or 80C88 processor and other

CLK50 10 O 50% DUTY CYCLE CLOCK: CLK50 is an auxiliary clock with a 50% duty cycle and is synchronized

PCLK 2 O PERIPHERAL CLOCK: PCLK is a peripheral clock signal whose output frequency is equal to the

OSC 18 O OSCILLATOR OUTPUT: OSC is the output of the internal oscillator circuitry. Its frequency is equal

NUMBER TYPE DESCRIPTION

23 22

13 14 15

CRYSTAL CONNECTIONS: X1 and X2 are the crystal oscillator connections. The crystalfrequency

must be 3 times the maximum desired processor clock frequency. X1 is the oscillator circuit input and X2 is the output of the oscillator circuit. If the crystal inputs are not used, X1 must be tied to VCC or GND, and X2 should be left open.

input signal should be a square wave with a frequency of three times the maximum desired CLK output frequency. If the crystal inputs are not used. XI must be tied to VCC or GND, and X2 should be left open.

main frequency source. When F/C is LOW, the 82C85 clocks are derived from the crystal oscillator circuit. When F/C is HIGH, CLK is generated from the EFI input. F/C cannot be dynamically switched during normal operation.

priate restart sequence is completed. When in the crystal mode (F/C LOW) with the oscillator stopped. The oscillator will be restarted

when a Start command is received. The CLK, CLK50 and PCLK outputs will start after the oscillator input signal (X1) reaches the Schmitt trigger input threshold and 8K internal counter reaches terminal count. If F/C is HIGH (EFI mode), CLK, CLK50 and PCLK will restart within 3 EFI cycles after START is recognized.

The 82C85 will restart in the same mode (SLO/FST) in which it stopped. A high level on START disables the STOP mode.

S2/STOP, S1, SO are used to stop the 82C85 clock outputs (CLK, CLK50, PCLK) and are sampled

by the rising edge of CLK, CLK50 and PCLK are stopped by S2/STOP, S1, SO being in the LHH

state on the low-to-high transition of CLK. This LHH state must follow a passive HHH state occurring on the previous low-to-high CLK transition. CLK and CLK50 stop in the high state when F/C is low and may stop in either the high or low state when F/C is high. PCLK stops in its current state (high or low).

When in the crystal mode (F/C) low and a STOP command is issued, the 82C85 oscillator will stop along with the CLK, CLK50 and PCLK outputs. When in the EFI mode, only the CLK, CLK50 and PCLK outputs will be halted. The oscillator circuit if operational, will continue to run. The oscillator and/or clock is restarted by the ST ART input signal going true (HIGH) or the reset input (RES) going low.

frequency (crystal or EFI frequency divided by 3). When LOW, CLK and CLK50 frequencies are equal to the crystal or EFI frequency divided by 768. SLO/FST changes are internally synchronized so proper CLK and CLK50 phase relationships are maintained and minimum pulse width specifications are met. START and STOP control of the oscillator or EFI is available in either the SLOW or FAST frequency modes. The SLO/FST input must be held LOW for at least 195 OSC/EFI clock cycles before it will be recognized. This eliminates unwanted frequency changes which could be caused by glitches or noise transients. The SLO/FST input must be held HIGH for at least 6 OSC/EFI clock pulses to guarantee a transition to FAST mode operation.

peripheral devices. When SLO/FST is high, CLK has an output frequency which is equal to the crystal or EFI input frequency divided by three. When SLO/FST is low, CLK has an output frequency which is equal to the crystal or EFI input frequency divided by 768. CLK has a 33% duty cycle.

to the falling edge of CLK. When SLO/FST is high, CLK50 has an output frequency which is equal to the crystal or EFI input frequency divided by 3. When SLO/FST is low, CLK50 has an output frequency equal to the crystal or EFI input frequency divided by 768.

crystal or EFI input frequency divided by 6 and has a 50% duty cycle. PCLK frequency is unaffected by the state of the SLO/FST input.

to that of the crystal oscillator circuit. OSC is unaffected by the state of the SLO/FST input. When the 82C85 is in the crystal mode (F/C low) and a STOP command is issued, the OSC output will stop in the HIGH state. When the 82C85 is in the EFI mode (F/C HIGH, the oscillator (if operational) will continue to run when a STOP command is issued and OSC remains active.

4-298

82C85

Pin Descriptions

(Continued)

DIP PIN

SYMBOL

NUMBER TYPE DESCRIPTION

RES 17 I RESET IN: RES is an active LOW signal which is used to generate RESET. The 82C85 provides a

Schmitt trigger input so that an RC connection can be used to establish the power-up reset of proper duration. RES starts crystal oscillator operation.

RESET 16 O RESET: RESET is an active HIGH signal which is used to reset the 80C86 family processors. Its

timing characteristics are determined by RES. RESET is guaranteed to be HIGH for a minimum of 16 CLK pulses after the rising edge of RES.

CSYNC 1 I CLOCK SYNCHRONIZATION: CSYNC is an active HIGH signal which allows multiple 82C85 and

82C84A to be synchronized to provide multiple in-phase clock signals When CSYNC is HIGH, the internal counters are reset and force CLK, CLK50 and PCLK into a HIGH state. When CSYNC is LOW, the internal counters are allowed to count and the CLK, CLK50 and PCLK outputs are active. CSYNC must be externally synchronized to EFI.

AEN1 AEN2

3 7

ADDRESS ENABLE: AEN is an active LOW signal. AEN serves to qualify its respective Bus Ready

Signal (RDY1 or RDY2).AEN1 validates RDY1 whileAEN2 validates RDY2. TwoAENsignal inputs are useful in system configurations which permit the processor to access two Multi-Master System Buses.

RDY1 RDY2

4 6

BUS READY: (Transfer Complete). RDY is an active HIGH signal which is an indication from a de-

vice located on the system data bus that data has been received, or is available RDY1 is qualified by AEN1 while RDY2 is qualified by AEN2.

ASYNC 21 I READY SYNCHRONIZATION SELECT: ASYNC is an input which defines the synchronization

mode of the READY logic. When ASYNC is LOW, two stages of READY synchronization are provided. When ASYNC is left open or HIGH a single stage of READY synchronization is provided.

READY 5 O READY: READY is an active HIGH signal which is the synchronized RDY signal input.

GND 9 I Ground

24 I VCC: is the +5V power supply pin. A 0.1mF capacitor between VCC and GND is recommended.

Functional Block Diagram

RES

(17)

START

(11)

CSYNC

(1)

SLO/FST

(12)

(19)

EFI

(20)

(22)

(23)

S2/STOP

(15)

(14)

(13)

RDY1

(4)

AEN1

(3)

AEN2

(7)

RDY2

(6)

ASYNC

(21)

RESTART

LOGIC

EXTERNAL

FREQ.

SELECT

OSC

OSCILLATOR

STOP LOGIC

READY

SELECT

RESTART

SELECTED

OSC

HALT

RESET PULSE

CONDITIONING

LOGIC

SYNC

LOGIC

SPEED SELECT

DIV 256 OR DIV 1

READY

SYNC

MASTER OSC

CLOCK

LOGIC

(DIVIDE

BY 3)

PERIPHERAL

CLOCK

(DIVIDE BY 6)

(24)

GND (9)

RESET

CLK

CLK50

PCLK

OSC

READY

(16)

(8)

(10)

(2)

(18)

(5)

4-299

82C85

Functional Description

The 82C85 Static Clock Controller/Generator provides simple and complete control static CMOS system operating modes. The 82C85 supports full speed, slow, stop-clock and stop-oscillator operation. While it is directly compatible with the Intersil 80C86 and 80C88 CMOS 16-bit static microprocessors, the 82C85 can also be used for general purpose system clock control.

The 82C85 pinout is a superset of the 82C84A Clock Generator/Driver. 82C85 pins 1-9, 16-24 are compatible with 82C84A pins 1-9, 10-18 respectively. An 82C84A can be placed in the upper 18 pins of an 82C85 socket and it will operate correctly (without the ability to control the clock and oscillator operation.) This allows dual design for simple system upgrades. The 82C85 will also emulate an 82C84A when pins 11-15 on the 82C85 are tied to V

For static systems designs, separate signals are provided on the 82C85 for stop and start control of the crystal oscillator and clock outputs. A single control line determines 82C85 fast (crystal/EFI frequency divided by 3) or slow (crystal/EFI frequency divided by 768) mode operation. The 82C85 also contains a crystal controlled oscillator, clock generation logic, complete “Ready” synchronization and reset logic.

Automatic 80C86/88 software HALT instruction decode logic is present to ease the design of software-based clock control systems and provide complete software control of STOP mode operation. Restart logic insures valid clock start-up and complete synchronization of CLK, CLK50 and PCLK.

Static Operating Modes

In static CMOS system design, there are four basic operating modes. The 82C85 Static Clock Controller supports each of them. These modes are: FAST, SLOW, STOP-CLOCK and STOP-OSCILLATOR. Each has distinct power and performance characteristics which can be matched to the needs of a particular system at a speciﬁc time (See Table 1).

Keep in mind that a single system may require all of these operating modes at one time or another during normal operation. A design need not be limited to a single operating mode or a speciﬁc combination of modes. The appropriate operating mode can be matched to the power-performance level needed at a speciﬁc time or in a particular circumstance.

Reset Logic

The 82C85 reset logic provides a Schmitt trigger input (

RES) and a synchronizing ﬂip-ﬂop to generate the reset timing. The reset signal is synchronized to the falling edge of CLK. A simple RC network can be used to provide power-on reset by utilizing this function of the 82C85.

When in the crystal oscillator (F/

C = LOW) or the EFI (F/C = HIGH) mode, a LOW state on the RES input will set the RESET output to the HIGH state. It will also restart the oscillator circuit if it is in the idle state. The RESET output is guaranteed to stay in the HIGH state for a minimum of 16 CLK cycles after a low-to-high transition of the

RES input.

An oscillator restart count sequence will not be disturbed by RESET if this count is already in progress. After the restart counter expires, the RESET output will stay HIGH at least for 16 periods of CLK before going LOW. RESET can be kept high beyond this time by a continuing lo w input on the

C is low (crystal oscillator mode), a low state on RES

If F/

RES input.

starts the crystal oscillator circuit. The stopped outputs remain inactive, until the oscillator signal amplitude reaches the X1 Schmitt trigger input threshold voltage and 8192 cycles of the crystal oscillator output are counted by an internal counter. After this count is complete, the stopped outputs (CLK, CLK50, PCLK, and OSC) start cleanly with the proper phase relationships.

This 8192 count requirement insures that the CLK, CLK50 and PCLK outputs will meet minimum clock requirements and will not be affected by unstable oscillator characteristics which may exist during the oscillator start-up sequence. This sequence is also followed when a START command is issued while the 82C85 oscillator is stopped.

Oscillator/Clock Start Control

Once the oscillator is stopped (or committed to stop) or at poweron, the restart sequence is initiated by a HIGH state on ST AR T or LOW state on

RES. If F/C is HIGH, then restart occurs immediately after the START or RES input is synchronized internally. This insures that stopped outputs (CLK, PCLK, OSC and CLK50) start cleanly with the proper phase relationship.

If F/

C is low (crystal oscillator mode), a HIGH state on the

START input or a low state on

RES causes the crystal oscil-

lator to be restarted. The stopped outputs remain stopped,

TABLE 1. STATIC SYSTEM OPERATING MODE CHARACTERISTICS

OPERATING

MODE DESCRIPTION POWER LEVEL PERFORMANCE

Stop-Oscillator All system clocks and main clock oscillator are

stopped

Stop-Clock System CPU and peripherals clocks stop but main

clock oscillator continues to run at rated frequency

Slow System CPU clocks are slowed while peripheral clock

and main clock oscillator run at rated frequency

Fast All clocks and oscillators run at rated frequency Highest Power Fastest response

Maximum Savings Slowest response due to oscillator

restart time

Reduced System Power

Power Dissipation Slightly Higher Than Stop-Clock

Fast restart-no oscillator restart time

Continuous operation at low frequency

4-300

82C85

until the oscillator signal amplitude reaches the X1 Schmitt trigger input threshold voltage and 8192 cycles of the crystal oscillator output are counted by an internal counter. After this count is complete, the stopped outputs (CLK, CLK50, PCLK, and OSC) start cleanly with the proper phase relationships.

Typically, any input signal which meets the START input timing requirements can be used to start the 82C85. In many cases, this would be the INT output from an 82C59A CMOS Priority Interrupt Controller (See Figure 1). This output, which is active high, can be connected to both the 82C85 START pin and to the appropriate interrupt request input on the microprocessor.

80C86/88

INTR

82C85

82C59A

INT

START

S2/STOP SLO/FST

CLK

S0 S1

PA0 PA1

82C55A

CLK

When the INT output becomes active, the oscillator/clock circuit on the 82C85 will restart. Upon completion of the appropriate restart sequence, the CLK signal to the CPU will become active. The CPU can then respond to the still pending interrupt request.

If the 82C59A/82C85 restart combination is used in conjunction with an 82C55A

STOP control, the 82C55A must be initialized prior to the 82C59A after reset. The 82C59A interrupt output is driven high at reset, causing the 82C85 to remain in the START mode regardless of the state of the S2/STOP input. This will avoid stopping the 82C85 due to negative transitions on the

S2/STOP input which may occur during a mode change on the 82C55A or during the operation of any peripheral I/O device prior to initialization.

Another method of insuring proper operation of the START function upon reset or system initialization is to bias the S2/STOP input low with an external pull-down resistor. The S2/STOP input will remain low until driven high by the 82C55A port pin or by external logic. This insures that the 82C85 STOP command (HHH prior to LHH requirement on the status inputs) will not be satisﬁed. To minimize power dissipation in this case (using a pulldown resistor), the S2/STOP input should be normally LOW and pulsed HIGH to develop the necessary HHH-to-LHH manner, the output driving the

STOP sequence. In this

S2/STOP input will be normally LOW and will not be driving to the opposite state of the pull-down resistor.

Fast Mode

FIGURE 1. CMOS PERIPHERAL CONTROL OF 82C85 STOP,

START AND SLOW/FAST OPERATIONS

The most common operating mode for a system is the FAST mode. In this mode, the 82C85 operates at the maximum frequency determined by the main oscillator or EFI frequency.

TABLE 2. TYPICAL SYSTEM POWER SUPPLY CURRENT FOR STATIC CMOS OPERATING MODES

FAST SLOW STOP-CLOCK STOP-OSC

CPU Frequency 5MHz 20 KHz DC DC XTAL Frequency 15MHz 15MHz 15MHz DC ICC 82C85 24.7mA 16.9mA 14.1mA 24.4mA 80C88 23.8mA 173.0mA 106.6mA 106.6mA 82C82 1.7mA 6.5mA 1.0mA 1.0mA 82C86 1.4mA 14.0mA 1.0mA 1.0mA 82C88 3.5mA 14.3mA 3.8mA 3.8mA 82C52 151.2mA 72.0mA 1.0mA 1.0mA 82C54 943.0mA 915.0mA 3.5mA 1.0mA 82C55A 3.2mA 1.2mA 1.0mA 1.0mA 82C59A 580.0mA 520.0mA 1.0mA 1.0mA 74HCXX + other 2.9mA 10.0mA 90.0mA 90.0mA HM-6516 820.0mA 32.0mA 1.9mA 1.9mA HM-6616 6.3mA 52.5mA 12.0mA 12.0mA Total 66.8mA 18.9mA 14.3mA 244.7mA

All measurements taken at room temperature, V frequency of operation.

= +5.0V. Power supply current levels will be dependent upon system configuration and

4-301

82C85

FAST mode operation is enabled by each of two conditions:

SLO/FST input is HIGH and a START or reset

• The command is issued

SLO/FST input is held HIGH for at least 6 oscillator or

• The EFI cycles.

Alternate Operating Modes

Using alternate modes of operation (slow, stop-clock, stoposcillator) will reduce the average system operating power dissipation in a static CMOS system (See Table 2). This does not mean that system speed or throughput must be reduced. When used appropriately , the slo w, stopclock, stoposcillator modes can make your design more power efﬁcient while maintaining maximum system performance.

Stop-Oscillator Mode

When the 82C85 is stopped while in the crystal mode (F/ LOW), the oscillator, in addition to all system clock signals (CLK, CLK50 and PCLK), are stopped. CLK and CLK50 stop in the high state. PCLK stops in it’s current state (high or lo w).

With the oscillator stopped, 82C85 power drops to it’s lowest level. All clocks and oscillators are stopped. All devices in the system which are driven by the 82C85 go into the lowest power standby mode. The 82C85 also goes into standb y and requires a power supply current of less than 100µA.

Stop-Clock Mode

When the 82C85 is in the EFI mode (F/

C HIGH) and a STOP command is issued, all system clock signals (CLK, CLK50, and PCLK) are stopped. CLK and CLK50 stop in the high state when F/ state when F/

C is low and may stop in either the high or low C is high. PCLK stops in its current state (high

or low). The 82C85 can also provide it’s own EFI source simply by

connecting the OSC output to the EFI input and pulling the F/C input HIGH. This puts the 82C85 into the External Frequency Mode using it’s own oscillator as an exter nal source signal (See Figure 2). In this conﬁguration, when the 82C85 is stopped in the EFI mode, the oscillator continues to run. Only the clocks to the CPU and peripherals (CLK, CLK50 and PCLK) are stopped.

Oscillator/Clock Stop Operation

Three control lines determine when the 82C85 clock outputs or oscillator will stop. These are S0, S1 and

S2/STOP. These three lines are designed to connect directly to the MAXimum mode 80C86 and 80C88 status lines or to be driven by external I/O signals (such as an 82C55A output port).

In the MAXimum mode conﬁguration, the 82C85 will automatically recognize a software HALT command from the 80C86 or 80C88 and stop the system clocks or oscillator. This allows complete software control of the

STOP function.

If the 80C86 or 80C88 is used in the MINimum mode, the 82C85 can be controlled using the

S2/STOP input (with S0 and S1 held high). This can be done using an external I/O control line, such as from an 82C55A or by decoding the state of the 80C86 MINimum mode status signals.

82C85 status inputs

rising edge of CLK. The oscillator (F/ outputs are stopped by

S2/STOP, S1, S0 are sampled on the

C LOW only) and clock

S2/STOP, S1, S0 being in the LHH state on a low-to-high transition of CLK. This LHH state must follow a passive HHH state occurring on the previous low-tohigh CLK transition. CLK and CLK50 will stop in the logic HIGH state after two additional complete cycles of CLK. PCLK stops in it’s current state (HIGH or LOW). This is true for both SLOW and FAST mode operation.

80C86/88 Maximum Mode Clock Control

The 82C85

STOP function has been optimized for 80C86/88 MAXimum mode operation. In this mode, the three 82C85 status inputs (

S2/STOP, S1, S0) are connected directly to the MAXimum mode status lines (S2, S1, S0) of the Intersil 80C86 or 80C88 static CMOS microprocessors (See Figure

3). When in the MAXimum mode, the 80C86/88 status lines

identify which type of bus cycle the CPU is starting to execute. 82C85

S2/STOP, S1 and S0 control input logic will recognize a valid MAXimum mode software HALT executed by the 80C86 or 80C88. Once this state has been recognized, the 82C85 stops the clock (F/

C HIGH) and oscillator (F/C

LOW) operation.

X1 X2

EFI

STOP

CONTROL

FIGURE 2. STOP-CLOCK MODE USING 82C85 IN EFI MODE

WITH OSCILLATOR AS FREQUENCY SOURCE

S2/STOP S1 S0

OSC

START

START CONTROL

S2 S1 S0

MN/

FIGURE 3. 82C85 STOP CONTROL USING 80C86/88

MAXIMUM MODE STATUS LINES

4-302

S2/STOP S1 S0

82C8580C86/88

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