Intersil Corporation 82C83H Datasheet
82C83H
March 1997
Features
• Full 8-Bit Parallel Latching Buffer
• Bipolar 8283 Compatible
• Three-State Inverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .25ns Max
• Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Operating Temperature Ranges
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0
- I82C83H. . . . . . . . . . . . . . . . . . . . . . . . -40
- M82C83H. . . . . . . . . . . . . . . . . . . . . . -55
o
C to +70oC
o
C to +85oC
o
C to +125oC
CMOS Octal Latching Inverting Bus Driver
Description
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
Ordering Information
PART NO. PACKAGE TEMP RANGE PKG. NO
CP82C83H 20 Ld PDIP 0
IP82C83H -40
CS82C83H 20 Ld PLCC 0
IS82C83H -40
CD82C83H 20 Ld CERDIP 0
ID82C83H -40
MD82C83H/B 0
8406702RA SMD# -55
MR82C83H/B 20 Pad CLCC -55
84067022A SMD# -55
o
C to +70oC E20.3
o
C to +85oC E20.3
o
C to +70oC N20.35
o
C to +85oC N20.35
o
C to +70oC F20.3
o
C to +85oC F20.3
o
C to +70oC F20.3
o
C to +125oC F20.3
o
C to +125oC J20.A
o
C to +125oC J20.A
Pinouts
82C83H (PDIP, CERDIP)
TOP VIEW
1
DI
0
DI
2
1
DI
3
2
DI
4
3
DI
5
4
DI
6
5
DI
7
6
8
DI
7
9
OE
GND
10
TRUTH TABLE
STB OE DI DO
X H X HI-Z
HLLH
HLHL
↓ LX†
H = Logic One
L = Logic Zero
X = Don‘t Care
HI-Z = High Impedance
↓ = Negative Transition
† = Latched to Value of Last
20
19
18
17
16
15
14
13
12
11
V
DO
DO
DO
DO
DO
DO
DO
DO
STB
Data
CC
0
1
2
3
4
5
6
7
82C83H (PLCC, CLCC)
TOP VIEW
DI2DI1DI0VCCDO
4
DI
3
DI
5
4
6
DI
5
DI
7
6
DI
8
7
9
10 11 12 13
OE
GND
STB
DO7DO
PIN NAMES
PIN DESCRIPTION
DI0 - DI
7
DO0 - DO
Data Input Pins
Data Output Pins
7
STB Active High Strobe
OE Active Low Output Enable
0
193 2 201
18
DO
1
17
DO
2
16
DO
3
15
DO
4
DO
14
5
6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
4-281
File Number 2971.1
82C83H
Functional Diagram
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
STB
DQ
CLK
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
V
and GND when the signal is at or near the input switch-
CC
ing threshold. Additionally, if the driving signal becomes high
impedance (``float'' condition), it could create an indeterminate logic state at the inputs and cause a disruption in
device operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the de vice is
disabled (
OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the V
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from V
to GND occurs during input transitions and invalid
CC
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
STB
DATA IN
V
CC
P
N
FIGURE 1. 82C82/83H
V
P
P
N
N
D.C. input voltage le vels can also cause an increase in ICC if
these input levels approach the minimum V
V
conditions. This is due to the operation of the input cir-
IL
cuitry in its linear operating region (partially conducting
CC
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
OE
CC
INTERNAL
DAT A
or maximum
IH
and
state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the transparent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
V
CC
P
OE
DATA IN
V
CC
P
N
P
N
N
INTERNAL
DAT A
FIGURE 2. 82C86H/87H GATED INPUTS
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C83H data sheet
is determined by
I = C
(dv/dt)
L
Assuming that all outputs change state at the same time and
that dv/dt is constant;
V
80 percent×()
CC
--------------------------------------------------------
IC
=
L
where t
R
⁄
t
RtF
= 20ns, VCC = 5.0V, CL = 300pF on each eight out-
puts.
I = (8 x 300 x 10
-12
) x (5.0V x 0.8)/(20 x 10-9) = 480mA
This current spike may cause a large negative voltage spike on
V
which could cause improper operation of the device. To fil-
CC
ter out this noise, it is recommended that a 0.1µF ceramic disc
capacitor be placed between V
and GND at each device,
CC
with placement being as near to the device as possible.
ALE
MULTI-
PLEXED
BUS
ICC
DATA IN
FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS
ADDRESS ADDRESS
STB
V
CC
P
N
V
CC
P
P
N
N
INTERNAL
DAT A
(EQ. 1)
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