Intersil Corporation 82C82 Datasheet
82C82
March 1997
Features
• Full Eight-Bit Parallel Latching Buffer
• Bipolar 8282 Compatible
• Three-State Noninverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.
• Gated Inputs:
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA
• Operating Temperature Ranges
- C82C82 . . . . . . . . . . . . . . . . . . . . . . . . . .0
- I82C82 . . . . . . . . . . . . . . . . . . . . . . . . . -40
- M82C82 . . . . . . . . . . . . . . . . . . . . . . . -55
o
C to +70oC
o
C to +85oC
o
C to +125oC
CMOS Octal Latching Bus Driver
Description
The Intersil 82C82 is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon
gate CMOS process (Scaled SAJI IV). The 82C82 provides
an eight-bit parallel latch/buffer in a 20 pin package. The
active high strobe (STB) input allows transparent transfer of
data and latches data on the negative transition of this signal. The active low output enable (
face to state-of-the-art microprocessor systems.
Ordering Information
PART NUMBER TEMP. RANGE PACKAGE PKG. NO.
CP82C82 0oC to +70oC 20 Ld PDIP E20.3
IP82C82 -40oC to +85oC
CS82C82 0oC to +70oC 20 Ld PLCC N20.35
IS82C82 -40oC to +85oC
CD82C82 0oC to +70oC 20 Ld CERDIP F20.3
ID82C82 -40oC to +85oC
MD82C82/B -55oC to +125oC
8406701RA SMD #
MR82C82/B -55oC to +125oC 20 Pad CLCC J20.A
84067012A SMD #
OE) permits simple inter-
Pinouts
82C82 (PDIP, CERDIP)
DI
0
DI
1
DI
2
DI
3
DI
4
DI
5
DI
6
DI
7
OE
GND
10
1
2
3
4
5
6
7
8
9
TOP VIEW
82C82 (PLCC, CLCC)
TOP VIEW
CC
V
7DO6
DO
0
DO
193 2 201
18
DO
1
17
DO
2
16
DO
3
15
DO
4
DO
14
5
DI2DI1DI
V
20
CC
DO
19
0
DO
18
1
DO
17
2
DO
16
3
DO
15
4
DO
14
5
DO
13
6
12
DO
7
11
STB
4
DI
3
DI
5
4
6
DI
5
DI
7
6
DI
8
7
9
OE
0
10 11 12 13
STB
GND
TRUTH TABLE
STB OE DI DO
X H X Hi-Z
HLLL
HLHH
↓ LX †
H = Logic One
L = Logic Zero
X = Don’t Care
† = Latched to Value of Last
Data
Hi-Z = High Impedance
↓ = Neg. Transition
PIN NAMES
PIN DESCRIPTION
DI0-DI
DO
0
STB Active High Strobe
OE Active Low Output
Data Input Pins
7
-DO7Data Output Pins
Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
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File Number 2975.1
Functional Diagram
82C82
DI
DI
DI
DI
DI
DI
DI
DI
STB
O
1
2
3
4
5
6
7
D Q
CLK
Gated Inputs
During normal system operation of a latch, signals on the bus
at the device inputs will become high impedance or make
transitions unrelated to the operation of the latch. These unrelated input transitions switch the input circuitry and typically
cause an increase in power dissipation in CMOS devices by
creating a low resistance path between V
the signal is at or near the input switching threshold. Additionally, if the driving signal becomes high impedance (“float” condition), it could create an indeterminate logic state at the input
and cause a disruption in device operation.
The Intersil 82C8X Series of bus drivers eliminates these conditions by turning off data inputs when data is latched (STB =
logic zero for the 82C82/83H) and when the device is disab led
(OE = logic one for 82C86H/87H). These gated inputs dis-
connect the input circuitry from the V
supply pins by turning off the upper P-channel and lower Nchannel (see Figures 1, 2). No new current flow from V
GND occurs during input transitions and invalid logic states
from floating inputs are not transmitted. The next stage is held
to a valid logic lev el internal to the device.
and GND when
CC
and ground power
CC
CC
to
DO
0
DO
1
DO
2
DO
3
DO
4
DO
5
DO
6
DO
7
OE
DC input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V
V
conditions. This is due to the operation of the input cir-
IL
or maximum
IH
cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the trans
parent mode (STB = logic one). ICC remains below the maximum ICC standby specification of l0mA during the time
inputs are disabled, thereby, greatly reducing the average
power dissipation of the 82C8X series devices
Typical 82C82 System Example
In a typical 80C86/88 system, the 82C82 is used to latch
multiplexed addresses and the STB input is driven by ALE
(Address Latch Enable) (see Figure 3). The high pulse width
of ALE is approximately 100ns with a bus cycle time of
800ns (80C86/88 at 5MHz). The 82C82 inputs are active
only 12.5% of the bus cycle time. Average power dissipation
related to input transitioning is reduced by this factor also.
STB
DATA IN
V
CC
V
CC
P
N
V
CC
P
P
P
INTERNAL
DAT A
N
N
OE
DATA IN
P
V
CC
P
N
N
N
FIGURE 16. 82C82/83H FIGURE 17. 82C86H/87H GATED INPUTS
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INTERNAL
DAT A
82C82
Application Information
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C82 data sheet is
determined by:
IC
= (dv/dt) (EQ. 1)
L
Assuming that all outputs change state at the same time and
that dv/dt is constant;
= (EQ. 2)
IC
L
V
x 80%()
CC
-----------------------------------
tR/tF
(EQ. 3)
where tR = 20ns, V
= 5.0V, CL = 300pF on each of eight
CC
outputs.
I = 8 x 300 x 10
()x (5.0V x 0.8)/ 20 x 10
-12
()= 480mA
9–
(EQ. 4)
This current spike may cause a large negative voltage spike
on VCC, which could cause improper operation of the device.
To filter out this noise, it is recommended that a 0.1µF
ceramic disc decoupling capacitor be placed between V
CC
and GND at each device, with placement being as near to
the device as possible.
ALE
MULTIPLEXED
BUS
ICC
STB
ADDRESSADDRESS
DATA IN
FIGURE 18. SYSTEM EFFECTS OF GATED INPUTS
V
CC
P
N
V
CC
P
P
INTERNAL
DAT A
N
N
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