Intersil Corporation 82C50A Datasheet

March 1997

82C50A

CMOS Asynchronous

Communications Element

Features

• Single Chip UART/BRG

• DC to 625K Baud (DC to 10MHz Clock)

• Crystal or External Clock Input

• On Chip Baud Rate Generator 1 to 65535 Divisor Generates 16X Clock

• Prioritized Interrupt Mode

• Fully TTL/CMOS Compatible

• Microprocessor Bus Oriented Interface

• 80C86/80C88 Compatible

• Scaled SAJI IV CMOS Process

• Low Power - 1mA/MHz Typical

• Modem Interface

• Line Break Generation and Detection

• Loopback and Echo Modes

• Doubled Buffered Transmitter and Receiver

• Single 5V Supply

Ordering Information

TEMPERA TURE

P ACKAGE

PDIP 0 to +70 CP82C50A-5 E40.6

PLCC 0 to +70 CS82C50A-5 N44.65

CERDIP 0 to +70 CD82C50A-5 F40.6

RANGE (oC) 625K BAUD

-40 to +85 IP82C50A-5 E40.6

-40 to +85 IS82C50A-5 N44.65

-40 to +85 ID82C50A-5 F40.6

-55 to +125 MD82C50A-5/B F40.6

PKG.

NO.

Description

The 82C50A Asynchronous Communication Element (ACE) is a high performance programmable Universal Asynchronous Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single chip. Using Intersil’s advanced Scaled SAJI IV CMOS Process, the ACE will support data rates from DC to 625K baud (0-10MHz clock).

The ACE’s receiver circuitry converts star t, data, stop, and parity bits into a parallel data word. The transmitter circuitry converts a parallel data word into serial form and appends the start, parity, and stop bits. The word length is programmable to 5, 6, 7, or 8 data bits. Stop bit selection provides a choice of 1,1.5, or 2 stop bits.

The Baud Rate Generator divides the clock by a divisor programmable from 1 to 2 baud rates when using any one of three industry standard baud rate crystals (1.8432MHz, 2.4576MHz, or 3.072MHz). A programmable buffered clock output (BAUDOUT) provides either a buffered oscillator or 16X (16 times the data rate) baud rate clock for general purpose system use.

To meet the system requirements of a CPU interfacing to an asynchronous channel, the modem control signals CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs have been designed with full TTL/CMOS compatibility in order to facilitate mixed TTL/NMOS/CMOS system design.

-1 to provide standard RS-232C

RTS,

Functional Diagram

CSO CS1 CS2

ADS 25 A0

A1 A2 MR

DISTR DISTR

DOSTR DOSTR

D0 D1 D2 D3 D4 D5 D6

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207

MICROPROCESSOR INTERFACE

12 13 14

INTERRUPT

28 27 26 35

22 21

19 18

1 2 3 4 5 6 7

ID, & CONTROL

ENABLE,

24 CSOUT 23 DDIS

30 INTRPT

LINE STATUS

AND CONTROL

MODEM CONTROL

MODEM STATUS

UART

MODEM

RECEIVER

DIVISOR LATCH

AND BAUD RATE

GENERATOR

TRANSMITTER

10 SIN

9 RCLK 15 BAUDOUT 16 XTAL1

17 XTAL2 11 SOUT

32 RTS 33 DTR 34

OUT1

31 OUT2 36 CTS 37 DSR 38 DCD 39 RI

File Number 2958.1

Pinouts

D0 D1 D2 D3 D4 D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

XTAL1

XTAL2 DOSTR DOSTR

GND

82C50A

82C50A (PDIP, CERDIP)

TOP VIEW

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

RI DCD DSR CTS MR OUT1 DTR RTS OUT2 INTRPT NC A0 A1 A2 ADS CSOUT DDIS DISTR DISTR

D5 D6 D7

RCLK

SIN

SOUT

CS0 CS1 CS2

BAUDOUT

82C50A (PLCC)

TOP VIEW

D4D3D2D1D0NCVCCRI

7 8 9 10 11 12 13 14 15 16 17

20 21 22 23 24 25 261918

DOSTR

GND

XTAL1

XTAL2

44 43 42 41 40

123456

DISTR

DCD

DDIS

DSR

CTS

39 38 37 36 35 34 33 32 31 30 29

2827

ADS

CSOUT

MR OUT1 DTR RTS OUT2

INTRP

A0 A1 A2

Pin Description

82C50A

SYMBOL

DISTR,

DISTR

DOSTR,

DOSTR

D0-D7 1-8 I/O DATA BITS 0-7: The Data Bus provides eight, three-state input/output lines for the

A0, A1,

NUMBER TYPE

22 21

19 18

28, 27,

I I

ACTIVE

LEVEL DESCRIPTION

H L

H REGISTER SELECT: The address lines select the internal registers during CPU

DATA IN STROBE, DATA IN STROBE: DISTR, DISTR are read inputs which cause the 82C50A to output data to the data bus (D0-D7). The data output depends upon the register selected by the address inputs A0, A1, A2. The chip select inputs CS0, CS1, CS2 enable the DISTR, DISTR inputs.

Only an active DISTR or DISTR, not both, is used to receive data from the 82C50A during a read operation. If DISTR is used as the read input, DlSTR should be tied high. If DISTR is used as the active read input, DISTR should be tied low.

DAT A OUT STR OBE, DATA OUT STROBE: DOSTR,DOSTR are write inputs which cause data from the data bus (D0-D7) to be input to the 82C50A. The data input depends upon the register selected by the address inputs A0, A1, A2. The chip select inputs CS0, CS1, CS2 enable the DOSTR, DOSTR inputs.

Only an active DOSTR or DOSTR, not both, is used to transmit data to the 82C50A during a write operation. If DOSTR is used as the write input, DOSTR should be tied high. If DOSTR is used as the write input, DOSTR should be tied low.

transfer of data, control and status information between the 82C50A and the CPU. For character formats of less than 8 bits, D7, D6 and D5 are “don’t cares” for data write operations and 0 for data read operations. These lines are normally in a high impedance state except during read operations. D0 is the Least Signiﬁcant Bit (LSB) and is the ﬁrst serial data bit to be received or transmitted.

bus operations. See Table 1.

XTAL1,

XTAL2

SOUT 11 O SERIAL DATA OUTPUT: Serial data output from the 82C50A transmitter circuitry . A

GND 20 L GROUND: Power supply ground connection (VSS).

CTS 36 I L CLEAR TO SEND: The logical state of the CTS pin is reﬂected in the CTS bit of the

DSR 37 I L DATA SET READY: The logical state of the DSR pin is reﬂected in MSR(5) of the

DTR 33 O L DATA TERMINAL READY: The DTR pin can be set (low) by writing a logic 1 to

16 17

CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. XTAL1 can also be used as an external clock input, in which case XTAL2 should be left open.

Mark (1) is a logic one (high) and Space (0) is a logic zero (low). SOUT is held in the Mark condition when the transmitter is disabled, MR is true, the Transmitter Register is empty, or when in the Loop Mode. SOUT is not affected by the CTS input.

(MSR) Modem Status Register (CTS is bit 4 of the MSR, written MSR (4)). A change of state in the CTS pin since the previous reading of the MSR causes the setting of DCTS (MSR(O)) of the Modem Status Register. WhenCTS pin is ACTIVE (lo w), the modem is indicating that data on SOUT can be transmitted on the communications link. If CTS pin goes INACTIVE (high), the 82C50A should not be allowed to transmit data out of SOUT. CTS pin does not affect Loop Mode operation.

Modem Status Register. DDSR (MSR(1)) indicates whether the DSR pin has changed state since the previous reading of the MSR. When theDSR pin is ACTIVE (low), the modem is indicating that it is ready to exchange data with the 82C50A, while the DSR Pin INACTIVE (high) indicates that the modem is not ready for data exchange. The ACTIVE condition indicates only the condition of the local Data Communications Equipment (DCE), and does not imply that a data circuit as been established with remote equipment.

MCR(0), Modem Control Register bit 0. This signal is cleared (high) by writing a logic 0 to the DTR bit (MCR(0)) or whenever a MR ACTIVE (high) is applied to the 82C50A. When ACTIVE (low), DTR pin indicates to the DCE that the 82C50A is ready to receive data. In some instances, DTR pin is used as a power on indicator. The INACTIVE (high) state causes the DCE to disconnect the modem from the telecommunications circuit.

82C50A

Pin Description

SYMBOL

RTS 32 O L REQUEST TO SEND: TheRTS signal is an output used to enable the modem. The

BAUDOUT 15 O BAUDOUT: This output is a 16X clock out used for the transmitter section (16X =

OUT1 34 O L OUTPUT 1: This is a general purpose output that can be programmed ACTIVE

OUT2 31 O L OUTPUT 2: This is a general purpose output that can be programmed ACTIVE

RI 39 1 L RING INDICAT OR: When lo w ,RI indicates that a telephone ringing signal has been

NUMBER TYPE

(Continued)

ACTIVE

LEVEL DESCRIPTION

RTS pin is set low by writing a logic 1 to MCR (1) bit 1 of the Modem Control Register. TheRTS pin is reset high by Master Reset. When ACTIVE, the RTS pin indicates to the DCE that the 82C50A has data ready to transmit. In half duplex operations, RTS is used to control the direction of the line.

16 times the data rate). The BAUDOUT clock r ate is equal to the reference oscillator frequency divided by the speciﬁed divisor in the Baud Rate Generator Divisor Latches DLL and DLM. BAUDOUT may be used b y the Receiver section b y tying this output to RCLK.

(low) by settingVCR(2) (OUT1) of the Modem Control Register to a high level. The OUT1 pin is set high by Master Reset. TheOUT1 pin is INACTIVE (high) during loop mode operation.

(low) by setting MCR(3) (OUT1) of the Modem Control Register to a high lev el. The OUT2 pin is set high by Master Reset. The OUT2 signal is INACTIVE (high) during loop mode operation.

received by the modem or data set. The RI signal is a modem control input whose condition is tested by reading MSR(6) (RI). The Modem Status Register output TERI (MSR(2)) indicates whether the RI input has changed from a Low to High since the previous reading of the MSR. If the interrupt is enabled (IER (3) = 1) andRI changes from a Low to High, an interrupt is generated. The ACTIVE (low) state ofRI indicates that the DCE is receiving a ringing signal. RI will appear ACTIVE for approximately the same length of time as the ACTIVE segment of the ringing cycle. The INACTIVE state of RI will occur during the INACTIVE segments not detected by the DCE. This circuit is not disabled by the INACTIVE condition ofDTR.

DCD 38 I L DA TA CARRIER DETECT: When A CTIVE (low),DCD indicates that the data carrier

has been detected by the modem or data set. DCD is a modem input whose condition can be tested by the CPU by reading MSR(7) (DCD) of the Modem Status Register. MSR(3) (DDCD) of the Modem Status Register indicates whether the DCD input has changed since the previous reading of the MSR.DOD has no effect on the receiver. If the DCD changes state with the modem status interrupt enabled, an interrupt is generated.

When DCD is ACTIVE (low), the received line signal from the remote terminal is within the limits speciﬁed by the DCE manufacturer. The INACTIVE (high) signal indicates that the signal is not within the speciﬁed limits, or is not present.

MR 35 1 H MASTER RESET: The MR input forces the 82C50A into an idle mode in which all

serial data activities are suspended. The Modem Control Register (MCR) along with its associated outputs are cleared. The Line Status Register (LSR) is cleared except for the THRE and TEMT bits, which are set. The 82C50A remains in an idle state until programmed to resume serial data activities. The MR input is a Schmitt trigger input. See the DC Electrical Characteristics for Schmitt trigger logic input voltage levels. See Table 7 for a summary of Master Reset’s effect on 82C50A operation.

lNTRPT 30 O H INTERRUPT REQUEST: The lNTRPT output goes ACTIVE (high) when one of the

following interrupts has an ACTIVE (high) condition and is enabled by the Interrupt Enable Register: Receiver Error ﬂag, Received Data Available, Transmitter Holding Register Empty , and Modem Status . The lNTRPT is reset low upon appropriate service or a MR operation. See Figure 1. Interrupt Control Structure.

SIN 10 I H SERIAL DA T A INPUT : The SIN input is the serial data input from the communication

line or modem to the 82C50A receiver circuits. A mark (1) is high, and a space (0) is low. Data inputs on SIN are disabled when operating in the loop mode.

82C50A

Pin Description

SYMBOL

NUMBER TYPE

(Continued)

ACTIVE

LEVEL DESCRIPTION

40 H VCC: +5V positive power supply pin. A 0.1µA decoupling capacitor from VCC (pin

40) to GND (pin 20) is recommended.

CS0, CS1,

CS2

12,13,

I I

H, H,LCHIP SELECT: The Chip Select inputs act as enable signals for the write (DOSTR,

DOSTR) and read (DlSTR, DlSTR) input signals. The Chip Select inputs are latched by the ADS input.

NC 29 Do Not Connect

CSOUT 24 O H CHIP SELECT OUT: When ACTIVE (high), this pin indicates that the chip has been

selected by active CS0, CS1, andCS2 inputs. No data transfer can be initiated until CSOUT is a logic 1, ACTIVE (high).

DDIS 23 O H DRIVER DISABLE: This output is INACTIVE (low) when the CPU is reading data

from the 82C50A. An ACTIVE (high) Dells output can be used to disable an external transceiver when the CPU is reading data.

ADS 25 I L ADDRESS STROBE: When ACTIVE (low), ADS latches the Register Select (A0,

A1, A2) and Chip Select (CS0, CS1, CS2) inputs. An active ADS is required when the Register Select pins are not stable for the duration of the read or write operation, multiplexed mode . If not required, theADS input should be tied low , non-m ultiplex ed mode.

RCLK 9 I This input is the 16X Baud Rate Clock for the receiver section of the 82C50A. This

input may be provided from the BAUDOUT output or an external clock.

Block Diagram

+5V

GND

A0 A1 A2

CS0 CS1 CS2

ADS

(1 - 8)

(40) (20)

(28) (27) (26)

(12) (13) (14) (25) (35) (22) (21) (19) (18) (23) (24) (16)

(17)

D7 - D0

DISTR

DISTR DOSTR DOSTR

DDIS

CSOUT

XTAL1 XTAL2

DATA BUS

BUFFER

POWER

SUPPLY

SELECT

CONTROL

LOGIC

SCRATCH

RECEIVER BUFFER

LINE CONTROL

DIVISOR

LATCH (LS)

DIVISOR

LATCH (MS)

LINE STATUS

TRANSMITTER

HOLDING REGISTER

MODEM CONTROL

MODEM STATUS

INTERRUPT ENABLE

INTERRUPT IO

BAUD RATE

GENERATOR

INTERRUPT

CONTROL

LOGIC

RECEIVER SHIFT

RECEIVER

RECEIVER TIMING

& CONTROL

TRANSMITTER

TIMING & CONTROL

TRANSMITTER

SHIFT REGISTER

MODEM

CONTROL

LOGIC

(10)

(9)

(15)

(11)

(32) (33) (34)

(31) (36)

(37) (38) (39)

(30)

SIN

RCLK

BAUDOUT

SOUT

RTS DTR OUT1 OUT2

CTS DSR DCD RI

INTRPT

Accessible Registers

82C50A

The three types of internal registers in the 82C50A used in the operation of the device are control, status, and data registers. The control registers are the Bit Rate Select Register DLL and DLM, Line Control Register, Interrupt Enable Register and the Modem Control registers, while the status registers are the Line Status Registers and the Modem Status Register. The data registers are the Receiver Buffer Register and Transmitter Holding Register. The Address, Read, and Write inputs are used in conjunction with the Divisor Latch Access Bit in the Line Control Register (LCR(7)) to select the register to be written or read (see Table 1.). Individual bits within these registers are referred to by the register mnemonic and the bit number in parenthesis. An example, LCR(7) refers to Line Control Register Bit 7.

The Transmitter Buffer Register and Receiver Buffer Register are data registers holding from 5-8 data bits. If less than eight data bits are transmitted, data is right justiﬁed to the LSB. Bit 0 of a data word is always the ﬁrst serial data bit received and transmitted. The 82C50A data registers are double buffered so that read and write operations can be performed at the same time the UART is performing the parallel to serial and serial to parallel conversion. This provides the microprocessor with increased ﬂexibility in its read and write timing.

Line Control Register (LCR)

LCR7LCR6LCR5LCR4LCR3LCR2LCR1LCR

Word Length Select

Stop Bit Select

Parity Enable

Even Parity Select

Stick Parity 0 = Stick Parity Disabled

Break Control

Divisor Latch Access Bit

TABLE 1. ACCESSING 82C50A INTERNAL REGISTERS

DLAB A2 A1 A0 MNEMONIC REGISTER

0 0 0 0 RBR Receiver Buffer

0 0 0 0 THR Transmitter Holding

0 0 0 1 lER Interrupt Enable

X 0 1 0 IIR Interrupt Identifica-

tion Register

(read only) X 0 1 1 LCR Line Control Register X 1 0 0 MCR Modem Control

NOTE: X = “Don’t Care”, 0 = Logic Low, 1 = Logic High

0 0 = 5 Data Bits 0 1 = 6 Data Bits 1 0 = 7 Data Bits 1 1 = 8 Data Bits

0 = 1 Stop Bit 1 = 1.5 Stop Bits if 5 Data Bit Word Length is Selected 2 Stop Bits if

6, 7, or 8 Data Bit Word Length is Selected

0 = Parity Disabled 1 = Parity Enabled (Generated & Checked)

0 = Odd Parity When Parity is Enabled 1 = Even Parity When Parity is Enabled

1 = When Parity is Enabled Forces the Transmission and Checking

of a Parity Bit of a Known State. Parity Bit Forced to a Logic 1 if LCR (4) = 0 or to a Logic 0 If LCR (4) = 1.

0 = Break Disabled 1 = Break Enabled. The Serial Output (SOUT) is Forced to the

Spacing (Logic 0) State.

0 = Must be Low to Access the Receiver Buffer. Transmitter Holding

1 = Must be High to Access the Divisor Latches DLL and DLM of the

Baud Rate Generator During a Read or Write Operation.

82C50A

LINE CONTROL REGISTER (LCR)

The format of the data character is controlled by the Line Control Register. The contents of the LCR may be read, eliminating the need for separate storage of the line characteristics in system memory. The contents of the LCR are described below.

LCR Bits 0 thru 7

LCR (0) Word Length Select Bit 0 (WLS0) LCR (1) Word Length Select Bit 1 (WLS1) LCR (2) Stop Bit Select (STB) LOR (3) Parity Enable (PEN) LCR (4) Even Parity Select (EPS) LOR (5) Stick Parity LOR (6) Set Break LCR (7) Divisor Latch Access Bit (DLAB)

LCR(0) and LCR(1) Word Length Select Bit 0, Word Length Select Bit 1: The number of bits in each transmitted

or received serial character is programmed as follows:

LCR(1) LCR(0) WORD LENGTH

0 0 5 Bits 0 1 6 Bits 1 0 7 Bits 1 1 8 Bits

LCR(2) Stop Bit Select: LCR(2) speciﬁes the number of stop bits in each transmitted character. If LCR(2) is a logic 0, one stop bit is generated in the transmitted data. If LCR(2) is a logic 1 when a 5-bit word length is selected, 1.5 stop bits are generated. If LCR(2) is a logic 1 when either a 6-, 7-, or 8-bit word length is selected, two stop bits are generated. The receiver checks for two stop bits if programmed.

LCR(3) Parity Enable: When LCR(3) is high, a parity bit between the last data word bit and stop bit is generated and checked.

LCR(4) Even Parity Select: When parity is enabled (LCR(3) = 1), LCR(4) = 0 selects odd parity, and LCR(4) = 1 selects even parity.

LCR(5) Stick Parity: When parity is enabled (LCR(3) = 1), LCR(5) = 1 causes the transmission and reception of a parity bit to be in the opposite state from that indicated by LCR(4). This allows the user to force parity to a known state and for the receiver to check the parity bit in a known state.

LCR(6) Break Control: When LCR(6) is set to logic-1, the serial output (SOUT) is forced to the spacing (logic 0) state. The break is disabled by setting LCR(6) to a logic-0. The Break Control bit acts only on SOUT and has no effect on the transmitter logic. Break Control enables the CPU to alert a terminal in a computer communications system. If the following sequence is used, no erroneous or extraneous characters will be transmitted because of the break.

1. Load an all Os pad character in response to THRE.

2. Set break in response to the next THRE.

3. Wait for the transmitter to be idle, (TEMT = 1), and clear break when normal transmission has to be restored.

During the break, the transmitter can be used as a character timer to accurately establish the break duration.

LCR(7) Divisor Latch Access Bit (DLAB): LCR(7) must be set high (logic 1) to access the Divisor Latches DLL and DLM of the Baud Rate Generator during a read or write operation. LCR(7) must be input low to access the Receiver Buffer, the Transmitter Holding Register, or the Interrupt Enable Register.

LINE STATUS REGISTER (LSR)

The LSR is a single register that provides status indications. The LSR is usually the ﬁrst register read by the CPU to determine the cause of an interrupt or to poll the status of the 82C50A.

Three error ﬂags OE, FE, and PE provide the status of any error conditions detected in the receiver circuitry. During reception of the stop bits, the error ﬂags are set high by an error condition. The error ﬂags are not reset by the absence of an error condition in the next received character. The ﬂags reﬂect the last character only if no overrun occurred. The Overrun Error (OE) indicates that a character in the Receiver Buffer Register has been overwritten by a character from the Receiver Shift Register before being read by the CPU. The character is lost. Framing Error (FE) indicates that the last character received contained incorrect (low) stop bits. This is caused by the absence of the required stop bit or by a stop bit too short to be detected. Parity Error (PE) indicates that the last character received contained a parity error based on the programmed and calculated parity of the received character.

The Break Interrupt (BI) status bit indicates that the last character received was a break character. A break character is an invalid data character, with the entire character, including parity and stop bits, logic zero.

The Transmitter Holding Register Empty (THRE) bit indicates that the THR register is empty and ready to receive another character. The Transmission Shift Register Empty (TEMT) bit indicates that the Transmitter Shift Register is empty, and the 82C50A has completed transmission of the last character. If the interrupt is enabled (lER(1)), an active THRE causes an interrupt (INTRPT).

The Data Ready (DR) bit indicates that the RBR has been loaded with a received character (including Break) and that the CPU may access this data.

Reading the LSR clears LSR (1) - LSR (4). (OE, PE, FE and BI).

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