Intersil Corporation 82C237 Datasheet

March 1997

82C237

CMOS High Performance

Programmable DMA Controller

Features

• Fully Compatible with Intersil 82C37A

- 82C237 May be Used in 8MHz and 12.5MHz 82C37A Sockets

• Optimized for 10MHz and 12.5MHz 80C286 Systems

• Special Mode Permits 16-Bit, Zero Wait State DMA Transfers

• High Speed Data Transfers:

- Up to 6.25MBytes/sec with 12.5MHz Clock in

Normal Mode

- Up to 12.5MBytes/sec with 12.5MHz Clock in 16-Bit

Mode

• Compatible with the NMOS 8237A

• Four Independent Maskable Channels with Autoinitialization Capability

• Cascadable to any Number of Channels

• Memory-to-Memory Transfers

• Static CMOS Design Permits Low Power Operation

- ICCSB = 10µA Maximum

- ICCOP = 2mA/MHz Maximum

• Fully TTL/CMOS Compatible

• Internal Registers may be Read from Software

Description

The 82C237 is a modiﬁed version of the 82C37A. The 82C237 is fully software and pin for pin compatible with the 82C37A but provides an additional mode for 16-bit DMA transfers, as well as enhanced speed. Each channel may be individually programmed for 8-bit or 16-bit data transfers.

The 82C237 controller can improve system performance by allowing external devices to transfer data directly to or from system memory. Memory-to-memory transfer capability is also provided, along with a memory block initialization feature. DMA requests may be generated by either hardware or software, and each channel is independently programmable with a variety of features for ﬂexible operation.

The 82C237 is designed to be used with an external address latch, such as the 82C82, to demultiplex the most signiﬁcant 8 bits of address. An additional latch is required to temporarily store the most signiﬁcant 8 bits of data if 16-bit memory-to-memory transfers are desired. The 82C237 can be used with industry standard microprocessors such as 80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and others. Multimode programmability allows the user to select from three basic types of DMA services, and reconﬁguration under program control is possible even with the clock to the controller stopped. Each channel has a full 64K address and word count range, and may be programmed to autoinitialize these registers following DMA termination (end of process).

Ordering Information

TEMPERATURE

PACKAGE

PDIP 0oC to +70oC CP82C237 CP82C237-12 E40.6

PLCC 0oC to +70oC CS82C237 CS82C237-12 N44.65

SBDIP 0oC to +70oC CD82C237 CD82C237-12 F40.6

SMD# 5962-9054304MQA 5962-9054305MQA F40.6

CLCC -55oC to +125oC MR82C237/B MR82C237-12/B J44.A

SMD# 5962-9054304MXA 5962-9054305MXA J44.A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207

RANGE 8MHz 12.5MHz PKG. NO.

-40oC to +85oC IP82C237 IP82C237-12 E40.6

-40oC to +85oC IS82C237 IS82C237-12 N44.65

-40oC to +85oC ID82C237 ID82C237-12 F40.6

-55oC to +125oC MD82C237/B MD82C237-12/B F40.6

4-148

File Number 2965.1

Pinouts

(GND) VSS

IOR

IOW

MEMR

MEMW

DWLE

(NOTE) READY

HLDA

ADSTB

AEN

HRQ

CLK

RESET DACK2 DACK3 DREQ3 DREQ2 DREQ1 DREQ0

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20

82C237 (DIP)

TOP VIEW

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

A7 A6 A5 A4 EOP A3 A2 A1 A0 V

DB0 DB1 DB2 DB3 DB4 DACK0 DACK1 DB5 DB6 DB7

82C237

NC NC

HLDA

ADSTB

AEN

HRQ

CLK

RESET

DACK2

NOTE: See Pin Description.

82C237 (CLCC/PLCC)

MEMW

READY

DWLE

(NOTE)

6 3

7 8

9 10 11 12 13 14 15 16 17

DACK3

DREQ3

DREQ2

TOP VIEW

IOR

MEMR

IOW

GND

DREQ1

DREQ0

DB5

2827262524232221201918

DACK1

EOP

40414243

A1 A0

DB0

DB1

DB2

DB3

DB4

DACK0

DB7

DB6

Block Diagram

DWLE

EOP

RESET

READY

CLK AEN

ADSTB

MEMR

MEMW

IOR

IOW

DREQ0 -

DREQ3

HLDA

DACK0 -

DACK3

HRQ

TIMING

AND

CONTROL

PRIORITY

ENCODER

AND

ROTATING

PRIORITY

LOGIC

DECREMENTOR

TEMP WORD

COUNT REG (16)

READ BUFFER

BASE

ADDRESS

(16)

DATA-WIDTH

(4)

COMMAND

(8)

MASK

(4)

REQUEST

(4)

16-BIT BUS

BASE

WORD

COUNT

(16)

INC DECREMENTOR

TEMP ADDRESS

REG (16)

READ WRITE BUFFER

CURRENT ADDRESS

(16)

WRITE

BUFFER

MODE (4 x 6)

CURRENT

WORD

COUNT

(16)

READ

BUFFER

INTERNAL DATA BUS

STATUS

(8)

A8 - A15

TEMPORARY

BUFFER

OUTPUT BUFFER

COMMAND

CONTROL

(8)

A0 - A3

A4 - A7

D0 - D1

BUFFER

DB0 - DB7

4-149

Pin Description

SYMBOL

NUMBER TYPE DESCRIPTION

82C237

GND 20 Ground

CLK 12 I CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C237

CS 11 I CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data b us f or

RESET 13 I RESET: This is an active high input which clears the Command, Status, Request, and Temporary

READY 6 I READY: This signal can be used to extend the memory read and write pulses from the 82C237 to

HLDA 7 I HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has

DREQ0-

DREQ3

31 VCC: is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for

decoupling.

operations. This input may be driven from DC to 12.5MHz for the 82C237-12 or from DC to 8MHz for the 82C237. The Clock may be stopped in either state for standby operation.

CPU communications.

registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore requests. The Data-Width register is set to perform 8-bit transfers on all channels (82C237 only). Following a Reset, the controller is in an idle cycle.

accommodate slow memories or I/O devices. READY must not make transitions during its speciﬁed set-up and hold times. See Figure 14 for timing. READY is ignored in verify transfer mode.

relinquished control of the system busses. HLDA is a synchronous input and must not transition during its speciﬁed set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising edge of clock, during which time HLDA must not transition.

16-19 I DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request

inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is programmable. RESET initializes these lines to active high. DREQ must be maintained until the corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set. In 16-bit Transfer mode (82C237 only), each DREQ channel may be programmed to perform either 8-bit or 16-bit DMA transfers.

DB0-DB7 21-23

26-30

IOR 1 I/O I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con-

IOW 2 I/O I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con-

I/O DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data

bus. The outputs are enabled in the Program condition during the I/O Read to output the contents of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is programming the 82C237 control registers. During DMA cycles, the most signiﬁcant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB. In memory-to-memory operations, data from the memory enters the 82C237 on the data bus during the read-from-memory transfer, then during the write-to-memory transfer , the data bus outputs write the data into the new memory location.

trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control signal used by the 82C237 to access data from the peripheral during a DMA Write transfer.

trol signal used by the CPU to load information into the 82C237. In the Active cycle, it is an output control signal used by the 82C237 to load data to the peripheral during a DMA Read transfer.

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82C237

Pin Description

SYMBOL

EOP 36 I/O END OF PROCESS: End of Process (EOP) is an active low bidirectional signal. Information

A0-A3 32-35 I/O ADDRESS: The four least signiﬁcant address lines are bidirectional three-state signals. In the Idle

A4-A7 37-40 O ADDRESS: The four most signiﬁcant address lines are three-state outputs and provide 4-bits of

NUMBER TYPE DESCRIPTION

(Continued)

concerning the completion of DMA services is available at the bidirectional EOP pin. The 82C237 allows an external signal to terminate an active DMA service by pulling the EOP pin

low. A pulse is generated by the 82C237 when ter minal count (TC) for any channel is reached, except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will be output when the TC for channel 1 occurs.

The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor to VCC.

When an EOP pulse occurs, whether internally or externally generated, the 82C237 will terminate the service, and if autoinitialize is enabled, the base registers will be written to the current registers of that channel. The mask bit and TC bit in the status word will be set for the currently active channel by EOP unless the channel is programmed for autoinitializ e. In that case, the mask bit remains clear .

cycle, they are inputs and are used by the 82C237 to address the control register to be loaded or read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address. When in 16-bit mode (82C237 only), and the active channel is a 16-bit channel (as deﬁned by the DataWidth register), then A0 will remain low during the entire transfer (i.e. an even word address will always be generated).

address. These lines are enabled only during the DMA service.

HRQ 10 O HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus.

When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made , the 82C237 issues HRQ. The HLDA signal then informs the controller when access to the system busses is permitted. For stand-alone operation where the 82C237 always controls the b usses, HRQ may be tied to HLDA. This will result in one S0 state before the transfer.

DACK0-

DACK3

AEN 9 O ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits

ADSTB 8 O ADDRESS STROBE: This is an active high signal used to control latching of the upper address

MEMR 3 O MEMORY READ: The Memory Read signal is an active low three-state output used to access data

MEMW 4 O MEMORY WRITE: The Memory Write is an active low three-state output used to write data to the

DWLE 5 O DATA-WIDTH, LATCH ENABLE: In normal 8-bit transfer mode (16-bit transfer mode not enabled),

14, 15 24, 25

O DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one

has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them to active low.

onto the system address bus. AEN can also be used to disable other system bus drivers during DMA transfers. AEN is active HIGH.

byte. It will drive directly the strobe input of external transparent octal latches, such as the 82C82. During block operations, ADSTB will only be issued when the upper address byte m ust be updated, thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling edge of the 82C237 clock.

from the selected memory location during a DMA Read or a memory-to-memory transfer.

selected memory location during a DMA Write or a memory-to-memory transfer.

this output is always high impedance three-stated. In 16-bit transfer mode (82C237 only), this output serves a dual purpose. During S1 cycles, the DWLE output indicates the data width (0 = 16-bit, 1 = 8-bit) of the active channel. During memory-to-memory transfers, the DWLE output is used to enable an external latch which temporarily stores the 8 most signiﬁcant bits of data during the read-frommemory transfer. DWLE enables this byte of data onto the data bus during the write-to-memory transfer of a memory-to-memory operation.

4-151

Functional Description

82C237

The 82C237 is an improved version of the Intersil 82C37A DMA controller and is fully software and pin for pin compatible with the 82C37A. All operational and pin descriptions of the 82C37A apply to the 82C237 with additional features noted in the section titled 82C237 Operation.

The 82C237 direct memory access controller is designed to improve the data transfer rate in systems which must transfer data from an I/O device to memory, or move a block of memory to an I/O device. It will also perform memory-tomemory block moves, or ﬁll a block of memory with data from a single location. Operating modes are provided to handle single byte transfers as well as discontinuous data streams, which allows the 82C237 to control data movement with software transparency.

The DMA controller is a state-driven address and control signal generator, which permits data to be transferred directly from an I/O device to memory or vice versa without ever being stored in a temporary register. This can greatly increase the data transfer rate for sequential operations, compared with processor move or repeated string instructions. Memory-to-memory operations require temporary internal storage of the data byte between generation of the source and destination addresses, so memory-to-memory transfers take place at less than half the rate of I/O operations, but still much faster than with central processor techniques. The maximum data transfer rates obtainable with the 82C237 are shown in Figure 1.

The block diagram of the 82C237 is shown on page 2. The timing and control block, priority block, and internal registers are the main components. Figure 2 lists the name and size of the internal registers. The timing and control block derives internal timing from CLK input, and generates external control signals. The Priority Encoder block resolves priority contention between DMA channels requesting service simultaneously.

82C237

TRANSFER

TYPE

Compressed 4.00 8.00 6.25 12.5 MByte/sec Normal I/O 2.67 5.34 4.17 8.34 MByte/sec Memory-to-

Memory

FIGURE 1. DMA TRANSFER RATES

8MHz 12.5MHz

UNIT8-BIT 16-BIT 8-BIT 16-BIT

1.00 2.00 1.56 3.12 MByte/sec

DMA Operation

In a system, the 82C237 address and control outputs and data bus pins are basically connected in parallel with the system busses. An external latch is required for the upper address byte. While inactive, the controller’s outputs are in a high impedance state. When activated by a DMA request and bus control is relinquished by the host, the 82C237 drives the busses and generates the control signals to perform the data transfer. The operation performed by activating one of the four DMA request inputs has previously

been programmed into the controller via the Command, Mode, Address, and Word Count registers.

For example, if a block of data is to be transferred from RAM to an I/O device, the starting address of the data is loaded into the 82C237 Current and Base Address registers for a particular channel, and the length of the block is loaded into the channel’s Word Count register. The corresponding Mode register is programmed for a memory-to-I/O operation (read transfer), and various options are selected by the Command register and the other Mode register bits. The channel’s mask bit is cleared to enable recognition of a DMA request (DREQ). The DREQ can either be a hardware signal or a software command.

Once initiated, the block DMA transfer will proceed as the controller outputs the data address, simultaneous and

IOW pulses, and selects an I/O device via the DMA

MEMR

acknowledge (DACK) outputs. The data byte ﬂows directly from the RAM to the I/O device. After each byte is transferred, the address is automatically incremented (or decremented) and the word count is decremented. The operation is then repeated for the next byte. The controller stops transferring data when the Word Count register underﬂows, or an external

NAME SIZE NUMBER

Base Address Registers 16-Bits 4 Base Word Count Registers 16-Bits 4 Current Address Registers 16-Bits 4 Current Word Count Registers 16-Bits 4 Temporary Address Register 16-Bits 1 Temporary Word Count Register 16-Bits 1 Status Register 8-Bits 1 Command Register 8-Bits 1 Temporary Register 8-Bits 1 Mode Registers 6-Bits 4 Mask Register 4-Bits 1 Request Register 4-Bits 1 Data-Width Register (See Note) 4-Bits 1

NOTE: 82C237 only

FIGURE 2. 82C237 INTERNAL REGISTERS

EOP is applied.

To further understand 82C237 operation, the states generated by each CLK cycle must be considered. The DMA controller operates in two major cycles, active and idle. After being programmed, the controller is normally idle until a DMA request occurs on an unmasked channel, or a software request is given. The 82C237 will then request control of the system busses and enter the active cycle. The activ e cycle is composed of several internal states, depending on what options have been selected and what type of operation has been requested.

4-152

82C237

The 82C237 can assume seven separate states, each composed of one full CLK period. State I (SI) is the idle state. It is entered when the 82C237 has no valid DMA requests pending, at the end of a transfer sequence, or when a RESET or Master Clear has occurred. While in SI, the DMA controller is inactive but may be in the Program Condition (being programmed by the processor).

State 0 (S0) is the ﬁrst state of a DMA service. The 82C237 has requested a hold but the processor has not yet returned an acknowledge. The 82C237 may still be programmed until it has received HLDA from the CPU. An acknowledge from the CPU will signal the DMA transfer may begin. S1, S2, S3, and S4 are the working state of the DMA service. If more time is needed to complete a transfer than is available with normal timing, wait states (SW) can be inserted between S3 and S4 in normal transfers by the use of the READY line on the 82C237. For compressed transfers, wait states can be inserted between S2 and S4. See timing Figures 14 and 15.

Note that the data is transferred directly from the I/O device to memory (or vice versa) with and

IOW) being active at the same time. The data is not read into or driven out of the 82C237 in I/O-to-memory or memory-to-I/O DMA transfers.

Memory-to-memory transfers require a read-from and a writeto memory to complete each transfer. The States, which resemble the normal working states, use two-digit numbers for identiﬁcation. Eight states are required for a single transfer. The ﬁrst four states (S11, S12, S13, S14) are used for the read-from-memory half and the last four states (S21, S22, S23, S24) for the write-to-memory half of the transfer.

IOR and MEMW (or MEMR

Idle Cycle

Special software commands can be executed by the 82C237 in the Program Condition. These commands are decoded as sets of addresses with do not make use of the data bus. Instructions include Set and Clear First/Last Flip-Flop, Master Clear, Clear Mode Register Counter, and Clear Mask Register.

CS, IOR, and IOW. The commands

Active Cycle

When the 82C237 is in the Idle cycle, and a software request or an unmasked channel requests a DMA service, the device will issue HRQ to the microprocessor and enter the Active cycle. It is in this cycle that the DMA service will take place, in one of four modes:

Single Transfer Mode - In single transfer mode, the device is programmed to make one transfer only. The word count will be decremented and the address decremented or incremented following each transfer. When the word count “rolls over” from zero to FFFFH, a terminal count bit in the status register is set, an channel will autoinitialize if this option has been selected. If not programmed to autoinitialize, the mask bit will be set, along with the TC bit and

DREQ must be held active until DACK becomes active. If DREQ is held active throughout the single transfer, HRQ will go inactive and release the bus to the system. It will again go active and, upon receipt of a new HLDA, another single transfer will be performed, unless a higher priority channel takes over. In 8080A, 8085A, 80C88, or 80C86 systems, this will ensure one full machine cycle execution between DMA transfers. Details of timing between the 82C237 and other bus control protocols will depend upon the characteristics of the microprocessor involved.

EOP pulse is generated, and the

EOP pulse.

When no channel is requesting service, the 82C237 will enter the idle cycle and perform “SI” States. In this cycle, the 82C237 will sample the DREQ lines on the falling edge of every CLK cycle to determine if any channel is requesting a DMA service.

Note that for standby operation where the clock has been stopped, DMA requests will be ignored. The device will respond to microprocessor to write or read the internal registers of the 82C237. When enters the Program Condition. The CPU can now establish, change or inspect the internal deﬁnition of the part by reading from or writing to the internal registers.

The 82C237 may be programmed with the clock stopped, provided that HLDA is low and at least one rising CLK edge has occurred after HLDA was driven low, so the controller is in an SI state. Address lines A0-A3 are inputs to the device and select which registers will be read or written. The and

IOW lines are used to select and time the read or write operations. Due to the number and size of the internal registers, an internal ﬂip-ﬂop called the First/Last Flip-Flop is used to generate an additional bit of address. The bit is used to determine the upper or lower byte of the 16-bit Address and Work Count registers. The ﬂip-ﬂop is reset by Master Clear or RESET. Separate software commands can also set or reset this ﬂip-ﬂop.

CS (chip select), in case of an attempt by the

CS is low and HLDA is low, the 82C237

IOR

Block Transfer Mode - In Bloc k Transfer mode, the de vice is activated by DREQ or software request and continues making transfers during the service until a TC, caused by word count going to FFFFH, or an external End of Process (

EOP) is encountered. DREQ need only be held active until DACK becomes active. Again, an Autoinitialization will occur at the end of the service if the channel has been programmed for that option.

Demand Transfer Mode - In Demand Transfer mode the device continues making transfers until a TC or external EOP is encountered, or until DREQ goes inactive. Thus, transfer may continue until the I/O device has exhausted its data capacity. After the I/O device has had a chance to catch up, the DMA service is reestablished by means of a DREQ. During the time between services when the microprocessor is allowed to operate, the intermediate values of address and word count are stored in the 82C237 Current Address and Current Word Count registers. Higher priority channels may intervene in the demand process, once DREQ has gone inactive. Only an end of service. external signal.

Cascade Mode - This mode is used to cascade more than one 82C237 for simple system expansion. The HRQ and HLDA signals from the additional 82C237 are connected to the DREQ and DACK signals respectively of a channel for

EOP can cause an Autoinitialization at the

EOP is generated either by TC or by an

4-153

82C237

the initial 82C237. This allows the DMA requests of the additional device to propagate through the priority network circuitry of the preceding device. The priority chain is preserved and the new device must wait for its turn to acknowledge requests. Since the cascade channel of the initial 82C237 is used only for prioritizing the additional device, it does not output an address or control signals of its own. These could conﬂict with the outputs of the active channel in the added device. The initial 82C237 will respond to DREQ and generate DA CK but all other outputs except HRQ will be disabled. An external

EOP will be ignored by the initial

device, but will have the usual effect on the added device. Figure 3 shows two additional devices cascaded with an

initial device using two of the initial device’s channels. This forms a two-level DMA system. More 82C237s could be added at the second level by using the remaining channels of the ﬁrst level. Additional devices can also be added by cascading into the channels of the second level devices, forming a third level.

2ND LEVEL

80C86/88

MICRO-

PROCESSOR

1ST LEVEL

HRQ HLDA

INITIAL DEVICE

FIGURE 3. CASCADED 82C237s

82C237

DREQ DACK

82C237

HRQ HLDA

82C237

ADDITIONAL

DEVICES

When programming cascaded controllers, start with the ﬁrst level device (closest to the microprocessor). After RESET, the DACK outputs are programmed to be active low and are held in the high state. If they are used to drive HLDA directly, the second level device(s) cannot be programmed until DACK polarity is selected as active high on the initial device. Also, the initial device’s mask bits function normally on cascaded channels, so they may be used to inhibit secondlevel services.

Transfer Types

Each of the three active transfer modes can perfor m three different types of transfers . These are Read, Write and Verify. Write transfers move data from an I/O device to the memor y by activating from memory to an I/O device by activating

Ver ify transfers are pseudo-transfers. The 82C237 operates as in Read or Write transfers generating addresses and responding to control lines all remain inactive. Verify mode is not permitted for memory-to-memory operation. READY is ignored during verify transfers.

MEMW and IOR. Read transfers move data

MEMR and IOW.

EOP, etc., however the memory and I/O

Autoinitialize - By setting bit 4 in the Mode register, a channel may be set up as an Autoinitialize channel. During Autoinitialization, the original values of the Current Address and Current Word Count registers are automatically restored from the Base Address and Base Word Count registers of the channel following

EOP. The base registers are loaded simultaneously with the current registers by the microprocessor and remain unchanged throughout the DMA service. The mask bit is not set when the channel is in Autoinitialize mode. F ollowing Autoinitialization, the channel is ready to perform another DMA service, without CPU intervention, as soon as a valid DREQ is detected, or software request made.

Memory-to-Memory - To perfor m block moves of data from one memory address space to another with minimum of program effort and time, the 82C237 includes a memory-tomemory transfer feature. Setting bit 0 in the Command register selects channels 0 and 1 to operate as memory-tomemory transfer channels.

The transfer is initiated by setting the software or hardware DREQ for channel 0. The 82C237 requests a DMA service in the normal manner. After HLDA is true, the device, using four-state transfers in Block Transfer mode, reads data from the memory. The channel 0 Current Address register is the source for the address used and is decremented or incremented in the normal manner. The data byte read from the memory is stored in the 82C237 internal Temporary register. Another four-state transfer moves the data to memor y using the address in channel one’s Current Address register and incrementing or decrementing it in the normal manner. The channel 1 Current Word Count is decremented.

When the word count of channel 1 decrements to FFFFH, a TC is generated causing an

EOP output, terminating the service, and setting the channel 1 TC bit in the Status register. The channel 1 mask bit will also be set, unless the channel 1 mode register is programmed for autoinitialization. Channel 0 word count decrementing to FFFFH will not set the channel 0 TC bit in the status register or generate an

EOP, or set the channel 0 mask bit in this mode. It will cause an autoinitialization of channel 0, if that option has been selected.

If full Autoinitialization for a memory-to-memory operation is desired, the channel 0 and channel 1 word counts must be set to equal values before the transfer begins. Otherwise, if channel 0 underﬂows before channel 1, it will autoinitialize and set the data source address back to the beginning of the block. If the channel 1 word count underﬂows before channel 0, the memory-to-memory DMA ser vice will terminate, and channel 1 will autoinitialize but channel 0 will not.

In memory-to-memory mode, Channel 0 may be programmed to retain the same address for all transfers. This allows a single byte to be written to a block of memory. This channel 0 address hold feature is selected by setting bit 1 in the Command register.

The 82C237 will respond to external

EOP signals during memory-to-memory transfers, but will only relinquish the system busses after the transfer is complete (i.e. after an S24 state). It should be noted that an external

EOP cannot

cause the channel 0 Address and Word Count registers to

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82C237

autoinitialize, even if the Mode register is programmed for autoinitialization. An external

EOP will autoinitialize the channel 1 registers, if so programmed. Data comparators in block search schemes may use the

EOP input to terminate the service when a match is found. The timing of memory-tomemory transfers in found in Figure 13. Memory-to-memory operations can be detected as an active AEN with no DACK outputs.

Priority - The 82C237 has two types of priority encoding available as software selectable options. The ﬁrst is Fixed Priority which ﬁxes the channels in priority order based upon the descending value of their numbers. The channel with the lowest priority is 3 followed by 2, 1 and the highest priority channel, 0. After the recognition of any one channel for service, the other channels are prevented from interfering with the service until it is completed.

The second scheme is Rotating Priority. The last channel to get service becomes the lowest priority channel with the others rotating accordingly. The next lower channel from the channel serviced has highest priority on the following request. Priority rotates every time control of the system busses is returned to the processor.

Rotating Priority

Highest

Lowest

1ST

SERVICE

0 1 2 3

Service

2nd

SERVICE

2 3 0 1

Service Request

3rd

SERVICE

3 0 1 2

Service

With Rotating Priority in a single chip DMA system, any device requesting service is guaranteed to be recognized after no more than three higher priority services have occurred. This prevents any one channel from monopolizing the system.

Regardless of which priority scheme is chosen, priority is evaluated every time a HLDA is returned to the 82C237.

Compressed Timing - In order to achieve even greater throughput where system characteristics permit, the 82C237 can compress the transfer time to two clock cycles. From Figure 12 it can be seen that state S3 is used to extend the access time of the read pulse. By removing state S3, the read pulse width is made equal to the write pulse width and a transfer consists only of state S2 to change the address and state S4 to perform the read/write. S1 states will still occur when A8-A15 need updating (see Address Generation). Timing for compressed transf ers is f ound in Figure 15.

EOP will output in S2 if compressed timing is selected. Compressed timing is not allowed for memory-tomemory transfers.

Address Generation - In order to reduce pin count, the 82C237 multiplexes the eight higher order address bits on the data lines. State S1 is used to output the higher order address bits to an external latch from which they may be placed on the address bus. The falling edge of Address Strobe (ADSTB) is used to load these bits from the data

lines to the latch. Address Enable (AEN) is used to enable the bits onto the address bus through a three-state enable. The lower order address bits are output by the 82C237 directly. Lines A0-A7 should be connected to the address bus. Figure 12 shows the time relationships between CLK, AEN, ADSTB, DB0-DB7 and A0-A7.

During Block and Demand Transfer mode service, which include multiple transfers, the addresses generated will be sequential. For many transfers the data held in the external address latch will remain the same. This data need only change when a carry or borrow from A7 to A8 takes place in the normal sequence of addresses. To save time and speed transfers, the 82C237 executes S1 states only when updating of A8-A15 in the latch is necessary. This means for long services, S1 states and Address Strobes may occur only once every 256 transfers, a savings of 255 clock cycles for each 256 transfers.

Programming

The 82C237 will accept programming from the host processor anytime that HLDA is inactive, and at least one rising CLK edge has occurred after HLDA went low. It is the responsibility of the host to assure that programming and HLDA are mutually exclusive.

Note that a problem can occur if a DMA request occurs on an unmasked channel while the 82C237 is being programmed. For instance, the CPU may be star ting to reprogram the two byte Address register of channel 1 when channel 1 receives a DMA request. If the 82C237 is enabled (bit 2 in the Command register is 0), and channel 1 is unmasked, a DMA service will occur after only one byte of the Address register has been reprogrammed. This condition can be avoided by disabling the controller (setting bit 2 in the Command register) or masking the channel before programming any of its registers. Once the programming is complete, the controller can be enabled/unmasked.

After power-up it is suggested that all internal locations be loaded with some known value, even if some channels are unused. This will aid in debugging.

Current Address Register - Each channel has a 16-bit

Current Address register. This register holds the value of the address used during DMA transfers. The address is automatically incremented or decremented by one after each transfer and the values of the address are stored in the Current Address register during the transfer . This register is written or read by the microprocessor in successive 8-bit bytes. See Figure 6 for programming information. It may also be reinitialized by an Autoinitialize back to its original value. Autoinitialize takes place only after an memory mode, the channel 0 Current Address register can be prevented from incrementing or decrementing by setting the address hold bit in the Command register.

EOP. In memory-to-

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