intersil 80C88 User Manual

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80C88

Data Sheet February 22, 2008

CMOS 8-/16-Bit Microprocessor

The Intersil 80C88 high performance 8-/16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the highest performance level.

Full TTL compatibility (with the exception of CLOCK) and industry-standard operation allow use of existing NMOS 8088 hardware and Intersil CMOS peripherals.

Complete software compatibility with the 80C86, 8086, and 8088 microprocessors allows use of existing software in new designs.

FN2949.4

Features

• Compatible with NMOS 8088

• Direct Software Compatibility with 80C86, 8086, 8088

• 8-Bit Data Bus Interface; 16-Bit Internal Archi tecture

• Completely Static CMOS Design

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88)

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C88-2)

• Low Power Operation

- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . 500µA Maximum

- ICCOP . . . . . . . . . . . . . . . . . . . . .10mA/MHz Maximum

• 1 Megabyte of Direct Memory Addressing Capability

• 24 Operand Addressing Modes

• Bit, Byte, Word, and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

• Bus-Hold Circuitry Eliminates Pull-up Resistors

• Wide Operating Temperature Ranges

- C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

- I80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

- M80C88 . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

• Pb-Free Available (RoHS Compliant)

Ordering Information

TEMPERATURE

PART NUMBER

(5MHz)

CP80C88 CP80C88 CP80C88-2 CP80C88-2 0 to +70 40 LD PDIP E40.6

IP80C88 IP80C88 IP80C88-2 IP80C88-2 -40 to +85 40 LD PDIP E40.6

MD80C88/B MD80C88/B -55 to +125 40 LD CERDIP F40.6

CP80C88Z (Note)

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

CP80C88Z 0 to +70 40 LD PDIP*

PART NUMBER

(8MHz)

PART

MARKING

RANGE

(°C) PACKAGE PKG. DWG. #

(Pb-Free)

E40.6

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Pinouts

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80C88

(40 LD PDIP, 40 LD CERIDP)

GND

A14

A13

A12

A11

A10

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

NMI

INTR

CLK

GND

TOP VIEW

MIN MAX

A15

A16/S3

A17/S4

A18/S5

A19/S6

SS0

MN/MX

HOLD

HLDA

IO/M

DT/R

DEN

ALE

INTA

TEST

READY

RESET

MODEMODE

(HIGH)

(RQ/GT0)

(RQ

/GT1)

)

(LOCK

(S2

)

(S1

)

(S0

(QS0)

(QS1)

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February 22, 2008

Functional Diagram

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EXECUTION UNIT

DATA POINTER

AND

INDEX REGS

(8 WORDS)

80C88

BUS INTERFACE UNIT

RELOCATION

SEGMENT REGISTERS

INSTRUCTION POINTER

AND

(5 WORDS)

TEST

INTR

NMI

/GT0, 1

HOLD HLDA

16-BIT ALU

FLAGS

CONTROL AND TIMING

CLK RESET READY

MEMORY INTERFACE

MN/MX

C-BUS

BUS

INTERFACE

UNIT

4-BYTE

INSTRUCTION

QUEUE

GND V

LOCK

QS0, QS1

, S1, S0

SSO/HIGH

A19/S6. . . A16/S3

AD7-AD0

A8-A15

, RD, WR

INTA

DT/R, DEN, ALE, IO/M

BUS

INTERFACE

UNIT

EXECUTION

UNIT

AH BH

B-BUS

AL BL CL

INSTRUCTION

STREAM BYTE

QUEUE

A-BUS

ARITHMETIC/

LOGIC UNIT

FLAGS

EXECUTION UNIT

CONTROL SYSTEM

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February 22, 2008

80C88

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Pin Description

The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The “local bus” in these descriptions is the direct multiplexed bus in te rf ace c onn ection to the 80C88 (without regard to additional bus buffers).

SYMBOL

MAXIMUM OR MINIMUM MODE. THE “LOCAL BUS” IN THESE DESCRIPTIONS IS THE DIRECT MULTIPLEXEDBUS INTERFACE CONNECTION TO THE 80C88 (WITHOUT REGARD TO ADDITIONAL BUS BUFFERS).

AD7 thru

AD0

A15,

A14 thru A8

A19/S6, A18/S5, A17/S4,

A16/S3

READY 22 I READY: is the acknowledgment from the address memory or I/O device that it will complete the data

INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each

TEST

NMI 17 I NONMASKABLE INTERRUPT : is an edge triggered input which causes a type 2 interrupt. A subroutine is

RESET 21 I RESET: cases the processor to immediately terminate its present activity . The signal must transition LOW

CLK 19 I CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty

GND 1, 20 GND: are the ground pins (both pins must be connected to system ground). A 0.1µF capacitor between

MN/MX

NUMBER TYPE DESCRIPTION

9 thru 16 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data

(T2,T3,Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last valid level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”

39, 2 thru 8 O ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1-T4). These

lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.

35 36 37 38

32 O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending on

23 I TEST: input is examined by the “wait for test” instruction. If the TEST input is LOW, execution continues,

40 VCC: is the +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 recommended for

33 I MINIMUM/MAXIMUM: indicates the mode in which the processor is to operate. The two modes are

ADDRESS/STATUS: During T1, these are the four most

significant address lines for memory operations. During I/O

operations, these lines are LOW. During memory and I/O

operations, status information is available on these lines during T2, T3, TW and T4. S6 is always LOW. The status of the interrupt enable flag bit (S5) is updated at the beginning of each clock cycle. S4 and S3 are encoded as shown.

This information indicates which segment register is presently being used for data accessing.

These lines are held at high impedance to the last valid logic level during local bus “hold acknowledge” or “grant Sequence”.

the state of the IO/M

is active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH in T2 until the

RD 80C88 local bus has floated. This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.

transfer. The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from READY. This signal is active HIGH. The 80C88 READY input is not synchronized. Correct operation is not guaranteed if the set up and hold times are not met.

instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

otherwise the processor waits in an “idle” state. This input is synchronized internally during each clock cycle on the leading edge of CLK.

vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.

to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as described in the instruction set description, when RESET returns LOW. RESET is internally synchronized.

cycle to provide optimized internal timing.

decoupling.

pins 1 and 20 is recommended for decoupling.

discussed in the following sections.

pin or S2. This signal is used to read devices which reside on the 80C88 local bus.

S4 S3 CHARACTERISTICS

0 0 Alternate Data 01Stack 1 0 Code or None 11Data

FN2949.4

February 22, 2008

80C88

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Pin Description

The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to the minimum mode are described; all other pin functions are as described above.

SYMBOL

MINIMUM MODE SYSTEM (i.e., MN/MX

IO/M 28 O STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from an I/O

WR 29 O Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depending on

INTA

ALE 25 O ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82/82C83

DT/R

DEN

HOLD,

HLDA

SS0

NUMBER TYPE DESCRIPTION

= VCC)

access. IO/M (I/O = HIGH, M = LOW). IO/M

the state of the IO/M to high impedance logic one during local bus “hold acknowledge”.

24 O INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and T w of

each interrupt acknowledge cycle. Note that INTA

address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note that ALE is never floated.

27 O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87 data

26 O DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which uses

31 30

34 O STATUS LINE: is logically equivalent to S0 in

bus transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R equivalent to S1 signal is held to a high impedance logic one during local bus “hold acknowledge”.

the transceiver. DEN or INTA the beginning of T2 until the middle of T4. DEN acknowledge”.

HOLD: indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD must be

active HIGH. The processor receiving the “hold” request will issue HLDA (HIGH) as an acknowledgment, in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines. Hold is not an asynchronous input. External synchronization should be provided if the system cannot otherwise guarantee the set up time.

the maximum mode. The combination of SS0 IO/M decode the current bus cycle status. SS0 to high impedance logic one during local bus “hold acknowledge”.

becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle

is held to a high impedance logic one during local bus “hold acknowledge”.

signal. WR is active for T2, T3, and Tw of any write cycle. It is active LOW, and is held

is never floated.

in the maximum mode, and its timing is the same as for IO/M (T = HIGH, R = LOW). This

is active LOW during each memory and I/O access, and for INTA cycles. For a read

cycle, it is active from the middle of T2 until the middle of T4, while for a write cycle, it is active from

is held to high impedance logic one during local bus “hold

IO/M DT/R SS0 CHARACTERISTICS

and DT/R allows the system to completely

is held

1 0 0 Interrupt Acknowledge 1 0 1 Read I/O Port 1 1 0 Write I/O Port 111Halt 0 0 0 Code Access 0 0 1 Read Memory 0 1 0 Write Memory 011Passive

FN2949.4

February 22, 2008

80C88

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Pin Description (Continued)

The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique to the maximum mode are described; all other pin functions are as described above.

SYMBOL

MAXIMUM MODE SYSTEM (i.e., MN/MX

S0 S1 S2

NUMBER TYPE DESCRIPTION

= GND).

26 27 28

STATUS: is active during clock high of T4, T1 and T2,

and is returned to the passive state (1, 1, 1) during T3 or

during Tw when READY is HIGH. This status is used by the 82C88 bus controller to generate all memory and I/O access control signals. Any change by S2 during T4 is used to indicate the beginning of a bus cycle, and the return to the passive state in T3 or Tw is used to indicate the end of a bus cycle. These signals are held at a high impedance logic one state during “grant sequence”.

, S1 or S0

S2 S1 S0 CHARACTERISTICS

0 0 0 Interrupt Acknowledge 001 Read I/O Port 010 Write I/O Port 011 Halt 100 Code Access 101 Read Memory

1 1 0 Write Memory 1 11Passive

/GT0,

RQ RQ/GT1

LOCK

31 30

29 O LOCK: indicates that other system bus masters are not to gain control of the system bus while LOCK is

I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local

bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ The request/grant sequence is as follows (see RQ

1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to the 80C88 (pulse 1).

2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88 to the requesting master (pulse

2), indicates that the 80C88 has allowed the local bus to float and that it will enter the “grant sequence” state at the next CLK. The CPUs bus interface unit is disconnected logically from the local bus during “grant sequence”.

3. A pulse one CLK wide from the requesting master indicates to the 80C88 (pulse 3) that the “hold” request is about to end and that the 80C88 can reclaim the local bus at the next CLK. The CPU then enters T4 (or T1 if no bus cycles pending).

Each master-master exchange of the local bus is a sequence of three pulses. There must be one idle CLK cycle after bus exchange. Pulses are active LOW. If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conjugations are met:

1. Request occurs on or before T2.

2. Current cycle is not the low bit of a word.

3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A locked instruction is not currently executing.

If the local bus is idle when the request is made the two possible events will follow:

1. Local bus will be released during the next clock.

2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied.

active (LOW). The LOCK completion of the next instruction. This signal is active LOW, and is held at a high impedance logic one state during “grant sequence”. In Max Mode, LOCK cycle and removed during T2 of the second INTA

/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may be left unconnected.

/GT Timing Sequence):

signal is activated by the “LOCK” prefix instruction and remains active until the

is automatically generated during T2 of the first INTA

cycle.

FN2949.4

February 22, 2008

80C88

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Pin Description (Continued)

SYMBOL

MAXIMUM MODE SYSTEM (i.e., MN/MX

QS1, QS0 24, 25 O QUEUE STATUS: provide status to allow external

NUMBER TYPE DESCRIPTION

= GND).

tracking of the internal 80C88 instruction queue. The queue status is valid during the CLK cycle after which the queue operation is performed. Note that the queue status never goes to a high impedance statue (floated).

34 O Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during a “grant

sequence”.

QS1 QS0 CHARACTERISTICS

00No Operation 0 1 First Byte of Opcode from

Queue 1 0 Empty the Queue 1 1 Subsequent Byte from

Queue

Functional Description

Static Operation

All 80C88 circuitry is static in design. Internal registers, counters and latches are static and require not refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microprocessors. The CMOS 80C88 can operate from DC to the specified upper frequency limit. The processor clock may be stopped in either state (high/low) and held there indefinitely. This type of operation is especially useful for system debug or power critical applications.

The 80C88 can be single stepped using only the CPU clock. This state can be maintained as long as is necessary. Single step clock operation allows simple interface circuitry to provide critical information for start-up.

Static design also allows very low frequency operation (as low as DC). In a power critical situation, this can provide extremely low power operation since 80C88 power dissipation is directly related to operation frequency. As the system frequency is reduced, so is the operating power until, at a DC input frequency, the power requirement is the 80C88 standby current.

Internal Architecture

The internal functions of the 80C88 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the CPU block diagram.

this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 4-bytes of the instruction stream can be queued while waiting for decoding and execution.

The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently. Whenever there is space for at least 1-byte in the queue, the BIU will attempt a byte fetch memory cycle. This greatly reduces “dead time”: on the memory bus. The queue acts as a First-In-First-Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU.

The execution unit receives pre-fetched instructions from the BIU queue and provides unrelocated operand addresses to the BIU. Memory operands are passed through the BIU for processing by the EU, which passes results to the BIU for storage.

Memory Organization

The processor provides a 20-bit address to memory which locates the byte being referenced. The memory is organized as a linear array of up to 1 million bytes, addressed as 00000(H) to FFFFF(H). The memory is logically divided into code, data, extra, and stack segments of up to 64-bytes each, with each segment falling on 16-byte boundaries. (See Figure 1).

These units can interact directly but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by

FN2949.4

February 22, 2008

80C88

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SEGMENT

64K-BIT

+ OFFSET

FIGURE 1. MEMORY ORGANIZATION

WORD

LSB

BYTE

MSB

FFFFFH

CODE SEGMENT

XXXXOH

STACK SEGMENT

DATA SEGMENT

EXTRA SEGMENT

00000H

All memory references are made relative to base addresses contained in high speed segment registers. The segment types were chosen based on the addressing needs of programs. The segment register to be selected is automatically chosen according to specific rules as shown in Table1. All information in one se gment type share the same logical attributes (e.g., code or data). By structuring memory into relocatable areas of similar characteristics and by automatically selecting segment registers, programs are shorter, faster, and more structured.

TABLE 1.

MEMORY

REFERENCE

NEED

Instructions CODE (CS) Automatic with all instruction

Stack STACK (SS) All stack pushes and pops.

Local Data DATA (DS) Data references when: relative

External Data (Global)

SEGMENT

USED

prefetch.

Memory references relative to BP base register except data references.

to stack, destination of string operation, or explicitly overridden.

EXTRA (ES) Destination of string

operations: Explicitly selected using a segment override.

SEGMENT

SELECTION RULE

Word (16-bit) operands can be located on even or odd address boundaries. For address and data operands, the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location.

Certain locations in memory are reserved for specific CPU operations. (See Figure 2). Locations from addresses FFFF0H through FFFFFH are reserved for operations including a jump to initial system initialization routine. Following RESET, the CPU will always begin execution at location FFFF0H where the jump must be located. Locations 00000H through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt service routines is accessed through its own pair of 16-bit pointers segment address pointer and offset address pointer. The first pointer, used as the offset address, is loaded into the IP, and the second pointer, which designates the base address, is loaded into the CS. At this point program control is transferred to the interrupt routine. The pointer elements are assumed to have been stored at their respective places in reserved memory prior to the occurrence of interrupts.

Minimum and Maximum Modes

The requirements for supporting minimum and maximum 80C88 systems are sufficiently different that they cannot be done efficiently with 40 uniquely defined pins. Consequently, the 80C88 is equipped with a strap pin (MN/MX defines the system configuration. The definition of a certain subset of the pins changes, dependent on the condition of the strap pin. When the MN/MX

pin is strapped to GND, the

80C88 defines pins 24 through 31 and 34 in maximum mode. When the MN/MX

pins is strapped to VCC, the 80C88 generates bus control signals itself on pins 24 through 31 and 34.

The minimum mode 80C88 can be used with either a muliplexed or demultiplexed bus. This architecture provides the 80C88 processing power in a highly integrated form.

The demultiplexed mode requires one latch (for 64k address ability) or two latches (for a full megabyte of addressing). An 82C86 or 82C87 transceiver can also be used if data bus buffering is required. (See Figure 3). The 80C88 provides DEN

and DT/R to control the transceiver, and ALE to latch the addresses. This configuration of the minimum mode provides the standard demultiplexed bus structure with heavy bus buffering and relaxed bus timing requirements.

The maximum mode employs the 82C88 bus controller (See Figure 4). The 82C88 decode status lines S0, S1 and S2, and provides the system with all bus control signals. Moving the bus control to the 82C88 provides better source and sink current capability to the control lines, and frees the 80C88 pins for extended large system features. Hardware lock, queue status, and two request/grant interfaces are provided by the 80C88 in maximum mode. These features allow coprocessors in local bus and remote bus configurations.

) which

The BIU will automatically execute two fetch or write cycles for 16-bit operands.

FN2949.4

February 22, 2008

80C88

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AVAILABLE INTERRUPT

POINTERS

(224)

RESERVED

INTERRUPT

POINTERS

(27)

DEDICATED INTERRUPT

POINTERS

(5)

FFFFFH

FFFF0H

3FFH

3FCH

084H

080H

07FH

014H

010H

00CH

008H

004H

000H

RESET BOOTSTRAP

PROGRAM JUMP

TYPE 255 POINTER

(AVAILABLE)

TYPE 33 POINTER

(AVAILABLE)

TYPE 32 POINTER

(AVAILABLE)

TYPE 31 POINTER

(AVAILABLE)

TYPE 5 POINTER

(RESERVED)

TYPE 4 POINTER

OVERFLOW

TYPE 3 POINTER

1 BYTE INT INSTRUCTION

TYPE 2 POINTER NON MASKABLE

TYPE 1 POINTER

SINGLE STEP

TYPE 0 POINTER

DIVIDE ERROR

CS BASE ADDRESS

IP OFFSET

16-BITS

FIGURE 2. RESERVED MEMORY LOCATIONS

Bus Operation

The 80C88 address/data bus is broken into three parts: the lower eight address/data bits (AD0-AD7), the middle eight address bits (A8-A15), and the upper four address bits (A16A19). The address/data bits and the highest four address bits are time multiplexed. This technique provides the most efficient use of pins on the processor, permitting the use of standard 40 lead package. The middle eight address bits are not multiplexed, i.e., they remain valid throughout each bus cycle. In addition, the bus can be demultiplexed at the processor with a single address latch if a standard, non multiplexed bus is desired for the system.

Each processor bus cycle consists of at least four CLK cycles. These are referred to as T1, T2, T3 and T4. (See Figure 5). The address is emitted from the processor during T1 and data transfer occurs on the bus during T3 and T4. T2 is used primarily for changing the direction of the bus during read operations. In the event that a “Not Ready” indication is given by the addressed device, “wait” states (TW) are inserted between T3 and T4. Each inserted “wait” state is of the same duration as a CLK cycle. Periods can occur between 80C88 driven bus cycles. These are referred to as “idle” states (TI), or inactive CLK cycles. The processor uses these cycles for internal housekeeping.

During T1 of any bus cycle, the ALE (Address latch enable) signal is emitted (by either the processor or the 82C88 bus controller, depending on the MN/MX

strap). At the trailing edge of this pulse, a valid address and certain status information for the cycle may be latched.

Status bits S0

, S1, and S2 are used by the bus controller, in maximum mode, to identify the type of bus transaction according to Table 2.

Status bits S3 through S6 are multiplexed with high order address bits and are therefore valid during T2 through T4. S3 and S4 indicate which segment register was used to this bus cycle in forming the address according to Table 3.

S5 is a reflection of the PSW interrupt enable bit. S6 is always equal to 0.

FN2949.4

February 22, 2008

80C88

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GND

82C84A/85

RES

RDY

CLOCK

GENERATOR

C1 = C2 = 0.1μF

CLK

READY

RESET

80C88

CPU

GND

AD0-AD7

GND

INTR

MN/MX

IO/M

INTA

DT/R

DEN

ALE

A8-A19

STB

GND

ADDR/DATA

82C82

LATCH

(1, 2 OR 3)

82C86

TRANSCEIVER

82C59A

INTERRUPT

CONTROL

INT

ADDRESS

DATA

HM-65162

CMOS PROM

FIGURE 3. DEMULTIPLEXED BUS CONFIGURATION

IR0-7

HS-6616

CMOS PROM

CS RDWR

82CXX

PERIPHERALS

GND

82C84A/85

RES

RDY

C1 = C2 = 0.1μF

CLK

S1 S2 DEN DT/R ALE

STB

(1, 2 OR 3)

TRANSCEIVER

82C88

82C82

LATCH

82C86

MRDC MWTC

AMWC

AIOWC

IORC

IOWC

INTA

INTERRUPT

ADDRESS

DATA

82C59A

CONTROL

CLK

READY

RESET

80C88

CPU

GND

AD0-AD7

GND

INT

MN/MX

A8-A19

GND

ADDR/DATA

FIGURE 4. FULLY BUFFERED SYSTEM USING BUS CONTROLLER

HM-65162

CMOS PROM

IR0-7

HS-6616

CMOS PROM

CS RDWR

82CXX

PERIPHERALS

FN2949.4

February 22, 2008

80C88

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CLK

ALE

-S0

ADDR

STATUS

ADDR

ADDR DATA

, INTA

READY

(4 + NWAIT) = TCY

T1 T2 T3 T4TWAIT T1 T2 T3 T4TWAIT

A19-A16

A7-A0

S6-S3

A15-A8

BUS RESERVED

FOR DATA IN

D15-D0

VALID

A19-A16

(4 + NWAIT) = TCY

GOES INACTIVE IN THE STATE

JUST PRIOR TO T4

S6-S3

A15-A8

A7-A0 DATA OUT (D7-D0)

READYREADY

WAIT WAIT

DT/R

DEN

MEMORY ACCESS TIME

FIGURE 5. BASIC SYSTEM TIMING

TABLE 2.

0 0 0 Interrupt Acknowledge 0 0 1 Read I/O 010Write I/O 011Halt 1 0 0 Instruction Fetch 1 0 1 Read Data from Memory 1 1 0 Write Data to Memory 111 Passive (No Bus Cycle)

S1 S0 CHARACTERISTICS

TABLE 3.

S4 S3 CHARACTERISTICS

0 0 Alternate Data (Extra Segment) 01Stack 1 0 Code or None 11Data

I/O Addressing

In the 80C88, I/O operations can address up to a maximum of 64k I/O registers. The I/O address appears in the same format as the memory address on bus lines A15-A0. The address lines A19-A16 are zero in I/O operations. The variable I/O instructions, which use register DX as a pointer, have full address capability, while the direct I/O instructions directly address one or two of the 256 I/O byte locations in page 0 of the I/O address space. I/O ports are addressed in the same manner as memory locations.

FN2949.4

February 22, 2008

80C88

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Designers familiar with the 8085 or upgrading an 8085 design should note that the 8085 addresses I/O with an 8-bit address on both halves of the 16-bit address bus. The 80C88 uses a full 16-bit address on its lower 16 address lines.

External Interface

Processor Reset and Initialization

Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin. The 80C88 RESET is required to be HIGH for greater than four clock cycles. The 80C88 will terminate operations on the high-going edge of RESET and will remain dormant as long as RESET is HIGH. The low-going transition of RESET triggers an internal reset sequence for approximately 7 clock cycles. After this interval the 80C88 operates normally, beginning with the instruction in absolute location FFFFOH (see Figure 2). The RESET input is internally synchronized to the processor clock. At initialization, the HIGH to LOW transition of RESET must occur no sooner than 50μs after power up, to allow complete initialization of the 80C88.

NMI will not be recognized if asserted prior to the second CLK cycle following the end of RESET.

appropriate element to the new interrupt service program location.

BOND

PAD

OUTPUT

DRIVER

INPUT

BUFFER

FIGURE 6A. BUS HOLD CIRCUITRY PINS 2-16 AND 35-39

OUTPUT

DRIVER

INPUT

BUFFER

FIGURE 6B. BUS HOLD CIRCUITRY PINS 26-32 AND 34

INPUT

PROTECTION

CIRCUITRY

INPUT

PROTECTION

CIRCUITRY

FIGURE 6.

BOND

PAD

EXTERNAL PIN

Bus Hold Circuitry

To avoid high current conditions caused by floating inputs to CMOS devices and to eliminate the need for pull-up/down resistors, “bus-hold” circuitry has been used on 80C88 pins 2-16, 26-32 and 34-39 (see Figure 6A and 6B). These circuits maintain a valid logic state if no driving source is present (i.e., an unconnected pin or a driving source which goes to a high impedance state).

T o override the “bus hold” circuits, an external driver must be capable of supplying 400μA minimum sink or source current at valid input voltage levels. Since this “bus hold” circuitry is active and not a “resistive” type element, the associated power supply current is negligible. Power dissipation is significantly reduced when compared to the use of passive pull-up resistors.

Interrupt Operations

Interrupt operations fall into two classes: software or hardware initiated. The software initiated interrupts and software aspects of hardware interrupts are specified in the instruction set description. Hardware interrupts can be classified as nonmusical or maskable.

Interrupts result in a transfer of control to a new program location. A 256 element table containing address pointers to the interrupt service program locations resides in absolute locations 0 through 3FFH (see Figure 2), which are reserved for this purpose. Each element in the table is 4-bytes in size and corresponds to an interrupt “type”. An interrupting device supplies an 8-bit type number, during the interrupt acknowledge sequence, which is used to vector through the

Non-Maskable Interrupt (NMI)

The processor provides a single non-maskable interrupt (NMI) pin which has higher priority than the maskable interrupt request (INTR) pin. A typical use would be to activate a power failure routine. The NMI is edge-triggered on a LOW to High transition. The activation of this pin causes a type 2 interrupt.

NMI is required to have a duration in the HIGH state of greater than two clock cycles, but is not required to be synchronized to the clock. An high going transition of NMI is latched on-chip and will be serviced at the end of the current instruction or between whole moves (2-bytes in the case of word moves) of a block type instruction. Worst case response to NMI would be for multiply, divide, and variable shift instructions. There is no specification on the occurrence of the low-going edge; it may occur before, during, or after the servicing of NMI. Another high-going edge triggers another response if it occurs after the start of the NMI procedure.

The signal must be free of logical spikes in general and be free of bounces on the low-going edge to avoid triggering extraneous responses.

Maskable Interrupt (INTR)

The 80C88 provides a singe interrupt request input (INTR) which can be masked internally by software with the resetting of the interrupt enable (IF) flag bit. The interrupt request signal is level triggered. It is internally synchronized during each clock cycle on the high-going edge of CLK.

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February 22, 2008

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