Intersil Corporation HD3-6402R-9, HD3-6402B-9, HD1-6402R-9, 5962-9052502MQA, 5962-9052501MQA Datasheet

5-1

March 1997

HD-6402

CMOS Universal Asynchronous

Receiver Transmitter (UART)

Features

• 8.0MHz Operating Frequency (HD-6402B)

• 2.0MHz Operating Frequency (HD-6402R)

• Low Power CMOS Design

• Programmable Word Length, Stop Bits and Parity

• Automatic Data Formatting and Status Generation

• Compatible with Industry Standard UARTs

• Single +5V Power Supply

• CMOS/TTL Compatible Inputs

Description

The HD-6402 is a CMOS UART for interfacing computers or
microprocessors to an asynchronous serial data channel.
The receiver converts serial start, data, parity and stop bits.
The transmitter converts parallel data into serial form and
automatically adds start, parity and stop bits. The data word
length can be 5, 6, 7 or 8 bits. Parity may be odd or even.
Parity checking and generation can be inhibited. The stop
bits may be one or two or one and one-half when transmit­ting 5-bit code.

The HD-6402 can be used in a wide range of applications
including modems, printers, peripherals and remote data
acquisition systems. Utilizing the Intersil advanced scaled
SAJI IV CMOS process permits operation clock frequencies
up to 8.0MHz (500K Baud). Power requirements , b y compar­ison, are reduced from 300mW to 10mW. Status logic
increases flexibility and simplifies the user interface.

Pinout

HD-6402 (PDIP, CERDIP)

TOP VIEW

Ordering Information

PACKAGE TEMPERATURE RANGE 2MHz = 125K BAUD 8MHz = 500K BAUD PKG. NO.

Plastic DIP -40oC to +85oC HD3-6402R-9 HD3-6402B-9 E40.6
CERDIP -40oC to +85oC HD1-6402R-9 HD1-6402B-9 F40.6

SMD# -55oC to +125oC 5962-9052501MQA 5962-9052502MQA F40.6

13

1
2
3
4
5
6
7
8

9
10
11
12

14
15
16
17
18
19
20

V

CC

NC
GND
RRD

RBR8
RBR7
RBR6
RBR5
RBR4
RBR3
RBR2
RBR1

PE
FE

OE

SFD
RRC
DRR

DR

RRI

28

40
39
38
37
36
35
34
33
32
31
30
29

27
26
25
24
23
22
21

TRC
EPE
CLS1
CLS2
SBS
PI
CRL
TBR8
TBR7
TBR6
TBR5
TBR4
TBR3
TBR2
TBR1
TRO
TRE
TBRL
TBRE
MR

File Number 2956.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

5-2

Functional Diagram

Control Definition

CONTROL WORD CHARACTER FORMAT

CLS 2 CLS 1 PI EPE SBS START BIT DATA BITS PARITY BIT STOP BITS

0 0 0 0 0 1 5 ODD 1
0 0 0 0 1 1 5 ODD 1.5
0 0 0 1 0 1 5 EVEN 1
0 0 0 1 1 1 5 EVEN 1.5
0 0 1 X 0 1 5 NONE 1
0 0 1 X 1 1 5 NONE 1.5
0 1 0 0 0 1 6 ODD 1
0 1 0 0 1 1 6 ODD 2
0 1 0 1 0 1 6 EVEN 1
0 1 0 1 1 1 6 EVEN 2
0 1 1 X 0 1 6 NONE 1
0 1 1 x 1 1 6 NONE 2
1 0 0 0 0 1 7 ODD 1
1 0 0 0 1 1 7 ODD 2
1 0 0 1 0 1 7 EVEN 1
1 0 0 1 1 1 7 EVEN 2
1 0 1 X 0 1 7 NONE 1
1 0 1 x 1 1 7 NONE 2
1 1 0 0 0 1 8 ODD 1
1 1 0 0 1 1 8 ODD 2
1 1 0 1 0 1 8 EVEN 1
1 1 0 1 1 1 8 EVEN 2
1 1 1 X 0 1 8 NONE 1
1 1 1 x 1 1 8 NONE 2

(24) TRE

(22) TBRE †

(23)

TBRL

(40) TRC

(38) CLS1
(37) CLS2

(34) CRL

(21) MR

(17) RRC
(18)

DRR

(19) DR †

(16) SFD

† OE † FE † PE

(15)

(14)

(13)

(5) (6) (7)

† RBR8

3-STATE

BUFFERS

(8) (9) (10)(11) (12)

† RBR1

RECEIVER BUFFER REGISTER

RECEIVER REGISTER

MULTIPLEXER

MULTIPLEXER

TRANSMITTER REGISTER

TRANSMITTER BUFFER REGISTER

START

STOP

PARITY

LOGIC

PARITY

LOGIC

START
LOGIC

STOP

LOGIC

CONTROL

REGISTER

RECEIVER

TIMING AND

CONTROL

TRANSMITTER

TIMING AND

CONTROL

† THESE OUTPUTS ARE

THREE-STATE

(4) RRD

(20) RRI

(35) PI

(39) EPE

(16) SFD

(36) SBS

(25) TRO

(26)

TBR1(27)

(30)

(29)

(28)

(31)

(32)

(33)TBR8

HD-6402

5-3

Pin Description

PIN TYPE SYMBOL DESCRIPTION

1V

CC

† Positive Voltage Supply
2 NC No Connection
3 GND Ground
4 I RRD A high level on RECEIVER REGISTER DISABLE

forces the receiver holding out-puts RBR1-RBR8
to high impedance state.

5 O RBR8 The contents of the RECEIVER BUFFER REGIS-

TER appear on these three-state outputs. Word for­mats less than 8 characters are right justified to

RBR1.
6 O RBR7 See Pin 5-RBR8
7 O RBR6 See Pin 5-RBR8
8 O RBR5 See Pin 5-RBR8
9 O RBR4 See Pin 5-RBR8

10 O RBR3 See Pin 5-RBR8
11 O RBR2 See Pin 5-RBR8
12 O RBR1 See Pin 5-RBR8
13 O PE A high level on PARITY ERROR indicates receiv ed

parity does not match parity programmed by control

bits. When parity is inhibited this output is low.

14 O FE A high level on FRAMING ERROR indicates the

first stop bit was invalid.

15 O OE A high level on OVERRUN ERROR indicates the

data received flag was not cleared before the last

character was transferred to the receiver buffer

register.

16 I SFD A high level on STATUS FLAGS DISABLE forces

the outputs PE, FE, OE, DR, TBRE to a high im-

pedance state.

17 I RRC The Receiver register clock is 16X the receiver

data rate.

18 I

DRR A low level on DATA RECEIVED RESET clears

the data received output DR to a low level.

19 O DR A high level on DATA RECEIVED indicates a

character has been received and transferred to

the receiver buffer register.

20 I RRI Serial data on RECEIVER REGISTER INPUT is

clocked into the receiver register.

21 I MR A high level on MASTER RESET clears PE, FE,

OE and DR to a low level and sets the transmitter

register empty (TRE) to a high level 18 clock cycles

after MR falling edge. MR does not clear the receiv-

er buffer register. This input must be pulsed at least

once after power up. The HD-6402 must be master

reset after power up. The reset pulse should meet

V

IH

and tMR. Wait 18 clock cycles after the falling

edge of MR before beginning operation.

22 O TBRE A high lev el on TRANSMITTER BUFFER REGIS-

TER EMPTY indicates the transmitter buffer register
has transferred its data to the transmitter register
and is ready for new data.

23 I

TBRL A low level on TRANSMITTER BUFFER REGIS-

TER LOAD transfers data from inputs TBR1­TBR8 into the transmitter buffer register. A low to
high transition on

TBRL initiates data transfer to
the transmitter register. If busy, transfer is auto­matically delayed so that the two characters are
transmitted end to end.

24 O TRE A high level on TRANSMITTER REGISTER EMP-

TY indicates completed transmission of a charac­ter including stop bits.

25 O TRO Character data, start data and stop bits appear se-

rially at the TRANSMITTER REGISTER OUTPUT.

26 I TRB1 Character data is loaded into the TRANSMITTER

BUFFER REGISTER via inputs TBR1-TBR8. For
character formats less than 8 bits the TBR8, 7 and
6 inputs are ignored corresponding to their pro­grammed word length.

27 I TBR2 See Pin 26-TBR1.
28 I TBR3 See Pin 26-TBR1.
29 I TBR4 See Pin 26-TBR1.
30 I TBR5 See Pin 26-TBR1.
31 I TBR6 See Pin 26-TBR1.
32 I TBR7 See Pin 26-TBR1.
33 I TBR8 See Pin 26-TBR1.
34 I CRL A high level on CONTROL REGISTER LOAD

loads the control register with the control word. The
control word is latched on the falling edge of CRL.
CRL may be tied high.

35 I PI A high level on PARITY INHIBIT inhibits parity gen-

eration, parity checking and forces PE output low.

36 I SBS A high level on STOP BIT SELECT selects 1.5

stop bits for 5 character format and 2 stop bits for
other lengths.

37 I CLS2 These inputs program the CHARACTER

LENGTH SELECTED (CLS1 low CLS2 low 5 bits)
(CLS1 high CLS2 low 6 bits) (CLS1 low CLS2
high 7 bits) (CLS1 high CLS2 high 8 bits.)

38 I CLS1 See Pin 37-CLS2.
39 I EPE When PI is low, a high level on EVEN PARITY

ENABLE generates and checks even parity. A low
level selects odd parity.

40 I TRC The TRANSMITTER REGISTER CLOCK is 16X

the transmit data rate.

† A 0.1µF decoupling capacitor from the VCC pin to the GND is rec-

ommended.

PIN TYPE SYMBOL DESCRIPTION

28

40

39

38

37

36

35

34

33

32

31

30

29

27

26

25

24

23

22

21

13

1

2

3

4

5

6

7

8

9

10

11

12

14

15

16

17

18

19

20

HD-6402

HD-6402