®
www.BDTIC.com/Intersil
5962-0721301QXC, 5962-0721302QXC,
5962-0721303QYC
Data Sheet October 17, 2007
500MHz Rail-to-Rail Amplifiers
The 5962-0721301QXC, 5962-0721302QXC and
5962-0721303QYC are fully DSCC SMD compliant parts and
the SMD data sheets are available on the DSCC website
(http://www.dscc.dla.mil/ programs/specfind/default.asp). The
5962-0721301QXC is electrically equivalent to the EL8202,
the 5962-0721302QXC is electrically equivalent to the
EL8203, and the 5962-0721303QYC is electrically equivalent
to the EL8403. Reference equivalent “EL” data sheet for
additional information. These parts are dual and quad ra il-to rail amplifiers with a -3dB bandwidth of 500 MHz and slew rate
of 600V/µs.
Running off a low supply current of 13.5mA per channel, the
5962-0721301QXC, 5962-0721302QXC, and 59620721303QYC also feature inputs that go to 0.15V below the
V
- rail. The 5962-0721301QXC and 5962-0721302QXC
S
are dual channel amplifiers. The 5962-0721303QYC is a
quad channel amplifier.
The 5962-0721301QXC includes a fast-acting
disable/power-down circuit with a 25ns disable and a 200ns
enable, the 5962-0721301QXC is ideal for multiplexing
applications.
FN6478.1
Features
• 500MHz -3dB bandwidth
• 600V/µs slew rate
• Supplies from 3V to 5.5V
• Rail-to-rail output
• Input to 0.15V below VS-
• Fast 25ns disable (5962-0721301QXC only)
Applications
• Video amplifiers
• Portable/hand-held products
• Communications devices
Ordering Information
PART
NUMBER
5962-0721301QXC 07213 01QXC 10 Ld Flat Pack K10.A
5962-0721302QXC 07213 02QXC 10 Ld Flat Pack K10.A
5962-0721303QYC 07213 03QYC 14 Ld Flat Pack K14.A
NOTE: These Intersil Pb-free Hermetic packaged products employ
100% Au plate - e4 termination finish, which is RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
PART
MARKING PACKAGE
PKG.
DWG. #
Pinouts
5962-0721301QXC
(10 LD FLATPACK)
TOP VIEW
1
2
3
4
5
INA+
CEA
VS-
CEB
INB+
INA-
OUTA
VS+
OUTB
INB-
5962-0721302QXC
(10 LD FLATPACK)
TOP VIEW
10
9
8
7
6
1
2
3
4
5
INA+
NC
VS-
NC
INB
INA-
OUTA
VS+
OUTB
INB-
10
9
8
7
6
5962-0721303QYC
(14 LD FLATPACK)
TOP VIEW
1
2
3
4
5
6
7
OUTA
INA-
INA+
VS+
INB
INB
OUTB
OUTD
IND-
IND+
VS-
INC+
INC-
OUTC
14
13
12
11
10
9
8
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
Copyright © Intersil Americas Inc. 2007. All Rights Reserved.
5962-0721301QXC, 5962-0721302QXC, 5962-0721303QYC
www.BDTIC.com/Intersil
Absolute Maximum Ratings (T
Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . 20mA/Op Amp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guar anteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T
Electrical Specifications V
= +25°C) Thermal Information
A
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 74.3mW/Op Amp
+ +0.3V to VS- -0.3V
S
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . .-55°C to +125°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
= TC = T
J
= 5V, VS- = GND, TA = +25°C, V
S+
A
= 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified.
CM
PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
R
IN
C
IN
Input Resistance Common Mode 3.5 MΩ
Input Capacitance 0.5 pF
OUTPUT CHARACTERISTICS
R
I
OUT
OUT
Output Resistance AV = +1 30 mΩ
Linear Output Current 65 mA
ENABLE (5962-0721301QXC ONLY)
t
EN
t
DS
V
IH-ENB
V
IL-ENB
Enable Time 200 ns
Disable Time 25 ns
ENABLE Pin Voltage for Power-up 0.8 V
ENABLE Pin Voltage for Shut-down 2 V
AC PERFORMANCE
BW -3dB Bandwidth A
BW ±0.1dB Bandwidth A
Peak Peaking A
= +1, RF = 0Ω, CL = 2.5pF 500 MHz
V
A
= -1, RF = 1kΩ, CL = 2.5pF 140 MHz
V
= +2, RF = 1kΩ, CL = 2.5pF 165 MHz
A
V
= +10, RF = 1kΩ, CL = 2.5pF 18 MHz
A
V
= +1, RF = 0Ω, CL = 2.5pF 35 MHz
V
= +1, RL = 1kΩ, CL = 2.5pF 2 dB
V
GBWP Gain Bandwidth Product 200 MHz
PM Phase Margin R
SR Slew Rate A
t
R
t
F
Rise Time 2.5V
Fall Time 2.5V
= 1kΩ, CL = 2.5pF 55 °
L
= 2, RL = 100Ω, V
V
, 20% to 80% 4 ns
STEP
, 20% to 80% 2 ns
STEP
= 0.5V to 4.5V 600 V/µs
OUT
OS Overshoot 200mV step 10 %
t
PD
t
S
dG Differential Gain A
dP Differential Phase A
e
N
+ Positive Input Noise Current f = 10kHz 1.7 pA/√Hz
i
N
i
- Negative Input Noise Current f = 10kHz 1.3 pA/√Hz
N
e
S
Propagation Delay 200mV step 1 ns
0.1% Settling Time 200mV step 15 ns
= +2, RF = 1kΩ, RL = 150Ω 0.01 %
V
= +2, RF = 1kΩ, RL = 150Ω 0.01 °
V
Input Noise Voltage f = 10kHz 12 nV/√Hz
Channel Separation f = 100kHz 95 dB
2
FN6478.1
October 17, 2007
Pin Descriptions
www.BDTIC.com/Intersil
5962-0721301QXC, 5962-0721302QXC, 5962-0721303QYC
5962-0721301QXC
(10 LD FLATPACK)
5962-0721302QXC
(10 LD FLATPACK)
1, 5 1, 5 3, 5, 10, 12 IN+ Non-inverting input for each channel
2, 4 CE
3 3 11 VS- Negative power supply
6, 10 6, 10 2, 6, 9, 13 IN- Inverting input for each channel
7, 9 7, 9 1, 7, 8, 14 OUT Amplifier output for each channel
8 8 4 VS+ Positive power supply
2, 4 NC Not Connected
Simplified Schematic Diagram
I
1
R
3
R
1
Q
IN+
1
5962-0721303QYC
(14 LD FLATPACK) NAME FUNCTION
Enable and disable input for each channel
V
S+
I
2
R
2
Q
IN-
2
V
BIAS2
R
6
Q
5
Q
3
R
7
V
Q
6
BIAS1
DIFFERENTIAL TO
SINGLE ENDED
DRIVE
GENERATOR
Q
4
Q
7
Q
8
R
8
OUT
R
4
R
5
V
S-
R
9
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidi aries.
For information regarding Intersil Corporation and its products, see www.intersil.com
3
FN6478.1
October 17, 2007
5962-0721301QXC, 5962-0721302QXC, 5962-0721303QYC
www.BDTIC.com/Intersil
Ceramic Metal Seal Flatpack Packages (Flatpack)
e
-A- -B-
b
0.004 H A - BMD
Q
A
-C-
SEATING AND
BASE PLANE
L
c1
M
PIN NO. 1
ID AREA
E1
S S
E
E3 E3
LEAD FINISH
BASE
METAL
b1
M
(b)
SECTION A-A
0.036 H A - BMD
-D-
LE2
(c)
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
A
A
S1
S S
C
D
-H-
K10.A MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B)
10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES MILLIMETERS
SYMBOL
A 0.045 0.115 1.14 2.92 -
b 0.015 0.022 0.38 0.56 -
b1 0.015 0.019 0.38 0.48 -
c 0.004 0.009 0.10 0.23 -
c1 0.004 0.006 0.10 0.15 -
D - 0.290 - 7.37 3
E 0.240 0.260 6.10 6.60 -
E1 -0.280-7.113
E2 0.125 - 3.18 - -
E3 0.030 - 0.76 - 7
e 0.050 BSC 1.27 BSC -
k 0.008 0.015 0.20 0.38 2
L 0.250 0.370 6.35 9.40 -
Q 0.026 0.045 0.66 1.14 8
S1 0.005 - 0.13 - 6
M - 0.0015 - 0.04 -
N10 10-
NOTESMIN MAX MIN MAX
Rev. 0 3/07
4
FN6478.1
October 17, 2007
5962-0721301QXC, 5962-0721302QXC, 5962-0721303QYC
www.BDTIC.com/Intersil
14 ld FLA TPACK Package Outline Drawing
A
e
PIN NO. 1
ID AREA
-A- -B-
b
E1
0.004 H A - BMD
Q
A
-C-
SEATING AND
BASE PLANE
S S
L
E3 E3
c1
M
LEAD FINISH
BASE
METAL
SECTION A-A
0.036 H A - BMD
E
(c)
b1
M
(b)
-D-
LE2
A
S1
S S
C
-H-
NOTES:
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
INCHES MILLIMETERS
SYMBOL
D
A 0.045 0.115 1.14 2.92 -
b 0.015 0.022 0.38 0.56 -
b1 0.015 0.019 0.38 0.48 -
c 0.004 0.009 0.10 0.23 -
c1 0.004 0.006 0.10 0.15 -
D - 0.390 - 9.91 3
E 0.235 0.260 5.97 6.60 -
E1 -0.290-7.113
E2 0.125 - 3.18 - -
E3 0.030 - 0.76 - 7
e 0.050 BSC 1.27 BSC -
k 0.008 0.015 0.20 0.38 2
L 0.270 0.370 6.86 9.40 -
Q 0.026 0.045 0.66 1.14 8
S1 0.005 - 0.13 - 6
M - 0.0015 - 0.04 -
N14 14-
NOTESMIN MAX MIN MAX
Rev. 0 5/18/94
5
FN6478.1
October 17, 2007
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