Datasheet 5962-0623501QPC, 5962-0623502QPC Datasheet (intersil)

®

www.BDTIC.com/Intersil

5962-0623501QPC, 5962-0623502QPC

Data Sheet May 11, 2007

500MHz Rail-to-Rail Amplifiers

The 5962-0623501QPC, 5962-0623502QPC are fully DSCC
SMD compliant parts and the SMD data sheets are available
on the DSCC website
(http://www.dscc.dla.mil/programs/specfind/default.asp).
The 5962-0623501QPC is electrically equivalent to the
EL8102 and the 5962-0623502QPC is electrically equivalent
to the EL8103, reference these data sheets for additional
information. These parts are single rail-to-rail amplifiers with
a -3dB bandwidth of 500MHz and slew rate of 600V/µs.
Running off a very low 11mA supply current, the
5962-0623501QPC, 5962-0623502QPC also feature inputs
that go to 0.15V below the V

The 5962-0623501QPC includes a fast-acting
disable/power-down circuit. With a 25ns disable and a 200ns
enable, the 5962-0623501QPC is ideal for multiplexing
applications.

The 5962-0623501QPC, 5962-0623502QPC are designed
for a number of general purpose video, communication,
instrumentation, and industrial applications. Both parts are
available in 8 Ld SBDIP. All are specified for operation over
the -55°C to +125°C temperature range.

- rail.

S

Features

• 500MHz -3dB bandwidth

• 600V/µs slew rate

• Low supply current = 11mA

• Supplies from 3V to 5.0V

• Rail-to-rail output

• Input to 0.15V below V

-

S

• Fast 25ns disable (5962-0623501QPC only)

Applications

• Video amplifiers

• Portable/hand-held products

• Communications devices

Pinouts

5962-0623501QPC

(8 LD SBDIP)

TOP VIEW

NC

1

8

ENABLE

FN6472.1

Ordering Information

PART

NUMBER

5962-0623501QPC 5962-0623

5962-0623502QPC 5962-0623

PART

MARKING

501QPC

502QPC

TEMP.

RANGE (°C) PACKAGE

-55 to +125 8 Ld SBDIP D8.3

-55 to +125 8 Ld SBDIP D8.3

DWG. #

PKG.

IN-

2

IN+

3

VS-

4

5962-0623502QPC

(8 LD SBDIP)

TOP VIEW

NC

1

IN-

2

IN+

3

VS-

4

7

-

+

­+

VS+

OUT

6

NC

5

NC

8

VS+

7

OUT

6

NC

5

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Copyright Intersil Americas Inc. 2007. All Rights Reserved

5962-0623501QPC, 5962-0623502QPC

www.BDTIC.com/Intersil

Absolute Maximum Ratings (T

Supply Voltage from VS+ to VS-. . . . . . . . . . . . . . . . . . . . . . . . . 5.5V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V

Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T

Electrical Specifications V

= +25°C) Thermal Information

A

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60.5mW

+ +0.3V to VS- -0.3V

S

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Ambient Operating Temperature . . . . . . . . . . . . . . .-55°C to +125°C

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+150°C

= TC = T

J

= 5V, VS- = GND, TA = +25°C, V

S+

A

= 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified

CM

PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS

R

IN

C

IN

Input Resistance Common Mode 3.5 MΩ
Input Capacitance 0.5 pF

OUTPUT CHARACTERISTICS

R

OUT

Output Resistance AV = +1 30 mΩ

ENABLE (5962-0623501QPC ONLY)

t

EN

t

DS

Enable Time 200 ns
Disable Time 25 ns

AC PERFORMANCE

BW -3dB Bandwidth A

BW ±0.1dB Bandwidth A
Peak Peaking A

= +1, RF = 0Ω, CL = 5pF 500 MHz

V

A

= -1, RF = 1kΩ, CL = 5pF 140 MHz

V

= +2, RF = 1kΩ, CL = 5pF 165 MHz

A

V

= +10, RF = 1kΩ, CL = 5pF 18 MHz

A

V

= +1, RF = 0Ω, CL = 5pF 35 MHz

V

= +1, RL = 1kΩ, CL = 5pF 1 dB

V

GBWP Gain Bandwidth Product 200 MHz
PM Phase Margin R
SR Slew Rate A
t

R

t

F

Rise Time 2.5V
Fall Time 2.5V

= 1kΩ, CL = 5pF 55 °

L

= 2, RL = 100Ω, V

V

, 20% to 80% 4 ns

STEP

, 20% to 80% 2 ns

STEP

= 0.5V to 4.5V 600 V/µs

OUT

OS Overshoot 200mV step 10 %
t

PD

t

S

dG Differential Gain A
dP Differential Phase A
e

N

+ Positive Input Noise Current f = 10kHz 1.7 pA/√Hz

i

N

i

- Negative Input Noise Current f = 10kHz 1.3 pA/√Hz

N

Propagation Delay 200mV step 1 ns

0.1% Settling Time 200mV step 15 ns
= +2, RF = 1kΩ, RL = 150Ω 0.01 %

V

= +2, RF = 1kΩ, RL = 150Ω 0.01 °

V

Input Noise Voltage f = 10kHz 12 nV/√Hz

2

FN6472.1

May 11, 2007

5962-0623501QPC, 5962-0623502QPC

www.BDTIC.com/Intersil

Pin Descriptions

PART

1, 5 1, 5, 8 NC Not connected

2 2 IN- Inverting input
3 3 IN+ Non-inverting input
4 4 VS- Negative power supply
6 6 OUT Amplifier output
7 7 VS+ Positive power supply
8 ENABLE

Simplified Schematic Diagram

PIN NAME FUNCTION5962-0623501QPC 5962-0623502QPC

Enable and disable input

V

S+

I1

IN+

R3

R1 R2

Q1 Q2

I2

V

IN-

BIAS2

R6

Q5

Q3

R4 R5

Q6

Q4

V

R7

R8

V

BIAS1

DIFFERENTIAL TO

SINGLE ENDED

DRIVE

GENERATOR

S-

Q7

OUT

Q8

R9

3

FN6472.1

May 11, 2007

5962-0623501QPC, 5962-0623502QPC

www.BDTIC.com/Intersil

Ceramic Dual-In-Line Metal Seal Packages (SBDIP)

LEAD FINISH

c1

-A-

-B-

S

bbb C A - B

BASE

PLANE

SEATING

PLANE

S1

b2

ccc

b

CA - BM

D

A

A

e

DS S

NOTES:

1. Index area: A notch or a pin one identification mark shall be locat­ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.

5. Dimension Q shall be measured from the seating plane to the
base plane.

6. Measure dimension S1 at all four corners.

7. Measure dimension S2 from the top of the ceramic body to the
nearest metallization or lead.

8. N is the maximum number of terminal positions.

9. Braze fillets shall be concave.

10. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

11. Controlling dimension: INCH.

-D-

BASE

E

S

S

D

Q

S2

-C-

METAL

b1

M

(b)

SECTION A-A

A

L

(c)

M

eA

aaa

eA/2

CA - BM DS S

c

D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)

8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.200 - 5.08 -

b 0.014 0.026 0.36 0.66 2

b1 0.014 0.023 0.36 0.58 3

b2 0.045 0.065 1.14 1.65 -

b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2

c1 0.008 0.015 0.20 0.38 3

D - 0.405 - 10.29 -

E 0.220 0.310 5.59 7.87 -

e 0.100 BSC 2.54 BSC -

eA 0.300 BSC 7.62 BSC -

eA/2 0.150 BSC 3.81 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.060 0.38 1.52 5

S1 0.005 - 0.13 - 6

S2 0.005 - 0.13 - 7

o

α

90

105

o

90

o

105

aaa - 0.015 - 0.38 -

bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2

N8 88

NOTESMIN MAX MIN MAX

o

Rev. 0 4/94

-

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or its subsidiaries.

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4

FN6472.1

May 11, 2007