International Rrectifier RECTIFIER User Manual

IR2114SSPbF/IR21141SSPbF IR2214SSPbF/IR22141SSPbF

HALF-BRIDGE GATE DRIVER IC

Features

• Floating channel up to +600 V or +1200 V

• Soft over-current shutdown

• Synchronization signal to synchronize shutdown with the other phases

• Integrated desaturation detection circuit

• Two stage turn on output for di/dt control

• Separate pull-up/pull-down output drive pins

• Matched delay outputs

• Undervoltage lockout with hysteresis band

• LEAD-FREE

Description

The IR211(4,41)/IR221(4,41) gate driver family is suited to drive a single half bridge in power switching applications. These drivers provide high gate driving capability (2 A source, 3 A sink) and require low quiescent current, which allows the use of bootstrap power supply techniques in medium power systems. These drivers feature full short circuit protection by means of power transistor desaturation detection and manage all half-bridge faults by smoothly turning off the desaturated transistor through the dedicated soft shutdown pin, therefore preventing over-voltages and reducing EM emissions. In multi-phase systems, the IR211(4,41)/ IR221(4,41) drivers communicate using a dedicated local network (SY_FLT and FAULT/SD signals) to properly manage phase-to-phase short circuits. The system controller may force shutdown or read device fault state through the 3.3 V compatible CMOS I/O pin (FAULT/SD). To improve the signal immunity from DC-bus noise, the control and power ground use dedicated pins enabling low-side emitter current sensing as well. Undervoltage conditions in floating and low voltage circuits are managed independently.

Product Summary

V

OFFSET

IO+/- (min) 1.0 A / 1.5 A

V

10.4 V – 20 V

OUT

Deadtime matching (max) 75 ns

Deadtime (typ) 330 ns

Desat blanking time (typ) 3 µs

DSH, DSL input voltage

threshold (typ)

Soft shutdown time (typ) 9.25 µs

Package

600 V or

1200 V max.

24-Lead SSOP

8.0 V

Typical connection

DC BUS

(Up t o 1200 V )

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DC+

Motor

DC-

15 V

uP,

Control

VCC

LIN

HIN

FAULT/SD

FLT_CLR

SY_F LT

VSS

IR2x14

VB

HOP

HON

SSDH

DSH

VS

LOP

LON

SSDL

DSL

COM

1

IR211(4,41)/IR221(4,41)SSPbF

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to V

, all currents are defined positive into any lead The thermal resistance

SS

and power dissipation ratings are measured under board mounted and still air conditions.

Symbol Definition Min. Max. Units

VS High side offset voltage VB - 25 VB + 0.3

VB High side floating supply voltage

(IR2114 or IR21141) -0.3 625

(IR2214 or IR22141) -0.3 1225 VHO High side floating output voltage (HOP, HON and SSDH) VS - 0.3 VB + 0.3

VCC Low side and logic fixed supply voltage -0.3 25

COM Power ground VCC - 25 V

VLO Low side output voltage (LOP, LON and SSDL) V

-0.3 VCC + 0.3

COM

CC

+ 0.3

V

VIN Logic input voltage (HIN, LIN and FLT_CLR) VSS -0.3 VCC + 0.3

V

FLT

V

DSH

V

DSL

FAULT input/output voltage (FAULT/SD and SY_FLT)

VSS -0.3 VCC + 0.3

High side DS input voltage VS -3 VB + 0.3

Low side DS input voltage

V

-3 VCC + 0.3

COM

dVs/dt Allowable offset voltage slew rate — 50 V/ns

PD Package power dissipation @ TA  25 °C — 1.5 W

RthJA Thermal resistance, junction to ambient — 65 °C/W

TJ Junction temperature — 150

TS Storage temperature -55 150

°C

TL Lead temperature (soldering, 10 seconds) — 300

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to V

. The VS offset rating is tested with all supplies biased at a 15 V differential.

SS

Symbol Definition Min. Max. Units

VB High side floating supply voltage (Note 1) VS + 11.5 VS + 20

VS

High side floating supply offset voltage

VHO High side output voltage (HOP, HON and SSDH) VS V

VLO Low side output voltage (LOP, LON and SSDL) V

VCC Low side and logic fixed supply voltage (Note 1) 11.5 20

(IR2114 or IR21141) Note 2 600

(IR2214 or IR22141) Note 2 1200

+ 20

S

VCC

COM

V

COM Power ground -5 5

VIN Logic input voltage (HIN, LIN and FLT_CLR) VSS V

V

DSH

V

DSL

Fault input/output voltage (FAULT/SD and SY_FLT)

FLT

VSS V

High side DS pin input voltage VS - 2.0 VB

Low side DS pin input voltage V

- 2.0 VCC

COM

CC

TA Ambient temperature -40 125 °C

Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables the output drivers if the UV thresholds are not reached.

: Logic operational for V

Note 2

to V

SS-VBS

. (Please refer to the Design Tip DT97-3 for more details).

from VSS-5 V to V

S

+600 V or 1200 V. Logic state held for VS from V

SS

-5 V

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2

IR211(4,41)/IR221(4,41)SSPbF

Static Electrical Characteristics

V

= 15 V, VSS = COM = 0 V, VS = 600 V or 1200 V and TA = 25 °C unless otherwise specified.

CC

Pins: VCC, VSS, VB, V

Symbol Definition Min Typ Max Units Test Conditions

V

VCC supply undervoltage positive going threshold 9.3 10.2 11.4

CCUV+

V

VCC supply undervoltage negative going threshold 8.7 9.3 10.3

CCUV-

V

VCC supply undervoltage lockout hysteresis — 0.9 —

CCUVH

V

(VB-VS) supply undervoltage positive going threshold 9.3 10.2 11.4

BSUV+

V

(VB-VS) supply undervoltage negative going threshold 8.7 9.3 10.3

BSUV-

V

(VB-VS) supply undervoltage lockout hysteresis — 0.9 —

BSUVH

ILK Offset supply leakage current — — 50

I

Quiescent VBS supply current — 400 800

QBS

I

Quiescent V

QCC

Note 1: Refer to Fig. 1

S

V

µA

supply current — 0.7 2.5 mA (No load)

CC

= 0 V, VS = 600 V

S

or 1200 V

= VS = 600 V or

B

1200 V

VIN = 0 V or 3.3 V

Pins: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT

Symbol Definition Min Typ Max Units Test Conditions

VIH Logic "1" input voltage 2.0 — —

VIL Logic "0" input voltage — — 0.8

V

Logic input hysteresis 0.2 0.4 —

IHSS

Logic “1” input bias current (HIN, LIN, FLTCLR) — 330 — Logic “0” input bias current (FAULT/SD, SY_FLT)

Logic “0” input bias current -1 — 0 Logic “1” input bias current (FAULT/SD, SY_FLT)

0 — 1

-1 — 0

FAULT/SD open drain resistance — 60 —

SY_FLT open drain resistance

— 60 —

R

I

IN+

I

IN-

ON,FLT

ON,SY

V

µA



Note 1: Refer to Figs. 2 & 3

Pins: DSL, DSH

The active bias is present only the IR21141and IR22141. V respectively for DSL and DSH.

Symbol Definition Min Typ Max Units Test Conditions

V

High desat input threshold voltage 7.2 8.0 8.8

DESAT+

V

Low desat input threshold voltage 6.3 7.0 7.7

DESAT-

V

Desat input voltage hysteresis — 1.0 —

DSTH

I

High DSH or DSL input bias current — 21 — V

DS+

IDS- Low DSH or DSL input bias current — -160 —

I

DSB

Note 1: Refer to Fig. 4

DSH or DSL input bias current (IR21141 and IR22141 only)

DESAT

, IDS and I

parameters are referenced to COM and V

DSB

V See Figs. 4,16

µA

— -20 — mA V

= VCC or VBS

DESAT

V

= 0 V

DESAT

= (VCC or VBS) – 2 V

DESAT

= V

V

CC

CCUV-

to 20 V

VIN = 3.3 V

VIN = 0 V

PW 7 µs

S

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3

IR211(4,41)/IR221(4,41)SSPbF

Pins: HOP, LOP

Symbol Definition Min Typ Max Units Test Conditions

VOH High level output voltage, VB – V

or VCC –V

HOP

— 40 300 mV IO= 20 mA

LOP

I

Output high first stage short circuit pulsed current 1 2 —

O1+

V

= 0 V, HIN

HOP/LOP

or L

= 1, PW

IN

200 ns, resistive

load, see Fig. 8

A

I

O2+

Output high second stage short circuit pulsed current

V

0.5 1 —

= 0 V, H

HOP/LOP

or LIN= 1,

400 ns PW 10

µs, resistive load,

IN

see Fig. 8

Note 1: Refer to Fig. 5

Pins: HON, LON, SSDH, SSDL

Symbol Definition Min Typ Max Units Test Conditions

VOL Low level output voltage, V

R

Soft Shutdown on resistance (Note 1) — 90 —  PW 7 µs

ON,SSD

IO- Output low short circuit pulsed current 1.5 3 — A

Note 1: SSD operation only Note 2: Refer to Fig. 6

HON

or V

— 45 300 mV IO= 20 mA

LON

V

H

IN

= 15 V,

HOP/LOP

or LIN = 0, PW

10 µs

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4

IR211(4,41)/IR221(4,41)SSPbF

AC Electrical Characteristics

VCC = VBS = 15 V, VS = VSS and TA = 25 °C unless otherwise specified.

Symbol Definition Min. Typ. Max. Units Test Conditions

ton Turn on propagation delay 220 440 660

t

Turn off propagation delay 220 440 660

off

tr Turn on rise time (C

tf Turn off fall time (C

t

Turn on first stage duration time 120 200 280 Fig. 8

on1

t

DESAT1

DSH to HO soft shutdown propagation delay at HO turn on

=1 nF) — 24 —

LOAD

=1 nF) — 7 —

LOAD

2000 3300 4600 V

= 0 & 1, VS = 0 V to 600 V

V

IN

or 1200 V,

HOP shorted to HON, LOP

shorted to LON, Fig. 7

= 1 V

HIN

t

DESAT2

t

DESAT3

t

DESAT4

DSH to HO soft shutdown propagation delay after blanking

DSL to LO soft shutdown propagation delay at LO turn on

DSL to LO soft shutdown propagation delay after blanking

1050 — — V

DESAT

2000 3300 4600 V

1050 — — V

DESAT

= 15 V, Fig. 10

= 1 V

LIN

= 15 V, Fig. 10

tDS Soft shutdown minimum pulse width of desat 1000 — — Fig. 9

tSS Soft shutdown duration period 5700 9250 13500 VDS=15 V, Fig. 9

t

SY_FLT,

DESAT1

t

SY_FLT,

DESAT2

t

SY_FLT

DESAT3

t

SY_FLT

DESAT4

DSH to SY_FLT propagation delay at HO turn on

DSH to SY_FLT propagation delay after blanking

,

DSL to SY_FLT propagation delay at LO turn on

,

DSL to SY_FLT propagation delay after blanking

— 3600 — V

1300 — — V

— 3050 — V

1050 — — V

tBL DS blanking time at turn on — 3000 —

Deadtime/Delay Matching Characteristics

ns

= 1 V

HIN

= 15 V, Fig. 10

DS

= 1 V

LIN

=15 V, Fig. 10

DESAT

V

= V

HIN

= 1 V, V

LIN

DESAT

=15 V,

Fig. 10

DT Deadtime — 330 — Fig. 11

MDT Deadtime matching, MDT=DTH-DTL — — 75 External DT = 0 s, Fig. 11

PDM

Propagation delay matching, Max (ton, toff) – Min (ton, toff)

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— — 75

External DT > 500 ns, Fig. 7

5

IR211(4,41)/IR221(4,41)SSPbF

VCC/V

B

comparator

UV

internal

signal

V

VSS/V

S

Figure 1:

FAULT/SD

SY_FLT

V

SS

Figure 3: FAULT/SD and SY_FLT Diagram Figure 4: DSH and DSL Diagram

on/off

internal signal

Figure 5: HOP and LOP Diagram Figure 6: HON, LON, SSDH and SSDL Diagram

CCUV/VBSUV

Undervoltage Diagram

fault/ hold

schmitt trigger

R

ON

interna l signal

hard/s oft shutdow n

internal signal

200ns

oneshot

VCC/V

B

V

OH

LOP/HOP

HIN/LIN/ FLTCLR

VCC/V

DSL/DSH

DESAT

V

COM/V

on/off

internal signal

desat

internal signal

V

SS

Figure 2:

BS

S

schmitt trigger

10k

HIN, LIN and FLTCLR Diagram

active

100k

bias

comparator

SSD

700k

LON/HON

SSDL/SSDH

R

ON,SSD

COM/V

internal

signal

internal

signal

V

OL

S

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6

IR211(4,41)/IR221(4,41)SSPbF

3.3V

HIN LIN

t

50% 50%

on

t

r

PW

in

PW

out

t

off

t

f

HO (HOP=HON) LO (LOP=LON)

90% 90%

10%

Figure 7: Switching Time Waveforms

Ton1

Io1+

Io2+

Figure 8: Output Source Current

3.3V

HIN/LIN

t

DS

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DSH/DSL

SSD Driver Enable

HO/LO

Figure 9:

8V

t

DESAT

Soft Shutdown Timing Waveform

8V

t

SS

7

HIN

(

IR211(4,41)/IR221(4,41)SSPbF

50%

LIN

DSH

DSL

SY_FLT

FAULT/SD

FLTCLR

10%

HON

LON

8V

50%

LIN HIN

50%

SY_FLT,DESAT1

t

tDESAT1

90%

tBL

Turn-On Propagation D elay

50%

8V

SoftShutdown

tSY_FLT,DESAT2

50%

tBL

tDESAT2

90%

50%

SoftShutdown

t

DESAT3

50%

10%

Figure 10: Desat Timing

50% 50%

50%

SY_FLT,DESAT3

90%

tBL

Turn-On Propagation Del ay

SoftShutdown

tSY_FLT,DESAT4

50%

8V

50%

Turn_Off propagation D elay

90%

t

DESAT4

90%

SoftShutdown

tBL

90%

HOP=HON)

HO

LOP=LON)

LO

50%

DTH

50%

DTL

50%

MDT=DTH-DTL

Figure 11:

Internal Deadtime Timing

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8

IR211(4,41)/IR221(4,41)SSPbF

Lead Assignments

HIN

1

24

DSH

LIN

FLT_CLR

SY_FLT

VB

N.C.

HOP

24-Lead SSOP

FAULT/SD

VSS

SSDL

COM

LON

LOP

VCC

DSL

SSOP24

12

13

Lead Definitions

Symbol Description

HON

VS

SSDH

N.C.

VCC Low side gate driver supply

VSS Logic ground

HIN Logic input for high side gate driver outputs (HOP/HON)

LIN Logic input for low side gate driver outputs (LOP/LON)

FAULT/SD

SY_FLT

FLT_CLR Fault clear active high input. Clears latched fault condition (see Fig. 17)

LOP Low side driver sourcing output

LON Low side driver sinking output

DSL Low side IGBT desaturation protection input

SSDL Low side soft shutdown

COM Low side driver return

VB High side gate driver floating supply

HOP High side driver sourcing output

HON High side driver sinking output

DSH High side IGBT desaturation protection input

SSDH High side soft shutdown

VS High side floating supply return

Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates fault condition. As an input, shuts down the outputs of the gate driver regardless H

Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates SSD sequence is occurring. As an input, an active low signal freezes both output status.

IN/LIN

status.

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9

IR211(4,41)/IR221(4,41)SSPbF

VCC

HIN

LIN

SY_FLT

FAULT/SD

FLT_CLR

VSS

UV_VCC DETECT

FAULT

SCHMITT

TRIGGER

INPUT

SHOOT

THROUGH

PREVENTION

(DT) Deadtime

UV_VCC

HOLDSSD

SD

INPUT

HOLD

LOGIC

internal Hold

FAULT LOGIC

managemend

(See figure 14)

OUTPUT

SHUTDOWN

LOGIC

Hard ShutDown

on/off (HS)

on/off (LS)

DesatHS

DesatLS

SHIFTERS

on/off

LEVEL

desat

FUNCTIONAL BLOCK DIAGRAM

Start-Up

Sequence

LATCH

LOCAL DESAT

PROTECTION

SOFT SHUTDOW N

UV_VBS DETECT

LOCAL DESAT

PROTECTION

SOFTSHUTDOW N

on/off

soft

shutdown

on/off

soft

shutdown

di/dt control Driver

VB

HOP

HON

SSDH

DSH

VS

LOP

LON

SSDL

DSL

COM

R

L

C

_

T

L

F

FAULT

DESAT EVENT

Soft

ShutDown

Stable State

FAULT

−

− HO=LO=0 (Normal operation)

− HO/LO=1 (Normal operation)

− UNDERVOLTAGE V

CC

− SHUTDOWN (SD)

− UNDERVOLTAGE V

BS

− FREEZE

T

L

F

_

Y

S

HO=LO=0

N

I

L

/

N

I

H

/ N

I

H

HO/LO=1

L

S

/

H

Y

S

_

D

F

L T

L

N

I

F

A

UnderVoltage

_

V

U

UV_VBS

U

L

T

/

S

F

V

HO=LO=0

C

V

D

A

U

L

T

/

S

D

C

C V

_

V

U

CC

UV_VCC

STATE DIAGRAM

Temporary State

SOFT SHUTDOWN

−

− START UP SEQUENCE

F

A

U

V

_

V

B

S

UnderVoltage

V

BS

HO=0, LO=LIN

U

L

T

/

S

D

ShutDown

D

S

/

T

L

U

A

F

S

Y

_

F

L

T

D

S

/

T

L

U

A

F

Freeze

L

/

H

S

D

System Variable

FLT_CLR

−

− HIN/LIN

− UV_VCC

− UV_VBS

− DSH/L

− SY_FLT

− FAULT/SD

NOTE 1: A change of logic value of the signal labeled on lines (system variable) generates a state transition. NOTE 2: Exiting from UNDERVOLTAGE V

state, the HO goes high only if a rising edge event happens in HIN.

BS

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10