International Rrectifier RECTIFIER User Manual

IR2114SSPbF/IR21141SSPbF
IR2214SSPbF/IR22141SSPbF

HALF-BRIDGE GATE DRIVER IC

Features

• Floating channel up to +600 V or +1200 V

• Soft over-current shutdown

• Synchronization signal to synchronize shutdown with the other phases

• Integrated desaturation detection circuit

• Two stage turn on output for di/dt control

• Separate pull-up/pull-down output drive pins

• Matched delay outputs

• Undervoltage lockout with hysteresis band

• LEAD-FREE

Description

The IR211(4,41)/IR221(4,41) gate driver family is suited to drive a single half
bridge in power switching applications. These drivers provide high gate driving
capability (2 A source, 3 A sink) and require low quiescent current, which allows
the use of bootstrap power supply techniques in medium power systems. These
drivers feature full short circuit protection by means of power transistor
desaturation detection and manage all half-bridge faults by smoothly turning off
the desaturated transistor through the dedicated soft shutdown pin, therefore
preventing over-voltages and reducing EM emissions. In multi-phase systems,
the IR211(4,41)/ IR221(4,41) drivers communicate using a dedicated local
network (SY_FLT and FAULT/SD signals) to properly manage phase-to-phase
short circuits. The system controller may force shutdown or read device fault
state through the 3.3 V compatible CMOS I/O pin (FAULT/SD). To improve the
signal immunity from DC-bus noise, the control and power ground use dedicated
pins enabling low-side emitter current sensing as well. Undervoltage conditions
in floating and low voltage circuits are managed independently.

Product Summary

V

OFFSET

IO+/- (min) 1.0 A / 1.5 A

V

10.4 V – 20 V

OUT

Deadtime matching (max) 75 ns

Deadtime (typ) 330 ns

Desat blanking time (typ) 3 µs

DSH, DSL input voltage

threshold (typ)

Soft shutdown time (typ) 9.25 µs

Package

600 V or

1200 V max.

24-Lead SSOP

8.0 V

Typical connection

DC BUS

(Up t o 1200 V )

www.irf.com

DC+

Motor

DC-

15 V

uP,

Control

VCC

LIN

HIN

FAULT/SD

FLT_CLR

SY_F LT

VSS

IR2x14

VB

HOP

HON

SSDH

DSH

VS

LOP

LON

SSDL

DSL

COM

1

IR211(4,41)/IR221(4,41)SSPbF

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to V

, all currents are defined positive into any lead The thermal resistance

SS

and power dissipation ratings are measured under board mounted and still air conditions.

Symbol Definition Min. Max. Units

VS High side offset voltage VB - 25 VB + 0.3

VB High side floating supply voltage

(IR2114 or IR21141) -0.3 625

(IR2214 or IR22141) -0.3 1225
VHO High side floating output voltage (HOP, HON and SSDH) VS - 0.3 VB + 0.3

VCC Low side and logic fixed supply voltage -0.3 25

COM Power ground VCC - 25 V

VLO Low side output voltage (LOP, LON and SSDL) V

-0.3 VCC + 0.3

COM

CC

+ 0.3

V

VIN Logic input voltage (HIN, LIN and FLT_CLR) VSS -0.3 VCC + 0.3

V

FLT

V

DSH

V

DSL

FAULT input/output voltage (FAULT/SD and SY_FLT)

VSS -0.3 VCC + 0.3

High side DS input voltage VS -3 VB + 0.3

Low side DS input voltage

V

-3 VCC + 0.3

COM

dVs/dt Allowable offset voltage slew rate — 50 V/ns

PD Package power dissipation @ TA  25 °C — 1.5 W

RthJA Thermal resistance, junction to ambient — 65 °C/W

TJ Junction temperature — 150

TS Storage temperature -55 150

°C

TL Lead temperature (soldering, 10 seconds) — 300

Recommended Operating Conditions

For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute
voltages referenced to V

. The VS offset rating is tested with all supplies biased at a 15 V differential.

SS

Symbol Definition Min. Max. Units

VB High side floating supply voltage (Note 1) VS + 11.5 VS + 20

VS

High side floating supply offset
voltage

VHO High side output voltage (HOP, HON and SSDH) VS V

VLO Low side output voltage (LOP, LON and SSDL) V

VCC Low side and logic fixed supply voltage (Note 1) 11.5 20

(IR2114 or IR21141) Note 2 600

(IR2214 or IR22141) Note 2 1200

+ 20

S

VCC

COM

V

COM Power ground -5 5

VIN Logic input voltage (HIN, LIN and FLT_CLR) VSS V

V

V

DSH

V

DSL

Fault input/output voltage (FAULT/SD and SY_FLT)

FLT

VSS V

High side DS pin input voltage VS - 2.0 VB

Low side DS pin input voltage V

- 2.0 VCC

COM

CC

CC

TA Ambient temperature -40 125 °C

Note 1: While internal circuitry is operational below the indicated supply voltages, the UV lockout disables
the output drivers if the UV thresholds are not reached.

: Logic operational for V

Note 2

to V

SS-VBS

. (Please refer to the Design Tip DT97-3 for more details).

from VSS-5 V to V

S

+600 V or 1200 V. Logic state held for VS from V

SS

SS

-5 V

www.irf.com

2

IR211(4,41)/IR221(4,41)SSPbF

Static Electrical Characteristics

V

= 15 V, VSS = COM = 0 V, VS = 600 V or 1200 V and TA = 25 °C unless otherwise specified.

CC

Pins: VCC, VSS, VB, V

Symbol Definition Min Typ Max Units Test Conditions

V

VCC supply undervoltage positive going threshold 9.3 10.2 11.4

CCUV+

V

VCC supply undervoltage negative going threshold 8.7 9.3 10.3

CCUV-

V

VCC supply undervoltage lockout hysteresis — 0.9 —

CCUVH

V

(VB-VS) supply undervoltage positive going threshold 9.3 10.2 11.4

BSUV+

V

(VB-VS) supply undervoltage negative going threshold 8.7 9.3 10.3

BSUV-

V

(VB-VS) supply undervoltage lockout hysteresis — 0.9 —

BSUVH

ILK Offset supply leakage current — — 50

I

Quiescent VBS supply current — 400 800

QBS

I

Quiescent V

QCC

Note 1: Refer to Fig. 1

S

V

V

V

µA

supply current — 0.7 2.5 mA (No load)

CC

= 0 V, VS = 600 V

S

or 1200 V

= VS = 600 V or

B

1200 V

VIN = 0 V or 3.3 V

Pins: HIN, LIN, FLTCLR, FAULT/SD, SY_FLT

Symbol Definition Min Typ Max Units Test Conditions

VIH Logic "1" input voltage 2.0 — —

VIL Logic "0" input voltage — — 0.8

V

Logic input hysteresis 0.2 0.4 —

IHSS

Logic “1” input bias current (HIN, LIN, FLTCLR) — 330 —
Logic “0” input bias current (FAULT/SD, SY_FLT)

Logic “0” input bias current -1 — 0
Logic “1” input bias current (FAULT/SD, SY_FLT)

0 — 1

-1 — 0

FAULT/SD open drain resistance — 60 —

SY_FLT open drain resistance

— 60 —

R

R

I

IN+

I

IN-

ON,FLT

ON,SY

V

µA



Note 1: Refer to Figs. 2 & 3

Pins: DSL, DSH

The active bias is present only the IR21141and IR22141. V
respectively for DSL and DSH.

Symbol Definition Min Typ Max Units Test Conditions

V

High desat input threshold voltage 7.2 8.0 8.8

DESAT+

V

Low desat input threshold voltage 6.3 7.0 7.7

DESAT-

V

Desat input voltage hysteresis — 1.0 —

DSTH

I

High DSH or DSL input bias current — 21 — V

DS+

IDS- Low DSH or DSL input bias current — -160 —

I

DSB

Note 1: Refer to Fig. 4

DSH or DSL input bias current
(IR21141 and IR22141 only)

DESAT

, IDS and I

parameters are referenced to COM and V

DSB

V See Figs. 4,16

µA

— -20 — mA V

= VCC or VBS

DESAT

V

= 0 V

DESAT

= (VCC or VBS) – 2 V

DESAT

= V

V

CC

CCUV-

to 20 V

VIN = 3.3 V

VIN = 0 V

PW 7 µs

S

www.irf.com

3

IR211(4,41)/IR221(4,41)SSPbF

Pins: HOP, LOP

Symbol Definition Min Typ Max Units Test Conditions

VOH High level output voltage, VB – V

or VCC –V

HOP

— 40 300 mV IO= 20 mA

LOP

I

Output high first stage short circuit pulsed current 1 2 —

O1+

V

= 0 V, HIN

HOP/LOP

or L

= 1, PW

IN

200 ns, resistive

load, see Fig. 8

A

I

O2+

Output high second stage short circuit pulsed current

V

0.5 1 —

= 0 V, H

HOP/LOP

or LIN= 1,

400 ns PW 10

µs, resistive load,

IN

see Fig. 8

Note 1: Refer to Fig. 5

Pins: HON, LON, SSDH, SSDL

Symbol Definition Min Typ Max Units Test Conditions

VOL Low level output voltage, V

R

Soft Shutdown on resistance (Note 1) — 90 —  PW 7 µs

ON,SSD

IO- Output low short circuit pulsed current 1.5 3 — A

Note 1: SSD operation only
Note 2: Refer to Fig. 6

HON

or V

— 45 300 mV IO= 20 mA

LON

V

H

IN

= 15 V,

HOP/LOP

or LIN = 0, PW

10 µs

www.irf.com

4

IR211(4,41)/IR221(4,41)SSPbF

AC Electrical Characteristics

VCC = VBS = 15 V, VS = VSS and TA = 25 °C unless otherwise specified.

Symbol Definition Min. Typ. Max. Units Test Conditions

ton Turn on propagation delay 220 440 660

t

Turn off propagation delay 220 440 660

off

tr Turn on rise time (C

tf Turn off fall time (C

t

Turn on first stage duration time 120 200 280 Fig. 8

on1

t

DESAT1

DSH to HO soft shutdown propagation delay at HO
turn on

=1 nF) — 24 —

LOAD

=1 nF) — 7 —

LOAD

2000 3300 4600 V

= 0 & 1, VS = 0 V to 600 V

V

IN

or 1200 V,

HOP shorted to HON, LOP

shorted to LON, Fig. 7

= 1 V

HIN

t

DESAT2

t

DESAT3

t

DESAT4

DSH to HO soft shutdown propagation delay after
blanking

DSL to LO soft shutdown propagation delay at LO
turn on

DSL to LO soft shutdown propagation delay after
blanking

1050 — — V

DESAT

2000 3300 4600 V

1050 — — V

DESAT

= 15 V, Fig. 10

= 1 V

LIN

= 15 V, Fig. 10

tDS Soft shutdown minimum pulse width of desat 1000 — — Fig. 9

tSS Soft shutdown duration period 5700 9250 13500 VDS=15 V, Fig. 9

t

SY_FLT,

DESAT1

t

SY_FLT,

DESAT2

t

SY_FLT

DESAT3

t

SY_FLT

DESAT4

DSH to SY_FLT propagation delay at HO turn on

DSH to SY_FLT propagation delay after blanking

,

DSL to SY_FLT propagation delay at LO turn on

,

DSL to SY_FLT propagation delay after blanking

— 3600 — V

1300 — — V

— 3050 — V

1050 — — V

tBL DS blanking time at turn on — 3000 —

Deadtime/Delay Matching Characteristics

ns

= 1 V

HIN

= 15 V, Fig. 10

DS

= 1 V

LIN

=15 V, Fig. 10

DESAT

V

= V

HIN

= 1 V, V

LIN

DESAT

=15 V,

Fig. 10

DT Deadtime — 330 — Fig. 11

MDT Deadtime matching, MDT=DTH-DTL — — 75 External DT = 0 s, Fig. 11

PDM

Propagation delay matching,
Max (ton, toff) – Min (ton, toff)

www.irf.com

— — 75

External DT > 500 ns, Fig. 7

5

IR211(4,41)/IR221(4,41)SSPbF

VCC/V

B

comparator

UV

internal

signal

V

VSS/V

S

Figure 1:

FAULT/SD

SY_FLT

V

SS

Figure 3: FAULT/SD and SY_FLT Diagram Figure 4: DSH and DSL Diagram

on/off

internal signal

Figure 5: HOP and LOP Diagram Figure 6: HON, LON, SSDH and SSDL Diagram

CCUV/VBSUV

Undervoltage Diagram

fault/ hold

schmitt
trigger

R

ON

interna l signal

hard/s oft shutdow n

internal signal

200ns

oneshot

VCC/V

B

V

OH

LOP/HOP

HIN/LIN/
FLTCLR

VCC/V

DSL/DSH

DESAT

V

COM/V

on/off

internal signal

desat

internal signal

V

SS

Figure 2:

BS

S

schmitt
trigger

10k

HIN, LIN and FLTCLR Diagram

active

100k

bias

comparator

SSD

700k

LON/HON

SSDL/SSDH

R

ON,SSD

COM/V

internal

signal

internal

signal

V

OL

S

www.irf.com

6

IR211(4,41)/IR221(4,41)SSPbF

3.3V

HIN
LIN

t

50% 50%

on

t

r

PW

in

PW

out

t

off

t

f

HO (HOP=HON)
LO (LOP=LON)

90% 90%

10%

10%

Figure 7: Switching Time Waveforms

Ton1

Io1+

Io2+

Figure 8: Output Source Current

3.3V

HIN/LIN

t

DS

www.irf.com

DSH/DSL

SSD Driver Enable

HO/LO

Figure 9:

8V

t

DESAT

Soft Shutdown Timing Waveform

8V

t

SS

7

HIN

(

(

IR211(4,41)/IR221(4,41)SSPbF

50%

50%

LIN

DSH

DSL

SY_FLT

FAULT/SD

FLTCLR

10%

HON

LON

8V

50%

LIN
HIN

50%

SY_FLT,DESAT1

t

tDESAT1

90%

tBL

Turn-On Propagation D elay

50%

8V

8V

SoftShutdown

tSY_FLT,DESAT2

50%

tBL

tDESAT2

90%

50%

SoftShutdown

t

t

DESAT3

50%

10%

Figure 10: Desat Timing

50% 50%

50%

SY_FLT,DESAT3

90%

tBL

Turn-On Propagation Del ay

SoftShutdown

tSY_FLT,DESAT4

50%

8V

50%

Turn_Off propagation D elay

90%

t

DESAT4

90%

SoftShutdown

tBL

90%

HOP=HON)

HO

LOP=LON)

LO

50%

DTH

50%

50%

DTL

50%

MDT=DTH-DTL

Figure 11:

Internal Deadtime Timing

www.irf.com

8

IR211(4,41)/IR221(4,41)SSPbF

Lead Assignments

HIN

1

24

DSH

LIN

FLT_CLR

SY_FLT

VB

N.C.

HOP

24-Lead SSOP

FAULT/SD

VSS

SSDL

COM

LON

LOP

VCC

DSL

SSOP24

12

13

Lead Definitions

Symbol Description

HON

VS

SSDH

N.C.

N.C.

N.C.

N.C.

N.C.

VCC Low side gate driver supply

VSS Logic ground

HIN Logic input for high side gate driver outputs (HOP/HON)

LIN Logic input for low side gate driver outputs (LOP/LON)

FAULT/SD

SY_FLT

FLT_CLR Fault clear active high input. Clears latched fault condition (see Fig. 17)

LOP Low side driver sourcing output

LON Low side driver sinking output

DSL Low side IGBT desaturation protection input

SSDL Low side soft shutdown

COM Low side driver return

VB High side gate driver floating supply

HOP High side driver sourcing output

HON High side driver sinking output

DSH High side IGBT desaturation protection input

SSDH High side soft shutdown

VS High side floating supply return

Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates fault condition.
As an input, shuts down the outputs of the gate driver regardless H

Dual function (in/out) active low pin. Refer to Figs. 15, 17, and 18. As an output, indicates SSD sequence
is occurring. As an input, an active low signal freezes both output status.

IN/LIN

status.

www.irf.com

9

IR211(4,41)/IR221(4,41)SSPbF

VCC

HIN

LIN

SY_FLT

FAULT/SD

FLT_CLR

VSS

UV_VCC
DETECT

FAULT

SCHMITT

TRIGGER

INPUT

SHOOT

THROUGH

PREVENTION

(DT) Deadtime

UV_VCC

HOLDSSD

SD

INPUT

HOLD

LOGIC

internal Hold

FAULT LOGIC

managemend

(See figure 14)

OUTPUT

SHUTDOWN

LOGIC

Hard ShutDown

on/off (HS)

on/off (LS)

DesatHS

DesatLS

SHIFTERS

on/off

LEVEL

desat

FUNCTIONAL BLOCK DIAGRAM

Start-Up

Sequence

LATCH

LOCAL DESAT

PROTECTION

SOFT SHUTDOW N

UV_VBS DETECT

LOCAL DESAT

PROTECTION

SOFTSHUTDOW N

on/off

soft

shutdown

on/off

soft

shutdown

di/dt control
Driver

di/dt control
Driver

VB

HOP

HON

SSDH

DSH

VS

LOP

LON

SSDL

DSL

COM

R

L

C

_

T

L

F

FAULT

DESAT
EVENT

Soft

ShutDown

Stable State

FAULT

−

− HO=LO=0 (Normal operation)

− HO/LO=1 (Normal operation)

− UNDERVOLTAGE V

CC

− SHUTDOWN (SD)

− UNDERVOLTAGE V

BS

− FREEZE

T

L

F

_

Y

S

HO=LO=0

N

I

L

/

N

I

H

/
N

I

H

HO/LO=1

L

S

/

H

Y

S

_

D

F

L
T

L

N

I

F

A

UnderVoltage

_

V

U

UV_VBS

U

L

T

/

S

F

V

HO=LO=0

C

C

V

D

A

U

L

T

/

S

D

C

C
V

_

V

U

CC

UV_VCC

STATE DIAGRAM

Temporary State

SOFT SHUTDOWN

−

− START UP SEQUENCE

F

A

U

V

_

V

B

S

UnderVoltage

V

BS

HO=0, LO=LIN

U

L

T

/

S

D

ShutDown

D

S

/

T

L

U

A

F

S

Y

_

F

L

T

D

S

/

T

L

U

A

F

Freeze

L

/

H

S

D

System Variable

FLT_CLR

−

− HIN/LIN

− UV_VCC

− UV_VBS

− DSH/L

− SY_FLT

− FAULT/SD

NOTE 1: A change of logic value of the signal labeled on lines (system variable) generates a state transition.
NOTE 2: Exiting from UNDERVOLTAGE V

state, the HO goes high only if a rising edge event happens in HIN.

BS

www.irf.com

10

IR211(4,41)/IR221(4,41)SSPbF

HO/LO Status HOP/LOP HON/LON SSDH/SSDL

0 HiZ 0 HiZ
1 1 HiZ HiZ

SSD

LO/HO Output follows inputs (in=1->out=1, in=0->out=0)

LO

/HO

n-1

Output keeps previous status

n-1

IR2214 Logic Table: Output Drivers Status Description

HiZ HiZ 0

Operation

Shutdown X X X X 0 (SD) X X 0 0

Fault Clear H

Normal

Operation

Anti Shoot

Through

Soft

Shutdown

(entering)

Soft
Shutdown
(finishing)

Freeze

Undervoltage

NOTE 1: SY_FLT automatically resets after the SSD event is over and FLT_CLR is not required. In order to avoid the
FLT_CLR conflicting with the SSD procedure, FLT_CLR should not be operated while SY_FLT is active.

Hin Lin FLT_CLR

IN LIN

1 0 0 1 1 No No 1 0

0 1 0 1 1 No No 0 1

0 0 0 1 1 No No 0 0

1 1 0 1 1 No No 0 0

1 0 0

0 1 0

X X 0

X X 0

X X X 0 (HOLD) 1 No No HO

X LIN X 1 1 No Yes 0 LO

X X X 1 0 (FAULT) Yes X 0 0

INPUTS

INPUT/OUTPUT

______

SY_FLT

SSD: desat (out)

HOLD: freezing

(in)

NOTE1

(SSD)

(SSD)

(SSD) (FAULT)

(SSD) (FAULT)

SD: shutdown (in)

FAULT: diagnostic

_________
FAULT/SD

(out)

(FAULT)

1 No No SSD 0

1 No No 0 SSD

Undervoltage

Yes: V< UV

threshold

No : V> UV

threshold

X: don’t care

VBS HO LO

V

CC

No No HO LO

No No 0 0

No No 0 0

OUTPUTS

LO

n-1

n-1

www.irf.com

11

IR211(4,41)/IR221(4,41)SSPbF

1 Features Description

1.1 Start-Up Sequence

At power supply start-up, it is recommended to keep the
FLT_CLR pin active until the supply voltages are
properly established. This prevents spurious diagnostic
signals being generated. All protection functions are
operating independently from the FLT_CLR status and
the output driver status reflects the input commands.

When the bootstrap supply topology is used for
supplying the floating high side stage, the following start­up sequence is recommended (see also Fig. 12):

1. Set V

2. Set FLT_CLR pin to HIGH level,

3. Set LIN pin to HIGH level and charge the

4. Release LIN pin to LOW level,

5. Release FLT_CLR pin to LOW level.

A minimum 15 µs LIN and FLT-CLR pulse is required.

1.2 Normal Operation Mode

After the start-up sequence has completed, the device
becomes fully operative (see grey blocks in the State
Diagram).

HIN and LIN produce driver outputs to switch
accordingly, while the input logic monitors the input
signals and deadtime (DT) prevent shoot-through events
from occurring.

1.3 Shutdown

The system controller can asynchronously command the
Hard Shutdown (HSD) through the 3.3 V compatible
CMOS I/O FAULT/SD pin. This event is not latched.

In a multi-phase system, FAULT/SD signals are or-ed so
the controller or one of the gate drivers can force the
simultaneous shutdown of the other gate drivers through
the same pin.

CC,

bootstrap capacitor,

VCC

FLT_CLR

LIN

LO

Figure 12

Start-Up Sequence

1.4 Fault Management

The IR211(4,41)/ IR221(4,41) is able to manage supply
failure (undervoltage lockout) and transistor desaturation
(on both the low and high side switches).

1.4.1 Undervoltage (UV)

The undervoltage protection function disables the
driver’s output stage which prevents the power device
from being driven when the input voltage is less than the
undervoltage threshold. Both the low side (V
and the floating side (V

supplied) are controlled by a

BS

supplied)

CC

dedicate undervoltage function.

An undervoltage event on the V
V

< UV

CC

) generates a diagnostic signal by forcing

VCC-

pin (when

CC

the FAULT/SD pin low (see FAULT/SD section and Fig.

14). This event disables both the low side and floating
drivers and the diagnostic signal holds until the
undervoltage condition is over. The fault condition is not
latched and the FAULT/SD pin is released once V
becomes higher than UV

VCC+

.

The V
the floating driver. Undervoltage on V

undervoltage protection works by disabling only

BS

does not prevent

BS

the low side driver from activating its output nor does it
generate diagnostic signals. The V
condition (V
stage in the low state. V

< UV

BS

) latches the high side output

VBS-

must exceed the UV

BS

undervoltage

BS

threshold to return the device to its normal operating
mode. To turn on the floating driver, H
asserted high (rising edge event on H

must be re-

IN

is required).

IN

1.4.2 Power Devices Desaturation

Different causes can generate a power inverter failure
(phase and/or rail supply short-circuit, overload
conditions induced by the load, etc.). In all of these fault
conditions, a large increase in current results in the
IGBT.

The IR211(4,41)/ IR221(4,41) fault detection circuit
monitors the IGBT emitter to collector voltage (V
external high voltage diode is connected between the
IGBT’s collector and the ICs DSH or DSL pins). A high
current in the IGBT may cause the transistor to
desaturate; this condition results in an increase of V

Once in desaturation, the current in the power transistor
can be as high as 10 times the nominal current.
Whenever the transistor is switched off, this high current
generates relevant voltage transients in the power stage
that need to be smoothed out in order to avoid
destruction (by over-voltage). The gate driver is able to
control the transient condition by smoothly turning off the
desaturated transistor with its integrated soft shutdown
(SSD) protection.

1.4.3 Desaturation Detection: DSH/L Function

Figure 13 shows the structure of the desaturation
sensing and soft shutdown block. This configuration is
the same for both the high and low side output stages.

CE

CC

VBS+

) (an

.

CE

www.irf.com

12

IR211(4,41)/IR221(4,41)SSPbF

on/off

DesatHS/LS

One Shot

SY_FLT

(external

hold)

FAULT/SD

(external hard

shutdown)

FLTCLR

tss

PPrreeDDrriivveer

tBL

Blanking

tDS

filter

Figure 13:

internal

HOLD

ONE

SHOT

(ton1)

desat

comparator

High and Low Side Output Stage

internal FAULT

(hard shutdown)

r

Figure 14: Fault Management Diagram

The external sensing diode should have BV > 600 V or
1200 V and low stray capacitance (in order to minimize
noise coupling and switching delays). The diode is
biased by an internal pull-up resistor R
V

CC/IDS-

or VBS/I

for IR2114 or IR2214) or by a

DS-

dedicated circuit (see the active-bias section for IR21141
and IR22141). When V

increases, the voltage at the

CE

DSH or DSL pin increases too. Being internally biased to
the local supply, the DSH/DSL voltage is automatically
clamped. When DSH/DSL exceeds the V
threshold, the comparator triggers (see Fig. 13). The
comparator’s output is filtered in order to avoid false
desaturation detection by externally induced noise;
pulses shorter than t

are filtered out. To avoid

DS

detecting a false desaturation event during IGBT turn on,
the desaturation circuit is disabled by a blanking signal
(T

, see blanking block in Fig. 13). This time is the

BL

estimated maximum IGBT turn on time and must be not
exceeded by proper gate resistance sizing. When the
IGBT is not completely saturated after T
is detected and the driver will turn off.

(equal to

DSH/L

DESAT+

, desaturation

BL

VB/Vcc

sensing

diode

HOPH/L

HONH/L

SSDH/L

Ron,ss

RDSH/L

DSH/L

VDESAT

VS/COM

SET

S

Q

R

Q

CLR

DesatHS

DesatLS

UVCC

Eligible desaturation signals initiate the SSD sequence.
While in SSD, the driver’s output goes to a high
impedance state and the SSD pull-down is activated to
turn off the IGBT through the SSDH/SSDL pin. The
SY_FLT output pin (active low, see Fig. 14) reports the
gate driver status during the SSD sequence (t

). Once

SS

the SSD has finished, SY_FLT releases, and the gate
driver generates a FAULT signal (see the FAULT/SD
section) by activating the FAULT/SD pin. This generates
a hard shutdown for both the high and low output stages
(HO=LO=low). Each driver is latched low until the fault is
cleared (see FLT_CLR).

Figure 14 shows the fault management circuit. In this
diagram DesatHS and DesatLS are two internal signals
that come from the output stages (see Fig. 13).

It must be noted that while in SSD, both the
undervoltage fault and external SD are masked until the
end of SSD. Desaturation protection is working
independently by the other control pin and it is disabled
only when the output status is off.

www.irf.com

13

IR211(4,41)/IR221(4,41)SSPbF

FAULT

VCC

LIN

HIN

FLT_CLR

SY_FLT

FAULT/SD

Figure 15:

1.4.4 Fault Management in Multi-Phase Systems

In a system with two or more gate drivers the IR2214/1
devices must be connected as shown in Fig. 15.

SY_FLT:

The bi-directional SY_FLT pins communicate

each other through a local network. The logic signal is
active low. The device that detects the IGBT
desaturation activates the SY_FLT, which is then read
by the other gate drivers. When SY_FLT is active all the
drivers hold their output state regardless of the input
signals (H

, LIN) they receive from the controller (freeze

IN

state). This feature is particularly important in phase-to­phase short circuit where two IGBTs are involved; in
fact, while one is softly shutting-down, the other must be
prevented from hard shutdown to avoid exiting SSD. In
the freeze state, the frozen drivers are not completely
inactive because desaturation detection still takes the
highest priority. SY_FLT communication has been
designed for creating a local network between the
drivers. There is no need to wire SY_FLT to the
controller.

FAULT/SD:

The bi-directional FAULT/SD pins

communicate with each other and with the system
controller. The logic signal is active low. When low, the
FAULT/SD signal commands the outputs to go off by
hard shutdown. There are three events that can force
FAULT/SD low:

1. Desaturation detection event: the FAULT/SD
pin is
FLT_CLR signal can reset it,

2. Undervoltage on V
forced low and held until the undervoltage is
active (

3. FAULT/SD is externally driven low either from
the controller or from another IR2x14/1 device.
This event is
FLT_CLR cannot disable it. Only when
FAULT/SD becomes high the device returns to
its normal operating mode.

1.5 Active Bias

For the purpose of sensing the power transistor
desaturation, the collector voltage is monitored (an
external high voltage diode is connected between the
IGBT’s collector and the IC’s DSH or DSL pin). The
diode is normally biased by an internal pull up resistor
connected to the local supply line (V
transistor is “on” the diode is conducting and the amount
of current flowing in the circuit is determined by the
internal pull up resistor value.

VB

HOP

HON

SSH

DSH

VS

LOP

IR2214

LON

SSL

DSL

COMVSS

phase U phase V phase W

SY_FLT

FAULT/SD

VCC

LIN

HIN

FLT_CLR

VB

HOP

HON

SSH

DSH

VS

LOP

IR2214

LON

SSL

DSL

COMVSS

SY_FLT

FAULT/SD

VCC

LIN

HIN

FLT_CLR

IR2214

IR2214 Used in a 3 Phase Application

latched low when SSD is over, and only a

: the FAULT/SD pin is

CC

not latched),

not latched; therefore the

or VCC). When the

B

VB

HOP

HON

SSH

DSH

VS

LOP

LON

SSL

DSL

COMVSS

In the high side circuit, the desaturation biasing current
may become relevant for dimensioning the bootstrap
capacitor (see Fig. 19). In fact, a pull up resistor with a
low resistance may result in a high current the
significantly discharges the bootstrap capacitor. For that
reason, the typical pull up resistor value is on the order
of 100 k. This is the value of the internal pull up.

While the impedance of the DSH/DSL pins is very low
when the transistor is on (low impedance path through
the external diode down to the power transistor), the
impedance is only controlled by the pull up resistor when
the transistor is off. In that case, relevant dV/dt applied
by the power transistor during the commutation at the
output results in a considerable current injected through
the stray capacitance of the diode into the desaturation
detection pin (DSH/DSL). This coupled noise may be
easily reduced be using an active bias structure for the
sensing diode.

An active bias structure is available only for the IR21141
or IR22141 versions. The DSH/DSL pins present an
active pull-up respectively to V
respectively to V

/COM.

S

and a pull-down

B/VCC,

The dedicated biasing circuit reduces the impedance on
the DSH/DSL pin when the voltage exceeds the V

DESAT

threshold (see Fig. 16). This low impedance helps in
rejecting the noise provided by the current injected by
the parasitic capacitance. When the power transistor is
fully on, the sensing diode is forward biased and the
voltage at the DSH/DSL pin decreases. At this point the
biasing circuit deactivates, in order to reduce the bias
current of the diode as shown in Fig. 16.

DSH/L

R

100K ohm

Figure 16:

-

+

T

T

A

A

S

S

E

E

D

D

V

V

R

Active Biasing

DSH/L

100 ohm

VDSH/L

1.6 Output Stage

The structure is shown in Fig. 13 and consists of two
turn on stages and one turn off stage. When the driver
turns on the IGBT (see Fig. 8), a first stage is activated
while an additional stage is maintained in the active state
for a limited time (ton1). This feature boosts the total
driving capability in order to accommodate both a fast
gate charge to the plateau voltage and dV/dt control in
switching.

At turn off, a single n-channel sinks up to 3 A (I

) and

O-

offers a low impedance path to prevent the self-turn on
due to the parasitic Miller capacitance in the power
switch.

1.7 Timing and Logic State Diagrams Description

The following figures show the input/output logic
diagram. Figure 17 shows the SY_FLT and FAULT/SD
signals as outputs, whereas Fig. 18 shows them as
inputs.

www.irf.com

14

IR211(4,41)/IR221(4,41)SSPbF

A B C D E F G

HIN

LIN

DSH

DSL

SY_FLT

FAULT/SD

FLT_CLR

HO(HOP/HON)

LO(LOP/LON)

Figure 17: I/O Timing Diagram with SY_FLT and FAULT/SD as Output

HIN

LIN

SY_FLT

FAULT/SD

FLT_CLR

HO (HOP/HON)

LO (LOP/LON)

Figure 18: I/O Logic Diagram with SY_FLT and FAULT/SD as Input

Referred to the timing diagram of Fig. 17:

A. When the input signals are on together the

outputs go off (anti-shoot through),

B. The HO signal is on and the high side IGBT

desaturates, the HO turn off softly while the
SY_FLT stays low. When SY_FLT goes high
the FAULT/SD goes low. While in SSD, if LIN
goes up, LO does not change (freeze),

C. When FAULT/SD is latched low (see

FAULT/SD section) FLT_CLR can disable it
and the outputs go back to follow the inputs,

D. The DSH goes high but this is not read

because HO is off,

E. The LO signal is on and the low side IGBT

desaturates, the low side behaviour is the
same as described in point B,

F. The DSL goes high but this is not read as LO

is off,

G. As point A (anti-shoot through).

ABCD EF

Referred to the timing diagram Fig. 18:

A. The device is in the hold state, regardless of

input variations. The hold state results as
SY_FLT is forced low externally,

B. The device outputs go off by hard shutdown,

externally commanded. A through B is the
same sequence adopted by another IR2x14x
device in SSD procedure.

C. Externally driven low FAULT/SD (shutdown

state) cannot be disabled by forcing FLT_CLR
(see FAULT/SD section),

D. The FAULT/SD is released and the outputs go

back to follow the inputs,

E. Externally driven low FAULT/SD: outputs go

off by hard shutdown (like point B),

F. As point A and B but for the low side output.

www.irf.com

15

IR211(4,41)/IR221(4,41)SSPbF

++=

⋅+++

+

−−≤

∆

V

2 Sizing Tips

2.1 Bootstrap Supply

The VBS voltage provides the supply to the high side
driver circuitry of the gate driver. This supply sits on top
of the V

voltage and so it must be floating. The

S

bootstrap method is used to generate the V
and can be used with any of the IR211(4,41)/
IR221(4,41) drivers. The bootstrap supply is formed by
a diode and a capacitor as connected in Fig. 19.

VCC

bootstrap

VCC

resistor

boot

R

bootstrap

diode

VF

VB

HOP

HON

VS

IR2214

SSDH

bootstrap

VBS

capacitor

Figure 19:

Bootstrap Supply Schematic

This method has the advantage of being simple and low
cost but may force some limitations on duty-cycle and
on-time since they are limited by the requirement to
refresh the charge in the bootstrap capacitor. Proper
capacitor choice can reduce drastically these
limitations.

2.2 Bootstrap Capacitor Sizing

To size the bootstrap capacitor, the first step is to
establish the minimum voltage drop (
have to guarantee when the high side IGBT is on.

V

If

is the minimum gate emitter voltage we want

GEmin

to maintain, the voltage drop must be:

under the condition,

>

V

where
diode forward voltage,
of low side IGBT, and
undervoltage negative going threshold.

Now we must consider the influencing factors
contributing V

is the IC voltage supply, VF is bootstrap

CC

to decrease:

BS

is emitter-collector voltage

V

CEon

V

is the high-side supply

BSUV-

− IGBT turn on required gate charge (

− IGBT gate-source leakage current (I

− Floating section quiescent current (I

− Floating section leakage current (I

− Bootstrap diode leakage current (I

− Desat diode bias when on (

−

supply

BS

DC+

VGE

ILOAD

motor

VCEon

min

−

BSUVGEVVmin

),

I

DS-

COM

) that we

∆V

BS

VVVVV −−−≤∆

CEonGEFCCBS

),

Q

G

LK_GE

),

QBS

),

LK

LK_DIODE

VFP

),

),

−

− Charge required by the internal level shifters

Q

); typical 20 nC,

(

LS

− Bootstrap capacitor leakage current (I

− High side on time (T

HON

).

LK_CAP

),

is only relevant when using an electrolytic

I

LK_CAP

capacitor and can be ignored if other types of
capacitors are used. It is strongly recommend using at
least one low ESR ceramic capacitor (paralleling
electrolytic and low ESR ceramic may result in an
efficient solution).

Then we have:

++

(

IIQQQ

QBSGELKLSGTOT

_

TIIII

)

HONDSCAPLKDIODELKLK

__

−

The minimum size of bootstrap capacitor is:

Q

TOT

C

BOOT

min

=

V

∆

BS

An example follows using IR2214SS or IR22141SS:

a) using a 25 A @ 125 °C 1200 V IGBT
(IRGP30B120KD):

• I

= 800 µA (datasheet IR2214);

QBS

= 50 µA (see Static Electrical Characteristics);

• I

LK

• Q

= 20 nC

LS

= 160 nC (datasheet IRGP30B120KD);

• Q

G

= 100 nA (datasheet IRGP30B120KD);

• I

LK_GE

• I

• I

• I

• T

= 100 µA (reverse recovery <100 ns);

LK_DIODE

= 0 (neglected for ceramic capacitor);

LK_CAP

= 150 µA (see Static Electrical Characteristics);

DS-

= 100 µs.

HON

And:

•

• V

• V

• V

V

CC

= 1 V

F

CEonmax

GEmin

= 15 V

= 3.1 V

= 10.5 V

∆V

the maximum voltage drop

becomes

BS

=−

VVVVV

min

CEonGEFCCBS

V V VV 4.01.35.10115 =−−−=

And the bootstrap capacitor is:

nC

C

BOOT

290

V

4.0

NOTICE: V

has been chosen to be 15 V. Some

CC

IGBTs may require a higher supply to work correctly
with the bootstrap technique. Also V
must be accounted in the above formulas.

nF

725

=≥

variations

CC

www.irf.com

16

IR211(4,41)/IR221(4,41)SSPbF

+

V

2.3 Some Important Considerations

Voltage Ripple: There are three different cases to
consider (refer to Fig. 19).

 I

IGBT (resulting in V

In this case we have the lowest value for VBS. This
represents the worst case for the bootstrap capacitor
sizing. When the IGBT is turned off, the V
pushed up by the load current until the high side
freewheeling diode is forwarded biased.

 I

and V

 I

freewheeling diode

In this case we have the highest value for VBS. Turning
on the high side IGBT, I
pulled up. To minimize the risk of undervoltage, the
bootstrap capacitor should be sized according to the
I

LOAD

Bootstrap Resistor: A resistor (R
with the bootstrap diode (see Fig. 19) in order to limit
the current when the bootstrap capacitor is initially
charged. We suggest not exceeding 10  to avoid
increasing the V
for charging the bootstrap capacitor or for refreshing its
charge must be verified against this time-constant.

Bootstrap Capacitor: For high
electrolytic capacitor is used, its ESR must be
considered. This parasitic resistance forms a voltage
divider with R
at the first charge of bootstrap capacitor. The voltage
step and the related speed (dV
As a general rule, ESR should meet the following
constraint.

A parallel combination of a small ceramic capacitor and
a large electrolytic capacitor is normally the best
compromise, the first capacitor posses a fast time
constant and limits the dV
equivalent resistance. The second capacitor provides a
large capacitance to maintain the V
within the desired

Bootstrap Diode: The diode must have a BV > 600 V or
1200 V and a fast recovery time (trr < 100 ns) to

< 0 A; the load current flows in the low side

LOAD

= 0 A; the IGBT is not loaded while being on

LOAD

can be neglected

CE

CEon

).

VVVV −−=

CEonFCCBS

VVV −=

FCCBS

> 0 A; the load current flows through the

LOAD

VVVV +−=

FPFCCBS

flows into it and VS is

LOAD

< 0 A case.

) is placed in series

boot

time-constant. The minimum on time

BS

T

designs where an

HON

, which generats a voltage step on V

boot

/dt) should be limited.

BS

ESR

∆V

RESR

+

BOOT

BS

.

BS

V

3≤⋅

CC

/dt by reducing the

voltage drop

BS

node is

s

BS

minimize the amount of charge fed back from the
bootstrap capacitor to V

supply.

CC

2.4 Gate Resistances

The switching speed of the output transistor can be
controlled by properly sizing the resistors controlling the
turn-on and turn-off gate currents. The following section
provides some basic rules for sizing the resistors to
obtain the desired switching time and speed by
introducing the equivalent output resistance of the gate

R

driver (

DRp

and R

DRn

).

The example shown uses IGBT power transistors and
Figure 20 shows the nomenclature used in the following
paragraphs. In addition, V
voltage,

Q

gc

and Q

indicate the gate to collector and

ge

*

indicates the plateau

ge

gate to emitter charge respectively.

I

C

GC

I

C

V

GE

C

C

t,Q

RESon

RESoff

Vge*

10%

C

RES

V

GE

t1,Q

GE

V

CE

90%

10%

t

Don

t2,Q

dV/dt

C

RES

t

SW

t

R

Figure 20: Nomenclature

2.5 Sizing The Turn-On Gate Resistor

Switching-Time: For the matters of the calculation
included hereafter, the switching time t

is defined

sw

as the time spent to reach the end of the plateau
voltage (a total

Q

has been provided to the

gc+Qge

IGBT gate). To obtain the desired switching time the

Q

gate resistance can be sized starting from

Q

, Vcc, V

gc

*

(see Fig. 21):

ge

ge

and

QQ

gegc

=

I

avg

t

sw

and

*

VVcc

−

R

=

TOT

ge

I

avg

www.irf.com

17

IR211(4,41)/IR221(4,41)SSPbF

t

+

⋅

(

I

Vcc/Vb

R

DRp

R

COM/Vs

> 7 , R



Vcc




I







O1+ ,IO2+

Figure 21: R

RRR +=

is defined by

DRp



Vcc




I

++

oo



Vcc

I

1

+

o

and t

on1

Characteristics”).

dV

out

where

R

= gate on-resistor

Gon

R

= driver equivalent on-resistance

DRp

When R

Gon

R

=

DRp

Table 1 reports the gate resistance size for two
commonly used IGBTs (calculation made using typical
datasheet values and assuming V

Output Voltage Slope: The turn-on gate resistor
R
(dV
linear behaviour, the maximum output slope can be
approximated by:

(I

can be sized to control the output slope

Gon

/dt). While the output voltage has a non-

OUT

dt

inserting the expression yielding I

=

R

TOT

C

As an example, table 2 shows the sizing of gate
resistance to get
popular IGBTs (typical datasheet values are used and

VCC= 15 V is assumed).

NOTICE

improper desaturation detection and SSD triggering.

: Turn on time must be lower than TBL to avoid

2.6 Sizing the Turn-Off Gate Resistor

The worst case in sizing the turn-off resistor R
when the collector of the IGBT in the off state is forced
to commutate by an external event (e.g., the turn-on of
the companion IGBT). In this case the dV/dt of the
output node induces a parasitic current through C
flowing in R
drop at the gate exceeds the threshold voltage of the

Goff

and R

dV

/dt= 5 V/ns when using two

out

(see Fig. 22). If the voltage

DRn

avg

C

RES

Gon

Sizing

Gon

GonDRpTOT

t



SW



1

−+



t

121

on



from “Static Electrical

= 15 V).

CC

I

avg

=

C

RESoff

RESoff

and rearranging:

avg

*

−

VVcc

ge

dV

out

⋅

d

ttwhen

>

1

onSW

ttwhen

≤

1

onSW

is

Goff

RESoff

IGBT, the device may self turn on, causing large
oscillation and relevant cross conduction.

HS Turning ON

C

RESoff

R

Goff

ON

Figure 22: R

The transfer function between the IGBT collector and
the IGBT gate then becomes:

V

ge

=

V

de

Which yields to a high pass filter with a pole at:

/1

τ

=

As a result, when
(to be verified after calculation) the transfer function can
be approximated by:

V

ge

V

de

So that

time domain.

Then the condition:

must be verified to avoid spurious turn on.

Rearranging the equation yields:

In any case, the worst condition for unwanted turn on is
with very fast steps on the IGBT collector.

In that case, the collector to gate transfer function can
be approximated with the capacitor divider:

which is driven only by IGBT characteristics.

R

DRn C

Sizing: Current Path When Low Side is

Goff

Off and High Side Turns On

1

τ is faster than the collector rise time

⋅+⋅=

)(

R −

Goff

V

<

C

RESoff

VV

⋅=

dege

OFF

IES

CRRs

⋅

)(

RESoffDRnGoff

CCRR +⋅+

IESRESoffDRnGoff

CRRs

RESoffDRnGoff

CRRV

RESoffDRnGoffge

dV

dV

RESoffDRnGoffgeth

R

)

CRRVV

⋅+=>

th

⋅

dt

C

RESoff

CC

+

IESRESoff

dV/dt

)()(1

CCRRs

+⋅+⋅+

IESRESoffDRnGoff

)()(

dV

de

⋅⋅+= )( in the

dt

out

dt

DRn

)(

www.irf.com

18

IR211(4,41)/IR221(4,41)SSPbF

As an example, table 3 reports R
above mentioned disequation) for two popular IGBTs to
withstand

dV

/dt = 5 V/ns.

out

(calculated with the

Goff

IGBT Qge Qgc Vge* tsw Iavg Rtot

IRGP30B120K(D) 19 nC 82 nC 9 V 400 ns 0.25 A

IRG4PH30K(D) 10 nC 20 nC 9 V 200 ns 0.15 A

Table 1: tsw Driven R

IGBT Qge Qgc Vge* CRESoff Rtot

IRGP30B120K(D) 19 nC 82 nC 9 V 85 pF

IRG4PH30K(D) 10 nc 20 nC 9 V 14 pF

Table 2: dV

IGBT Vth(min) CRESoff RGoff

IRGP30B120K(D) 4 85 pF RGoff  4 

IRG4PH30K(D) 3 14 pF RGoff  35 

/dt Driven R

OUT

Table 3: R

Goff

NOTICE:

to approximate a way to size the gate resistance. A
more accurate sizing may provide more precise device
and PCB (parasitic) modelling.

Gon

14
85

Sizing

The above-described equations are intended

RGon

→ std commercial value

24

Ω RTOT - RDRp = 12.7  → 10  →420 ns

40

Ω RTOT - RDRp = 32.5  → 33  →202 ns

Sizing

RGon

→ std commercial value

Ω RTOT - RDRp = 6.5  → 8.2  →4.5 V/ns
Ω RTOT - RDRp = 78  → 82  →5 V/ns

Sizing

Gon

Tsw

dVout/dt

www.irf.com

19

IR211(4,41)/IR221(4,41)SSPbF

3 PCB Layout Tips

3.1 Distance from High to Low Voltage

The IR2x14/1 pin out maximizes the distance between
floating (from DC- to DC+) and low voltage pins. It’s
strongly recommended to place components tied to
floating voltage on the high voltage side of device (V

side) while the other components are placed on the

V

S

opposite side.

3.2 Ground Plane

To minimize noise coupling, the ground plane must not
be placed under or near the high voltage floating side.

3.3 Gate Drive Loops

Current loops behave like antennas and are able to
receive and transmit EM noise. In order to reduce the
EM coupling and improve the power switch turn on/off
performances, gate drive loops must be reduced as
much as possible. Figure 23 shows the high and low
side gate loops.

Moreover, current can be injected inside the gate drive
loop via the IGBT collector-to-gate parasitic
capacitance. The parasitic auto-inductance of the gate
loop contributes to developing a voltage across the
gate-emitter, increasing the possibility of self turn-on.
For this reason, it is strongly recommended to place the
three gate resistances close together and to minimize
the loop area (see Fig. 23).

IGC

VB/ VCC

H/LOP
H/LON

SSDH/L

gate

resistance

Gate Drive

Loop

CGC

VGE

,

B

3.5 Routing and Placement Example

Figure 24 shows one of the possible layout solutions
using a 3 layer PCB. This example takes into account
all the previous considerations. Placement and routing
for supply capacitors and gate resistances in the high
and low voltage side minimize the supply path loop and
the gate drive loop. The bootstrap diode is placed under
the device to have the cathode as close as possible to
the bootstrap capacitor and the anode far from high
voltage and close to V

V

GH

V

GL

V

EH

V

CC

V

EL

.

CC

R2

R3

R4

IR2214

R5

R6

C2

R7

a) Top Layer

C1

D1

R1

b) Bottom Layer

D2

DC+

D3

Phase

VS/COM

Figure 23: gate drive loop

3.4 Supply Capacitors

The IR2x14x output stages are able to quickly turn on
an IGBT, with up to 2 A of output current. The supply
capacitors must be placed as close as possible to the
device pins (V
and V

for the floating supply) in order to minimize

S

and VSS for the ground tied supply, VB

CC

parasitic inductance/resistance.

www.irf.com

c) Ground Plane

Figure 24:

layout example

Information below refers to Fig. 24:
Bootstrap section: R1, C1, D1
High side gate: R2, R3, R4
High side Desat: D2
Low side supply: C2
Low side gate: R5, R6, R7
Low side Desat: D3

20

IR211(4,41)/IR221(4,41)SSPbF

Figures 25-83 provide information on the experimental performance of the IR211(4,41)/ IR221(4,41)SSPbF HVIC. The
line plotted in each figure is generated from actual lab data. A large number of individual samples from multiple wafer lots
were tested at three temperatures (-40 ºC, 25 ºC, and 125 ºC) in order to generate the experimental (Exp.) curve. The
line labeled Exp. consist of three data points (one data point at each of the tested temperatures) that have been
connected together to illustrate the understood trend. The individual data points on the curve were determined by
calculating the averaged experimental value of the parameter (for a given temperature).

10.30

10.25

10.20

Threshold (V)

10.15

10.10

CCUV+

V

10.05

Exp.

10.00

9.95

-50 -25 0 25 50 75 100 125

Figure 25. V

Temperature (

Threshold vs. Temperature

CCUV+

o

C)

9.60

9.55

9.50

9.45

Threshol d (V)

9.40

9.35

CCUV-

V

9.30

9.25

Exp .

9.20

9.15

-50 -25 0 25 50 75 100 125

o

C)

Figure 26. V

Temperature (

Threshold vs. Tempe rature

CCUV-

10.45

10.40

10.35

10.30

10.25

10.20

10.15

Threshol d Threshold (V)

10.10

Exp .

10.05

BSUV+

V

10.00

-50 -25 0 25 50 75 100 125

Figure 27. V

Temperature (

Threshold vs. Tempe rature

BSUV+

o

C)

9.70

9.65

9.60

9.55

9.50

9.45

9.40

ThresholdThreshold (V)

9.35

Exp .

BSUV-

9.30

V

9.25

-50 -25 0 25 50 75 100 125

o

C)

Figure 28. V

Temperature (

Threshold vs. Temperature

BSUV-

600

500

400

300

Exp .

200

Quiescent Current (uA)

BS

100

V

0

-50 -25 0 25 50 75 100 125

o

C)

Figure 29. V

Temperature (

Quiescent Current vs. Temperature

BS

1.00

0.90

0.80

0.70

Exp .

0.60

0.50

0.40

0.30

Quiescent Current (mA )

0.20

CC

V

0.10

0.00

-50 -25 0 25 50 75 100 125

o

C)

Figure 30. V

Temperature (

Quiescent Current vs. Temperature

CC

www.irf.com

21

IR211(4,41)/IR221(4,41)SSPbF

2.70

2.10

2.30

1.80

1.90

Exp .

Logic I nput Voltage (V)

1.50

IH

V

1.10

-50 -25 0 25 50 75 100 125

o

Temperature (

Figure 31. VIH Logic Input Voltage vs. Temperature

C)

1.50

Logic Input Volt age (V)

Exp .

IL

1.20

V

0.90

-50 -25 0 25 50 75 100 125

Temperature (

Figure 32. VIL Logic Input Vol tage vs. Tempera ture

o

C)

0.60

0.50

0.40

0.30

0.20

0.10

0.00

VIHSS HIN Logic Input Hy steres is (V)

Exp .

-50 -25 0 25 50 75 100 125

o

C)

Figure 33. V

Temperature (

HIN Logic Input Hysteresis vs.

IHSS

Temperature

2.20

1.90

Exp .

1.60

1.30

LIN Logic "1" Input Voltage (V)

1.00

-50 -25 0 25 50 75 100 125

o

Temperature (

Figure 34. LIN Logic "1" Input Vol tage vs. Temperature

C)

1.90

1.60

1.30

Exp .

1.00

LIN Logic "0" Input Voltage (V)

0.70

-50 -25 0 25 50 75 100 125

o

Temperature (

Figure 35. LIN Logic "0" Input Voltage vs. Temperature

C)

0.90

0.70

Exp .

0.50

0.30

LIN Logic Input Hysteresis (V)

IHSS

0.10

V

-50 -25 0 25 50 75 100 125

o

C)

Figure 36. V

Temperature (

LIN Logic Input Hysteresis vs.

IHSS

Temperature

www.irf.com

22

IR211(4,41)/IR221(4,41)SSPbF

2.30

1.70

2.00

Exp .

1.70

1.40

FLTCLR Logic Input Voltage (V)

1.10

IH

-50 -25 0 25 50 75 100 125

V

o

C)

Figure 37. V

Temperature (

FLTCLR Logic Input Voltage vs.

IH

Temperature

1.40

Exp .

1.10

0.80

-50 -25 0 25 50 75 100 125

VIL FLTCLR Logic Input Hys teresis (V)

Figure 38. V

Temperature (

FLTCLR Logic Input Voltage vs.

IL

Temperature

o

C)

0.60

0.50

Exp .

0.40

0.30

FLTCLR Logic Input Hysteresis (V)

0.20

-50 -25 0 25 50 75 100 125

IHSS

V

Figure 39. V

Temperature (

FLTCLR Logic Input Hysteresis vs.

IHSS

Temperature

o

C)

2.10

Exp .

1.70

1.30

0.90

VIH SD Logic Input Voltage (V)

0.50

-50 -25 0 25 50 75 100 125

o

C)

Figure 40. V

Temperature (

SD Logic Input Voltage vs. Tempera ture

IH

2.10

0.60

1.70

1.30

Exp .

0.50

0.40

Exp .

0.90

SD Logic Input Voltage (V)

IL

V

0.50

-50 -25 0 25 50 75 100 125

o

C)

Figure 41. V

Temperature (

SD Logic Input Voltage vs. Tempe rature

IL

www.irf.com

0.30

SD Logic Input Hysteresis (V )

0.20

IHSS

-50 -25 0 25 50 75 100 125

V

o

C)

Figure 42. V

Temperature (

SD Logic Input Hysteresis vs. Temperature

IHSS

23

IR211(4,41)/IR221(4,41)SSPbF

5

2.40

2.40

2.00

Exp .

1.60

1.20

SYFLT Logic Input Voltage (V)

0.80

IH

V

-50 -25 0 25 50 75 100 125

Figure 43. VIH SYFLT Logic Input Voltage vs. Temperature

Temperature (

o

C)

2.00

1.60

Exp.

1.20

SYFLT Logic Input Voltage (V)

0.80

IL

V

-50 -25 0 25 50 75 100 125

Temperature (

Figure 44. VIL SYFLT Logic Input Volta ge vs. Tempera ture

o

C)

0.60

0.50

Exp .

0.40

0.30

60

50

40

LO (mV)

OL

V

Exp .

30

SYFLT Logic Input Hysteresis (V)

0.20

IHSS

-50 -25 0 25 50 75 100 12

V

Figure 45. V

Temperature (oC)

SYFLT Logic Input Hysteresis vs.

IHSS

Temperature

20

-50 -25 0 25 50 75 100 125

o

C)

Figure 46. V

Temperature (

LO vs. Tempera ture

OL

900

725

550

LO (mV)

OH

Exp .

V

375

65

55

45

Exp .

35

VOL HO (mV)

200

-50 -25 0 25 50 75 100 125

Temperature (

Figure 47. VOH LO vs. Temperature

o

C)

www.irf.com

25

-50 -25 0 25 50 75 100 125

Temperature (

Figure 48. VOL HO vs. Temperature

o

C)

24

IR211(4,41)/IR221(4,41)SSPbF

900

725

9

Exp .

8

Input Voltage (V)

550

HO (mV)

OH

V

375

Exp .

200

-50 -25 0 25 50 75 100 125

Figure 49. V

Temperature (

HO vs. Te mpe rature

OH

o

C)

7

DSH

6

DSH+

V

5

-50 - 25 0 25 50 75 100 125

o

C)

Figure 50. V

Temperature (

DSH Input Voltage vs. Temperature

DSH+

9

8.30

9

8

DSL Input Voltage (V)

Exp .

DSL+

8

V

7

-50 -25 0 25 50 75 100 125

Figure 51. V

Temperature (

DSL Input Voltage vs. Temperature

DSL+

o

C)

7.60

Exp .

6.90

DSH Input Voltage (V)

DSH-

6.20

V

5.50

-50 -25 0 25 50 75 100 125

o

C)

Figure 52. V

Temperature (

DSH Input Voltage vs. Temperature

DSH-

8.00

7.50

DSL Input Voltage (V)

DSL-

V

7.00

6.50

Exp .

90

75

60

45

Exp .

6.00

-50 -25 0 25 50 75 100 125

o

C)

Figure 53. V

Temperature (

DSL Input Voltage vs. Tempera ture

DSL-

www.irf.com

30

-50-250255075100125

FAULT/SD Open Drain Resistance ()

Temperature (

Figure 54. FAULT/SD Open Drai n Resistance vs.

Temperature

o

C)

25

IR211(4,41)/IR221(4,41)SSPbF

)

)

)

130

490

105

430

80

55

Exp .

370

310

DTL Off Deadtime (ns

Exp .

30

SY_FLT Open Drain Resistance ()

-50 -25 0 25 50 75 100 125

Figure 55. SY_FLT Open Drain Resistance vs. Temperature

Temperature (

o

C)

250

-50 -25 0 25 50 75 100 125

Temperature (

Figure 56. DTL Off Deadtime vs. Temperature

o

C)

490

780

430

Exp .

370

DTH Off Deadtime (ns

310

250

-50 -25 0 25 50 75 100 125

Fi gu re 57. DTH Off De adti m e vs. Te m pe r a ture

Temperature (

o

C)

660

540

Exp .

420

TonH Propagation Delay (ns)

300

-50 -25 0 25 50 75 100 125

o

Temperature (

Figure 58. TonH Propagation Delay vs. Tempera ture

C)

780

660

540

420

Exp .

Toff H Propagation Delay (ns

300

-50 -25 0 25 50 75 100 125

o

Temperature (

Figure 59. ToffH Propagati on Delay vs. Tempera ture

C)

32

28

24

20

Exp .

16

TrH Turn On Ri se Time (ns)

12

-50 -25 0 25 50 75 100 125

Temperature (

Figure 60. TrH Turn On Rise Time vs. Temperature

o

C)

www.irf.com

26

IR211(4,41)/IR221(4,41)SSPbF

)

)

18

780

15

660

12

Exp .

9

TfH Turn Off Fall Time (ns)

6

-50 -25 0 25 50 75 100 125

Figure 61. TfH Turn Off Fall Time vs. Temperature

Temperature (

o

C)

540

Exp .

420

TonL Propagation Delay (ns)

300

-50 -25 0 25 50 75 100 125

Temperature (

Figure 62. TonL Propagati on Delay vs. Temperature

o

C)

780

660

40

33

540

Exp .

420

Toff L Propagation Delay (ns

300

-50 -25 0 25 50 75 100 125

Figure 63. ToffL Propagation Delay vs. Tempe rature

Temperature (

o

C)

26

Exp .

19

TrL Turn On Rise Time (ns

12

-50 -25 0 25 50 75 100 125

o

Temperature (

Figure 64. TrL Turn On Rise Time vs. Temperature

C)

20

16

12

Exp .

TfL Tu rn Off Fal l Time (n s)

8

6

5

Exp .

(us)

4

DSAT1

t

3

4

-50 -25 0 25 50 75 100 125

Figure 65. TfL Turn Off Fall Time vs. Temperature

Temperature (

o

C)

2

-50 -25 0 25 50 75 100 125

o

C)

vs. Temperature

Figure 66. t

Temperature (

DSAT1

www.irf.com

27

IR211(4,41)/IR221(4,41)SSPbF

3

6

3

5

(us)

2

Exp .

DSAT2

t

2

1

-50 -25 0 25 50 75 100 125

o

C)

Figure 67. t

Temperature (

vs. Temperature

DSAT2

Exp .

4

(us)

DSAT3

3

t

2

-50 -25 0 25 50 75 100 125

o

C)

vs. Temperature

Figure 68. t

Temperature (

DSAT3

4.50

17

3.50

(us)

2.50

Exp .

DSAT4

t

1.50

0.50

-50 -25 0 25 50 75 100 125

Figure 69. t

Temperature (

vs. Temperature

DSAT4

o

C)

14

Exp .

11

tSSH (us)

8

5

-50-250255075100125

o

C)

Figure 70. t

Temperature (

vs. Temperature

SSH

17

1.80

14

Exp.

11

(us)

SSL

t

8

1.45

1.10

Exp .

0.75

5

-50 -25 0 25 50 75 100 125

o

C)

Figure 71. t

Temperature (

vs. Temperature

SSL

www.irf.com

IO2+H SC Pulsed Current (A)

0.40

-50 -25 0 25 50 75 100 125

o

Temperature (

Figure 72. IO2+H SC Pulsed Current vs. Temperature

C)

28

IR211(4,41)/IR221(4,41)SSPbF

1.80

3.25

1.45

IO2+L SC Pulsed Current (A)

Exp .

1.10

0.75

0.40

-50 -25 0 25 50 75 100 125

Temperature (

Figure 73. IO2+L SC Pulsed Current vs. Temperature

o

C)

2.80

Exp .

2.35

1.90

IO-H SC Pulsed Current (A)

1.45

-50 -25 0 25 50 75 100 125

Temperature (

Figure 74. IO-H SC Pulsed Current vs. Temperature

o

C)

3.50

900

3.05

IO-L SC Pulsed Current (A)

Exp .

2.60

2.15

1.70

1.25

-50 -25 0 25 50 75 100 125

Temperature (

Figure 75. IO-L SC Pulsed Current vs. Tempe rature

o

C)

700

Exp .

500

tON1H (ns)

300

100

-50 -25 0 25 50 75 100 125

o

C)

Figure 76. t

Temperature (

vs. Temperature

ON1H

500

3.00

400

2.50

Exp .

(ns)

300

ON1L

t

200

100

-50 -25 0 25 50 75 100 125

o

C)

Figure 77. t

Temperature (

vs. Temperature

ON1L

2.00

Exp .

1.50

IO1+H SC Pulsed Current (A)

1.00

-50 -25 0 25 50 75 100 125

Temperature (

Figure 78. IO1+H SC Pulsed Current vs. Temperature

o

C)

www.irf.com

29

IR211(4,41)/IR221(4,41)SSPbF

4

900

3

700

Exp .

2

500

1

IO1+L SC Pulsed Current (ns)

0

-50 -25 0 25 50 75 100 125

Figure 79. IO1+L SC Pulsed Current vs. Temperature

Temperature (

o

C)

300

Exp .

100

Logic "1" Input Bias Current (uA)

-50 -25 0 25 50 75 100 125

HIN+

I

Figure 80. I

Temperature (

Logic "1" Input Bia s Current vs.

HIN+

Temperature

o

C)

0.02

(uA)

-0.03

Exp .

-0.08

-0.13

-0.18

-0.23

-0.28

Logic "0" Input Bias Current

-50 -25 0 25 50 75 100 125

HIN-

I

Figure 81. I

Temperature (

Logic "0" Input Bias Currentvs.

HIN-

Temperature

o

C)

900

700

500

300

Exp .

100

Logic "1" Input Bias Current (uA)

-50 -25 0 25 50 75 100 125

LIN+

I

Figure 82. I

Temperature (

Logic "1" Input Bia s Current vs.

LIN+

Temperature

o

C)

0.02

-0.03

-0.08

Exp .

-0.13

-0.18

-0.23

-0.28

Logic "0" Input Bias Current (uA)

-50 -25 0 25 50 75 100 125

LIN-

I

Figure 83. I

Temperature (

Logic "0" Input Bias Current vs.

LIN-

Temperature

o

C)

www.irf.com

30

Case Outline

IR211(4,41)/IR221(4,41)SSPbF

www.irf.com

31

IR211(4,41)/IR221(4,41)SSPbF

E

N

F

OTE : CONTRO LLING

DIMENSION IN MM

CARRIER TAPE DIMENSION FOR 24SSOP:2000 units per reel

Code Min Max Min Max
A 11.90 12.10 0.468 0.476
B 3.90 4.10 0.153 0.161
C 15.70 16.30 0.618 0.641
D 7.40 7.60 0.291 0.299
E 8.30 8.50 0.326 0.334
F 8.50 8.70 0.334 0.342
G 1.50 n/a 0.059 n/a
H 1.50 1.60 0.059 0.062

REEL DIMENSIONS FOR 24SSOP

Code Min Max Min Max
A 329.60 330.25 12.976 13.001
B 20.95 21.45 0.824 0.844
C 12.80 13.20 0.503 0.519
D 1.95 2.45 0.767 0.096
E 98.00 102.00 3.858 4.015
F n/a 22.40 n/a 0.881
G 18.50 21.10 0.728 0.830
H 16.40 18.40 0.645 0.724

LOADED TAPE FEED DIRECTION

B

F

C

E

G

H

A

A

G

Metric Imperial

B

D

Metric Imperial

H

D

C

A

www.irf.com

32

IR211(4,41)/IR221(4,41)SSPbF

This part has been qualified per industrial level

http://www.irf.com Data and specifications subject to change without notice. 1/25/2008

WORLDWIDE HEADQUARTERS: 233 Kansas Street, El Segundo, CA 90245 Tel: [phone]

LEAD-FREE PART MARKING INFORMATION

Part number

Date code

Pin 1

Identifier

?

MARKING CODE

Lead Free Released

P

Non-Lead Free

Relased

ORDER INFORMATION

24-Lead SSOP IR2114SSPbF
24-Lead SSOP IR21141SSPbF
24-Lead SSOP IR2214SSPbF
24-Lead SSOP IR22141SSPbF

24-Lead SSOP Tape & Reel IR2114SSPbF
24-Lead SSOP Tape & Reel IR21141SSPbF
24-Lead SSOP Tape & Reel IR2214SSPbF
24-Lead SSOP Tape & Reel IR22141SSPbF

IRxxxxx

YWW?

?XXXX

(P rod mode – 4 digit SP N code)

Assembly site code
Per SCOP 200-002

IR logo

Lot C ode

www.irf.com

33