International Rrectifier IRS2308SPbF User Manual

Data Sheet No.PD60266

IRS2308

(S)PbF

HALF-BRIDGE DRIVER

Features

Floating channel designed for bootstrap operation

•

Fully operational to +600 V

•

Tolerant to negative transient voltage, dV/dt

•

immune Gate drive supply range from 10 V to 20 V

•

Undervoltage lockout for both channels

•

3.3 V, 5 V, and 15 V input logic compatible

•

Cross-conduction prevention logic

•

Matched propagation delay for both channels

•

Outputs in phase with inputs

•

Logic and power ground +/- 5 V offset.

•

Internal 540 ns deadtime

•

Lower di/dt gate driver for better

•

noise immunity

Description

The IRS2308/IRS23084 are high voltage, high speed power MOSFET and IGBT drivers with dependent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 V.

Feature Comparison

Part

2106 21064 2108 Internal 540 COM

21084

2109 Internal 540 COM

21094

2304

2308

Packages

8-Lead SOIC

IRS2308S

Input logic

HIN/LIN no none

LIN

HIN/

IN/SD yes HIN/LIN

HIN/LIN yes

Crossconduction prevention

logic

yes

Deadtime

(ns)

Programmable 540 - 5000

Programmable 540 - 5000 VSS/COM

Internal 100 Internal 540 COM 220/200

8-Lead PDIP

IRS2308

Ground Pins

COM

V

SS/COM

VSS/COM

COM

Ton/Toff

(ns)

220/200

750/200 160/140

Typical Connection

up to 600 V

V

CC

V

CC

HIN

LIN

(Refer to L ead Assignments for correct pin configuration). This diagram shows electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

HIN LIN

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V

HO

V

LOCOM

B

S

TO

LOAD

IRS2308(S)PbF

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

IN

dVS/dt Allowable offset supply voltage transient — 50 V/ns

P

D

Rth

JA

T

J

T

S

T

L

High side floating absolute voltage -0.3 625 High side floating supply offset voltage VB - 25 VB + 0.3 High side floating output voltage VS - 0.3 V Low side and logic fixed supply voltage -0.3 25 Low side output voltage -0.3 VCC + 0.3 Logic input voltage (HIN & LIN ) VSS - 0.3 V

Package power dissipation @ TA ≤ +25 °C

Thermal resistance, junction to ambient

Junction temperature — 150 Storage temperature -50 150 Lead temperature (soldering, 10 seconds) — 300

(8 lead PDIP) — 1.0

(8 lead SOIC) — 0.625 (8 lead PDIP) — 125 (8 lead SOIC) — 200

CC

B

+ 0.3

V

W

°C/W

°C

Recommended Operating Conditions

The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset rating are tested with all supplies biased at a 15 V differential.

Symbol Definition Min. Max. Units

VB High side floating supply absolute voltage VS + 10 VS + 20 V

S

V

HO

V

CC

V

LO

V

IN

T

A

Note 1: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip DT97-3 for more details).

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High side floating supply offset voltage Note 1 600 High side floating output voltage V Low side and logic fixed supply voltage 10 20 Low side output voltage 0 V Logic input voltage COM V Ambient temperature -40 125

S

V

CC

B

V

°C

IRS2308(S)PbF

Dynamic Electrical Characteristics

V

(VCC, VBS) = 15 V, VSS = COM, CL = 1000 pF, TA = 25 °C, DT = VSS unless otherwise specified.

BIAS

Symbol Definition Min. Typ. Max. Units Test Conditions

t

on

t

off

MT Delay matching | ton - t

t

DT

MDT Deadtime matching = | DT

Static Electrical Characteristics

V

BIAS

eters are referenced to VSS/COM and are applicable to the respective input leads: HIN and LIN. The VO, IO, and R parameters are referenced to COM and are applicable to the respective output leads: HO and LO.

Symbol Definition Min. Typ. Max. Units T est Conditions

V

V V V

I

LK

I

QBS

I

QCC

I

IN+

I

IN-

V

CCUV+

V

BSUV+

V

CCUV-

V

BSUV-

V

CCUVH

V

BSUVH

I

O+

I

Turn-on propagation delay — 220 300 VS = 0 V Turn-off propagation delay — 200 280 VS = 0 V or 600 V

off

|

Turn-on rise time — 100 220

r

Turn-off fall time — 35 80

f

Deadtime: LO turn-off to HO turn-on(DT HO turn-off to LO turn-on (DT

LO-HO

(VCC, VBS) = 15 V, VSS = COM, DT= VSS and TA = 25 °C unless otherwise specified. The VIL, V

Logic “1” input voltage for HIN & LIN 2.5 — —

IH

Logic “0” input voltage for HIN & LIN — — 0.8

IL OH OL

O-

High level output voltage, V Low level output voltage, V Offset supply leakage current — — 50 VB = VS = 600 V Quiescent VBS supply current 20 60 150 Quiescent VCC supply current 0.4 1.0 1.6 mA Logic “1” input bias current — 5 20 HIN = 5 V, LIN = 5 V Logic “0” input bias current — 1 2 HIN = 0 V, LIN = 0 V VCC and VBS supply undervoltage positive going threshold VCC and V threshold

Hysteresis 0.3 0.7 —

Output high short circuit pulsed current 97 290 —

Output low short circuit pulsed current 250 600 —

supply undervoltage negative going

BS

BIAS

O

- V

- DT

O

LO-HO) &

HO-LO)

HO-LO

—046

400 540 680

—060

|

— 0.05 0.2 — 0.02 0.1

8.0 8.9 9.8

7.4 8.2 9.0

ns

V

µA

V

mA

VS = 0 V

and IIN param-

IH,

VCC = 10 V to 20 V

V

IN

PW ≤ 10 µs

on

IO = 2 mA

= 0 V or 5 V

VO = 0 V,

VO = 15 V,

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Functional Block Diagram

IR2308

HIN

VSS/COM

LEVEL

SHIFT

PULSE

GENERATOR

HV

LEVEL

SHIFTER

IRS2308(S)PbF

UV

PULSE FILTER

DETECT

R

Q

R S

VB

HO

VS

LIN

DT

VSS

DEADTIME &

SHOOT-THROUGH

PREVENTION

VSS/COM

LEVEL

SHIFT

DELAY

UV

DETECT

VCC

LO

COM

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Lead Definitions

Symbol Description

HIN Logic input for high side gate driver output (HO), in phase LIN Logic input for low side gate driver output (LO), in phase V

B

HO High side gate driver output V

S

V

CC

LO Low side gate driver output COM Low side return

High side floating supply

High side floating supply return Low side and logic fixed supply

IRS2308(S)PbF

Lead Assignments

1

V

CC

2

HIN

3

LIN

4

COM

8 Lead PDIP 8 Lead SOIC

V

HO

V LO

8

B

7 6

S

5

1

V

CC

2

HIN

3

LIN

4

COM

IRS2308PbF IRS2308SPbF

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V

HO

V LO

8

B

7 6

S

5

LIN

IRS2308(S)PbF

HIN

50%

LIN

HIN

HO

LO

Figure 1. Input/Output Timing Diagram Figure 2. Switching Time Waveform Definitions

LIN

50

HIN

%

LO

50 %

90%

t

on

t

r

t

off

t

f

90% 90%

10% 10%

HO

LO

DT

LO-HO

90%

MDT=

DT

10%

LO-HO

- DT

DT

HO-LO

10%

HO-LO

Figure 3. Deadtime Waveform Definitions

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IRS2308(S)PbF

)

500

400

300

Max.

200

Typ.

100

Turn-on Delay Tim e (ns

Turn-On Delay Time (ns)

0

-50-250 255075100125

o

Temperature(

Temperature (oC)

Figure 4A. Turn-On T ime

Figure 4A. Turn-On Time

vs. Temperature

C)

500

400

300

Max.

200

100

Typ.

Turn-O ff Time (ns

Turn-Off Time (ns)

500

400

Max.

300

Typ.

200

100

Turn-on Delay Time (ns

Turn-On Delay Time (ns)

0

10 12 14 16 18 20

V

Supply Voltage (V)

V

BIAS

Figure 4B. Turn-On Time

Figure 4B. Turn-On T ime

vs. Supply Voltage

vs. Supply Volt age

500

400

Max.

300

Typ.

200

Turn-Off Time (ns)

T u rn-Off Time (ns

100

0

-50 -25 0 25 50 75 100 125

Temperature (oC)

Temperature(

Figure 5A. Turn-Off Prop agation Delay

Figure 5A. Turn-Off Propagation Delay

vs. Temperature

o

C)

0

10 12 14 16 18 20

Supply Voltage (V)

V

Supply Voltage (V)

BIAS

Figure 5B . Turn-Off Propagation Delay vs.

Figure 5B. Turn-Off Prop agation Delay

vs. Supply Volt age

Supply Voltage

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