International Rrectifier IRS2111SPbF User Manual
Data Sheet No. PD60253
IRS2111(S)PbF
HALF-BRIDGE DRIVER
Features
Product Summary
• Floating channel designed for bootstrap operation
• Fully operational to +600 V
• Tolerant to negative transient voltage, dV/dt
immune
• Gate drive supply range from 10 V to 20 V
• Undervoltage lockout for both channels
• CMOS Schmitt-triggered inputs with pull-down
• Matched propagation delay for both channels
• Internally set deadtime
• High side output in phase with input
Deadtime (typ.) 650 ns
Description
The IRS2111 is a high voltage, high speed power MOSFET and
IGBT driver with dependent high and low side referenced output channels designed for half-bridge applications. Proprietary
HVIC and latch immune CMOS technologies enable ruggedized
monolithic construction. Logic input is compatible with standard
CMOS outputs. The output drivers feature a high pulse current
buffer stage designed for minimum driver cross-conduction. Internal deadtime is provided to avoid shoot-through in the output
half-bridge. The floating channel can be used to drive an Nchannel power MOSFET or IGBT in the high side configuration
which operates up to 600 V.
V
OFFSET
600 V max.
IO+/- 200 mA / 420 mA
V
OUT
t
(typ.) 750 ns & 150 ns
on/off
10 V - 20 V
Packages
8-Lead PDIP
IRS2111PbF
8-Lead SOIC
IRS21111SPbF
Typical Connection
up to 600 V
V
CC
V
CC
IN
(Refer to L ead Assignments for correct pin configuration). This diagram shows electrical connections only. Please
refer to our Application Notes and DesignTips for proper circuit board layout.
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IN
COM
LO
V
HO
V
B
TO
S
LOAD
IRS2111(S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figs. 7 through 10.
Symbol Definition Min. Max. Units
V
B
V
S
V
HO
V
CC
V
LO
V
IN
dVs/dt Allowable offset supply voltage transient (Fig. 2) — 50 V/ns
P
D
Rth
JA
T
J
T
S
T
L
Note 1: All supplies are fully tested at 25 V, and an internal 20 V clamp exists for each supply
High side floating supply voltage -0.3 625 (Note 1)
High side floating supply offset voltage VB - 25 VB + 0.3
High side floating output voltage VS - 0.3 V
B
+ 0.3
Low side and logic fixed supply voltage -0.3 25 (Note 1)
Low side output voltage -0.3 VCC + 0.3
Logic input voltage -0.3 V
Package power dissipation @ TA ≤ +25°C
(8 lead SOIC) — 0.625
Thermal resistance, junction to ambient
(8 Lead PDIP) — 1.0
(8 lead PDIP) — 125
(8 lead SOIC) — 200
CC
+ 0.3
Junction temperature — 150
Storage temperature -55 150
Lead temperature (soldering, 10 seconds) — 300
V
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at a 15 V differential.
Symbol Definition Min. Max. Units
V
B
V
S
V
HO
V
CC
V
LO
V
IN
T
A
Note 2: Logic operational for VS of -5 V to +600 V. Logic state held for VS of -5 V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
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High side floating supply absolute voltage VS + 10 VS + 20
High side floating supply offset voltage Note 2 600
High side floating output voltage V
S
V
B
Low side and logic fixed supply voltage 10 20
Low side output voltage 0 V
Logic input voltage 0 V
CC
CC
Ambient temperature -40 125
V
°C
IRS2111(S)PbF
Dynamic Electrical Characteristics
V
(VCC, VBS) = 15 V, CL = 1000 pF and T
BIAS
are measured using the test circuit shown in Fig. 3.
Symbol Definition Min. Typ. Max. Units Test Conditions
t
on
t
off
t
t
DT
MT Delay matching, HS & LS turn-on/off — 30 —
Turn-on propagation delay 550 750 950 VS = 0 V
Turn-off propagation delay — 150 180 VS = 600 V
Turn-on rise time — 75 130
r
Turn-off fall time — 35 65
f
Deadtime, LS turn-off to HS turn-on &
HS turn-off to LS turn-on
Static Electrical Characteristics
V
(VCC, VBS) = 15 V and T
BIAS
COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol Definition Min. Typ. Max. Units Test Conditions
V
V
V
OH
V
OL
I
LK
I
QBS
I
QCC
I
IN+
I
IN-
V
BSUV+
V
BSUV-
V
CCUV+
V
CCUV-
I
O+
I
O-
Logic “1” input voltage for HO & logic “0” for LO 9.5 — — VCC = 15 V
IH
Logic “0” input voltage for HO & logic “1” for LO — — 6.0 VCC = 15 V
IL
High level output voltage, V
Low level output voltage, V
Offset supply leakage current — — 50 VB = VS = 600 V
Quiescent VBS supply current — 50 100
Quiescent VCC supply current — 70 180
Logic “1” input bias current — 30 50 VIN = V
Logic “0” input bias current — — 1.0 VIN = 0 V
VBS supply undervoltage positive going threshold 7.6 8.6 9.6
VBS supply undervoltage negative going threshold 7.2 8.2 9.2
VCC supply undervoltage positive going threshold 7.6 8.6 9.6
VCC supply undervoltage negative going threshold 7.2 8.2 9.2
Output high short circuit pulsed current 200 290 —
Output low short circuit pulsed current420600—
= 25 °C unless otherwise specified. The V
A
= 25 °C unless otherwise specified. The dynamic electrical characteristics
A
ns
480 650 820
, V
and IIN parameters are referenced to
IN
TH,
6.4 — — VCC = 10 V
12.6 — — VCC = 20 V
— — 3.8 VCC = 10 V
V
— — 8.3 VCC = 20 V
BIAS
O
- V
O
— 0.05 0.2
— 0.02 0.1
mV
µA
V
IN
IO = 2 mA
= 0 V or V
V
VO = 0 V, V
mA
PW ≤ 10 µs
VO = 15 V, V
PW ≤ 10 µs
IN
CC
IN
CC
= V
= 0 V
CC
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Functional Block Diagram
DEAD
TIME
HV
LEVEL
SHIFT
UV
DETECT
PULSE
FILTER
IRS2111(S)PbF
V
B
R
Q
R
S
HO
PULSE
GEN
IN
DETECT
DEAD
TIME
UV
Lead Definitions
Symbol Description
IN Logic input for high side and low side gate driver outputs (HO & LO), in phase with HO
V
B
HO High side gate drive output
V
S
V
CC
LO Low side gate drive output
COM Low side return
High side floating supply
High side floating supply return
Low side and logic fixed supply
Lead Assignments
V
S
V
CC
LO
COM
8 Lead DIP 8 Lead SOIC
IRS2111 IRS2111S
Part Number
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IRS2111(S)PbF
Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit
Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition
Figure 5. Deadtime Waveform Definitions Figure 6. Delay Matching Waveform Definitions
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