International Rrectifier IR2121 User Manual

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CURRENT LIMITING LOW SIDE DRIVER

Data Sheet No. PD-6.018D

IR2121

Features

n Gate drive supply range from 12 to 18V
n Undervoltage lockout
n Current detection and limiting loop to limit driven

power transistor current

n Error lead indicates fault conditions and programs

shutdown time

n Output in phase with input

Description

The IR2121 is a high speed power MOSFET and

IGBT driver with over-current limiting protection cir­cuitry . Latch imm une CMOS technology enables rug­gedized monolithic construction. Logic inputs are
compatible with standard CMOS or LSTTL outputs.
The output driver features a high pulse current b uffer
stage designed for minimum cross-conduction. The
protection circuitry detects over-current in the driven
power transistor and limits the gate drive voltage.
Cycle-by-cycle shutdown is programmed by an ex­ternal capacitor which directly controls the time in­terval between detection of the over-current limiting
condition and latched shutdown. The output can be
used to drive an N-channel power MOSFET or IGBT
in the low side configuration.

Product Summary

V

OFFSET

IO+/- 1A / 2A

V

OUT

V

CSth

t

(typ.) 150 & 150 ns

on/off

Package

5V max.

12 - 18V

230 mV

Typical Connection

V

CC

IN

V

CC

IN
ERR
COM

V

CC

OUT

CS

V

TO

LOAD

S

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-91

IR2121

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param­eters are absolute voltages referenced to COM. The Ther mal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.

Parameter Value

Symbol Definition Min. Max. Units

V

R

V

V
V

V

ERR

V

P

T
T
T

CC

S
O

IN

CS

D

θJA

J
S
L

Fixed Supply Voltage -0.3 25
Gate Drive Return Voltage VCC - 25 VCC + 0.3
Output Voltage VS - 0.3 V
Logic Input Voltage -0.3 V
Error Signal Voltage -0.3 V
Current Sense Voltage VS - 0.3 V

CC
CC
CC
CC

+ 0.3
+ 0.3
+ 0.3
+ 0.3

V

Package Power Dissipation @ TA ≤ +25°C — 1.0 W
Thermal Resistance, Junction to Ambient — 125 °C/W
Junction Temperature — 150
Storage Temperature -55 150 °C
Lead Temperature (Soldering, 10 seconds) — 300

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The V

Symbol Definition Min. Max. Units

V

CC

V

S

V

O

V

IN

V

ERR

V

CS

T

A

B-92 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

Fixed Supply Voltage VS + 10 VS + 20
Gate Drive Return Voltage -5 5
Output Voltage V
Logic Input Voltage 0 V
Error Signal Voltage 0 V
Current Sense Signal Voltage V
Ambient Temperature -40 125 °C

offset rating is tested with all supplies biased at 15V differential.

S

Parameter Value

S

S

V

CC
CC
CC

V

CC

V

IR2121

Dynamic Electrical Characteristics

V

(VCC) = 15V, CL = 3300 pF and TA = 25°C unless otherwise specified. The dynamic electrical characteristics are

BIAS

defined in Figures 2 through 5.

Parameter Value

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

t

on

t

off

t

sd

t
t

t

cs

t

err

Static Electrical Characteristics

V

(VCC) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM.

BIAS

The V

O

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

V
V

V

CSTH+

V

CSTH-

V

OH

V

OL

I

QCC

I

IN+

I

IN-

I

CS+

I

CS-

V

CCUV+

V

CCUV-

I

ERR

I

ERR+

I

ERR-

I

O+

I

O-

Turn-On Propagation Delay 7 — 150 200
Turn-Off Propagation Delay 8 — 150 190

ns

ERR Shutdown Propagation Delay 9 — 1.7 2.2 µs
Turn-On Rise Time 10 — 4 3 60

r

Turn-Off Fall Time 11 — 26 35

f

CS Shutdown Propagation Delay 1 2 — 0.7 1.2
CS to ERR Pull-Up Propagation Delay 13 — 9.0 12 C

ns

µs

and IO parameters are referenced to VS .

Parameter Value

Logic “1” Input Voltage 14 2.2 — — VCC = 12V to 18V

IH

Logic “0” Input Voltage 15 — — 0.8 VCC = 12V to 18V

IL

CS Input Positive Going Threshold 16 150 230 320 VCC = 12V to 18V
CS Input Negative Going Threshold 17 130 200 260 VCC = 12V to 18V
High Level Output Voltage, V
Low Level Output V oltage, V

BIAS

O

- V

O

18 — — 100 IO = 0A

19 — — 100 IO = 0A
Quiescent VCC Supply Current 20 — 1.1 2.2 mA
Logic “1” Input Bias Current 21 — 4.5 10
Logic “0” Input Bias Current 22 — — 1.0
“High” CS Bias Current 23 — 4.5 10
“Low” CS Bias Current 24 — — 1.0
VCC Supply Undervoltage Positive Going 25 8.3 8.9 9.6
Threshold
VCC Supply Undervoltage Negative Going 26 7.3 8.0 8.7
Threshold
ERR Timing Charge Current 27 65 100 130

ERR Pull-Up Current 28 8.0 15 —

ERR Pull-Down Current 29 16 30 —
Output High Short Circuit Pulsed Current 3 0 1.0 1.6 —

Output Low Short Circuit Pulsed Current 31 2.0 3.3 —

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-93

V

mV

V

µA

V

µA

mA

A

ERR

V

=

IN

V
V

V

= 3V or 5V

CS

V

V

= 5V,

IN

ERR < V

V

= 5V,

IN

ERR > V

V

V

= 0V,

O

PW ≤ 10 µs

V

= 15V ,

O

PW ≤ 10 µs

= 270 pF

= 0V or 5V

CS

= 5V

IN

= 0V

IN

= 0V

CS

V

CS

ERR+

V

CS

ERR+

= 0V

IN

V

= 5V

IN

V

IN

= 3V

= 3V

= 0V

IR2121

Functional Block Diagram

V

CC

UV

ERR

COM

DETECT

IN

1.8V

ERROR
TIMING

1.8V

PRE

DRIVER

500 ns
BLANK

BUFFER

0.23V

-

+

AMPLIFER

COMPARATOR

Lead Definitions

Lead

Symbol Description

V

CC

IN Logic input for gate driver output (OUT), in phase with OUT
ERR Serves multiple functions; status reporting, linear mode timing and cycle by cycle logic

COM Logic ground
OUT

V

S

CS

Logic and gate drive supply

shutdown

Gate drive output
Gate drive supply return

Current sense input to current sense comparator

V

CC

OUT

V

S

CS

Lead Assignments

8 Lead DIP

IR2121

Part Number

B-94 CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL

Device Information

Process & Design Rule HVDCMOS 4.0 µm
Transistor Count 410
Die Size 104 X 111 X 26 (mil)
Die Outline

Thickness of Gate Oxide 800Å
Connections Material Poly Silicon

First Width 4 µm
Layer Spacing 6 µm

Thickness 5000Å

Material Al - Si (Si: 1.0% ±0.1%)
Second Width 6 µm
Layer Spacing 9 µm

Thickness 20,000Å

Contact Hole Dimension 8 µm X 8 µm
Insulation Layer Material PSG (SiO2)

Thickness 1.5 µm

Passivation Material PSG (SiO2)
(1) Thickness 1.5 µm
Passivation Material Proprietary*
(2) Thickness Proprietary*
Method of Saw Full Cut
Method of Die Bond Ablebond 84 - 1
Wire Bond Method Thermo Sonic

Material Au (1.0 mil / 1.3 mil)

Leadframe Material Cu

Die Area Ag

Lead Plating Pb : Sn (37 : 63)

Pa ckage Types 8 Lead PDIP

Materials EME6300 / MP150 / MP190

Remarks: * Patent Pending

IR2121

CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-95