International Rrectifier IR2112S User Manual

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Data Sheet No. PD60026-O

(

IR2112

S

HIGH AND LOW SIDE DRIVER

)

Features

Product Summary

• Floating channel designed for bootstrap operation

• Fully operational to +600V

V

OFFSET

600V max.

• Tolerant to negative transient voltage

I

+/- 200 mA / 420 mA

dV/dt immune

O

• Gate drive supply range from 10 to 20V

• Undervoltage lockout for both channels

V

OUT

10 - 20V

• 3.3V logic compatible

Separate logic supply range from 3.3V to 20V Logic and power ground ±5V offset

• CMOS Schmitt-triggered inputs with pull-down

t

(typ.) 125 & 105 ns

on/off

Delay Matching 30 ns

• Cycle by cycle edge-triggered shutdown logic

• Matched propagation delay for both channels

• Outputs in phase with inputs

Packages

Description

The IR2112(S) is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL outputs, down to 3.3V logic. The output drivers feature a high pulse

current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.

14-Lead PDIP

16-Lead SOIC

(wide body)

Typical Connection

HO

V

DD

HIN SD LIN V

SS

V

CC

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

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V HIN SD LIN V

DD

SS

V

COM

LO

V

B

V

S

CC

up to 600V

TO

LOAD

IR2112(S)

Absolute Maximum Ratings

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

DD

V

SS

V

IN

dVs/dt Allowable Offset Supply Voltage Transient (Figure 2) — 50 V/ns

P

D

R

THJA

T

J

T

S

T

L

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset ratings are tested with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figures 36 and 37.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

DD

V

SS

V

IN

T

A

High Side Floating Supply Voltage -0.3 625 High Side Floating Supply Offset Voltage VB - 25 VB + 0.3 High Side Floating Output Voltage VS - 0.3 V Low Side Fixed Supply Voltage -0.3 25 Low Side Output Voltage -0.3 VCC + 0.3 Logic Supply Voltage -0.3 VSS + 25 Logic Supply Offset Voltage VCC - 25 V Logic Input Voltage (HIN, LIN & SD) VSS - 0.3 V

Package Power Dissipation @ TA ≤ +25°C (14 Lead DIP) — 1.6

(16 Lead SOIC) — 1.25

Thermal Resistance, Junction to Ambient (14 Lead DIP) — 75

(16 Lead SOIC) — 100 Junction Temperature — 150 Storage Temperature -55 150 Lead Temperature (Soldering, 10 seconds) — 300

High Side Floating Supply Absolute Voltage VS + 10 VS + 20 High Side Floating Supply Offset Voltage Note 1 600 High Side Floating Output Voltage V Low Side Fixed Supply Voltage 10 20 Low Side Output Voltage 0 VCC Logic Supply Voltage VSS + 3 VSS + 20 Logic Supply Offset Voltage -5 (Note 2) 5 Logic Input Voltage (HIN, LIN & SD) V Ambient Temperature -40 125 °C

S

SS

B

CC DD

+ 0.3

V

+ 0.3 + 0.3

B

DD

W

°C/W

°C

V

Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details). Note 2: When V

DD < 5V, the minimum VSS offset is limited to -VDD.

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IR2112(S)

Dynamic Electrical Characteristics

V

(VCC, VBS, VDD) = 15V, CL = 1000 pF, T

BIAS

electrical characteristics are measured using the test circuit shown in Figure 3.

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

t t t

MT Delay Matching, HS & LS Turn-On/Off — — — 30 Figure 5

Turn-On Propagation Delay 7 — 125 180 VS = 0V

on

Turn-Off Propagation Delay 8 — 105 160 VS = 600V

off

Shutdown Propagation Delay 9 — 105 160 VS = 600V

sd

t

Turn-On Rise Time 10 — 80 130

r

t

Turn-Off Fall Time 11 — 40 65

f

Static Electrical Characteristics

V

(VCC, VBS, VDD) = 15V, T

BIAS

are referenced to V referenced to COM and are applicable to the respective output leads: HO or LO.

and are applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are

SS

Symbol Definition Figure Min. Typ. Max. Units Test Conditions

V

V V

I

QBS

I

QCC

I

QDD

I

V

BSUV+

V

BSUV-

V

CCUV+

V

CCUV-

I

V

OH

I

LK

IN+

I

IN-

O+

I

O-

OL

Logic “1” Input Voltage 12 9.5 — —

IH

Logic “0” Input Voltage 13 — — 6.0

IL

High Level Output Voltage, V Low Level Output Voltage, V Offset Supply Leakage Current 16 — — 50 VB = VS = 600V Quiescent VBS Supply Current 17 — 25 60 V Quiescent VCC Supply Current 18 — 80 180 VIN = 0V or V Quiescent VDD Supply Current 19 — 2.0 5.0 VIN = 0V or V Logic “1” Input Bias Current 20 — 20 40 VIN = V Logic “0” Input Bias Current 21 — — 1.0 V

VBS Supply Undervoltage Positive Going 22 7.4 8.5 9.6 Threshold VBS Supply Undervoltage Negative Going 23 7.0 8.1 9.2 Threshold VCC Supply Undervoltage Positive Going 24 7.6 8.6 9.6 Threshold VCC Supply Undervoltage Negative Going 25 7.2 8.2 9.2 Threshold Output High Short Circuit Pulsed Current 26 200 250 — VO = 0V, V

Output Low Short Circuit Pulsed Current 27 420 500 — VO = 15V, V

= 25°C and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters

A

BIAS O

= 25°C and VSS = COM unless otherwise specified. The dynamic

A

ns

V

- V

O

14 — — 100 IO = 0A 15 — — 100 IO = 0A

mV

µA

V

mA

= 0V or V

IN

PW ≤ 10 µs

IN

= 0V

IN

DD

IN

DD DD DD

= V

= 0V

DD

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IR2112(S)

Functional Block Diagram

V

DD

HIN

SD

LIN

V

RSQ

SS

VDD/V

LEVEL

SHIFT

VDD/V

LEVEL SHIFT

CC

PULSE

GEN

CC

Lead Definitions

Symbol Description

V

DD

HIN Logic input for high side gate driver output (HO), in phase SD Logic input for shutdown LIN Logic input for low side gate driver output (LO), in phase V

SS

V

B

HO High side gate drive output V

S

V

CC

LO Low side gate drive output COM Low side return

Logic supply

Logic ground High side floating supply

High side floating supply return Low side supply

HV LEVEL SHIFT

UV

DETECT

PULSE FILTER

DETECT

UV

DELAY

R Q R

S

V

B

HO

V

S

V

LO

COM

CC

Lead Assignments

14 Lead DIP 16 Lead SOIC (Wide Body)

IR2112 IR2112S

Part Number

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IR2112(S)

10% 10%

HOLO

<50 V/ns

Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test

HIN

50%

Circuit

50%

LIN

t

on

t

r

90% 90%

t

off

t

f

HO LO

Figure 3. Switching Time Test Circuit Figure 4. Switching Time Waveform Definition

SD

HO LO

50%

t

sd

HIN

LIN

90%

50% 50%

LO

10%

MT

HO

MT

90%

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Figure 6. Delay Matching Waveform DefinitionsFigure 5. Shutdown Waveform Definitions