International Rrectifier IR2111S User Manual

查询IR2111PBF供应商

Data Sheet No. PD60028-M

IR2111(S) & (PbF

HALF-BRIDGE DRIVER

Features

• Floating channel designed for bootstrap operation

Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune

• Gate drive supply range from 10 to 20V

• Undervoltage lockout for both channels

• CMOS Schmitt-triggered inputs with pull-down

• Matched propagation delay for both channels

• Internally set deadtime

• High side output in phase with input

• Also available LEAD-FREE

Description

The IR2111(S) is a high voltage, high speed power
MOSFET and IGBT driver with dependent high and
low side referenced output channels designed for half­bridge applications. Proprietary HVIC and latch
immune CMOS technologies enable ruggedized
monolithic construction. Logic input is compatible with
standard CMOS outputs. The output drivers feature a
high pulse current buffer stage designed for minimum
driver cross-conduction. Internal deadtime is provided
to avoid shoot-through in the output half-bridge. The
floating channel can be used to drive an N-channel
power MOSFET or IGBT in the high side configuration which operates up to 600 volts.

Product Summary

V

OFFSET

+/- 200 mA / 420 mA

I

O

V

OUT

t

(typ.) 750 & 150 ns

on/off

Deadtime (typ.) 650 ns

Packages

8-Lead PDIP 8-Lead SOIC

)

600V max.

10 - 20V

Typical Connection

up to 600V

V

CC

V

CC

IN

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections
only. Please refer to our Application Notes and DesignT ips for proper circuit board layout.

www.irf.com 1

IN
COM
LO

V

HO

V

B

S

TO

LOAD

IR2111(S

) & ( PbF)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param­eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in figures 7 through 10.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

IN

dVs/dt Allowable offset supply voltage transient (figure 2) — 50 V/ns

P

D

Rth

JA

T

J

T

S

T

L

High side floating supply voltage -0.3 625
High side floating supply offset voltage VB - 25 VB + 0.3
High side floating output voltage VS - 0.3 V
Low side and logic fixed supply voltage -0.3 25
Low side output voltage -0.3 VCC + 0.3
Logic input voltage -0.3 V

Package power dissipation @ TA ≤ +25°C (8 Lead PDIP) — 1.0

(8 lead SOIC) — 0.625

Thermal resistance, junction to ambient (8 lead PDIP) — 125

(8 lead SOIC) — 200
Junction temperature — 150
Storage temperature -55 150
Lead temperature (soldering, 10 seconds) — 300

CC

B

+ 0.3

+ 0.3

V

W

°C/W

°C

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

IN

T

A

Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).

2 www.irf.com

High side floating supply absolute voltage VS + 10 VS + 20
High side floating supply offset voltage Note 1 600
High side floating output voltage V
Low side and logic fixed supply voltage 10 20
Low side output voltage 0 V
Logic input voltage 0 V
Ambient temperature -40 125

S

V

B

CC
CC

V

°C

IR2111(S

) & ( PbF)

Dynamic Electrical Characteristics

V

(VCC, VBS) = 15V, CL = 1000 pF and TA = 25°C unless otherwise specified. The dynamic electrical characteristics

BIAS

are measured using the test circuit shown in figure 3.

Symbol Definition Min. T yp. Max. Units T est Conditions

t

on

t

off
t

t

DT Deadtime, LS turn-off to HS turn-on & 480 650 820

MT Delay matching, HS & LS turn-on/off — 30 —

Turn-on propagation delay 550 750 950 VS = 0V
Turn-off propagation delay — 150 180 VS = 600V
Turn-on rise time — 80 130

r

Turn-off fall time — 40 65

f

HS turn-off to LS turn-on

ns

Static Electrical Characteristics

V

(VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to

BIAS

COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.

Symbol Definition Min. T yp. Max. Units Test Conditions

V

V

V

V

I

I

QBS

I

QCC

I

IN+

I

IN-

V

BSUV+

V

BSUV-

V

CCUV+

V

CCUV-

I

O+

I

OH

OL

LK

O-

Logic “1” input voltage for HO & logic “0” for LO 6.4 — — VCC = 10V

IH

9.5 — — VCC = 15V

12.6 — — VCC = 20V

Logic “0” input voltage for HO & logic “1” for LO — — 3.8 VCC = 10V

IL

— — 6.0 VCC = 15V

— — 8.3 VCC = 20V
High level output voltage, V
Low level output voltage, V
Offset supply leakage current — — 50 VB = VS = 600V
Quiescent VBS supply current — 50 100 V
Quiescent VCC supply current — 70 180 VIN = 0V or V
Logic “1” input bias current — 30 50 VIN = V
Logic “0” input bias current — — 1.0 VIN = 0V
VBS supply undervoltage positive going threshold 7.6 8.6 9.6
VBS supply undervoltage negative going threshold 7.2 8.2 9.2
VCC supply undervoltage positive going threshold 7.6 8.6 9.6
VCC supply undervoltage negative going threshold 7.2 8.2 9.2
Output high short circuit pulsed current 200 250 — VO = 0V , V

Output low short circuit pulsed current 420 500 — VO = 15V, V

BIAS

O

- V

O

— — 100 IO = 0A

— — 100 IO = 0A

V

mV

µA

V

mA

= 0V or V

IN

IN

PW ≤ 10 µs

PW ≤ 10 µs

CC

IN

CC
CC

= V

= 0V

CC

www.irf.com 3

IR2111(S

) & ( PbF)

Functional Block Diagram

DEAD

TIME

HV
LEVEL
SHIFT

UV

DETECT

PULSE
FILTER

V

B

R

Q

R
S

HO

PULSE

GEN

IN

DETECT

DEAD

TIME

UV

Lead Definitions

Symbol Description

IN Logic input for high side and low side gate driver outputs (HO & LO), in phase with HO
V

B

HO High side gate drive output
V

S

V

CC

LO Low side gate drive output
COM Low side return

High side floating supply

High side floating supply return
Low side and logic fixed supply

Lead Assignments

V

S

V

CC

LO

COM

8 Lead DIP 8 Lead SOIC

IR2111 IR2111S

Part Number

4 www.irf.com

IR2111(S

IN

HO

LO

Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit

IN

(LO)

50%

t

off

90% 90%

IN

(HO)

t

on

50%

t

r

) & ( PbF)

t

f

LO
HO

Figure 3. Switching Time T est Circuit Figure 4. Switching Time Waveform Definition

IN

50% 50%

(LO)

IN

IN

(HO)

90%

HO

LO

Figure 5. Deadtime Waveform Definitions Figure 6. Delay Matching Waveform Definitions

www.irf.com 5

10%

DT

90%

10%

10% 10%

50%

LO

MT

50%

HO

10%

MT

90%

HOLO