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Data Sheet No. PD60028-M
IR2111(S) & (PbF
HALF-BRIDGE DRIVER
Features
• Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
• Gate drive supply range from 10 to 20V
• Undervoltage lockout for both channels
• CMOS Schmitt-triggered inputs with pull-down
• Matched propagation delay for both channels
• Internally set deadtime
• High side output in phase with input
• Also available LEAD-FREE
Description
The IR2111(S) is a high voltage, high speed power
MOSFET and IGBT driver with dependent high and
low side referenced output channels designed for halfbridge applications. Proprietary HVIC and latch
immune CMOS technologies enable ruggedized
monolithic construction. Logic input is compatible with
standard CMOS outputs. The output drivers feature a
high pulse current buffer stage designed for minimum
driver cross-conduction. Internal deadtime is provided
to avoid shoot-through in the output half-bridge. The
floating channel can be used to drive an N-channel
power MOSFET or IGBT in the high side configuration which operates up to 600 volts.
Product Summary
V
OFFSET
+/- 200 mA / 420 mA
I
O
V
OUT
t
(typ.) 750 & 150 ns
on/off
Deadtime (typ.) 650 ns
Packages
8-Lead PDIP 8-Lead SOIC
)
600V max.
10 - 20V
Typical Connection
up to 600V
V
CC
V
CC
IN
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections
only. Please refer to our Application Notes and DesignT ips for proper circuit board layout.
www.irf.com 1
IN
COM
LO
V
HO
V
B
S
TO
LOAD
IR2111(S
) & ( PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in figures 7 through 10.
Symbol Definition Min. Max. Units
V
B
V
S
V
HO
V
CC
V
LO
V
IN
dVs/dt Allowable offset supply voltage transient (figure 2) — 50 V/ns
P
D
Rth
JA
T
J
T
S
T
L
High side floating supply voltage -0.3 625
High side floating supply offset voltage VB - 25 VB + 0.3
High side floating output voltage VS - 0.3 V
Low side and logic fixed supply voltage -0.3 25
Low side output voltage -0.3 VCC + 0.3
Logic input voltage -0.3 V
Package power dissipation @ TA ≤ +25°C (8 Lead PDIP) — 1.0
(8 lead SOIC) — 0.625
Thermal resistance, junction to ambient (8 lead PDIP) — 125
(8 lead SOIC) — 200
Junction temperature — 150
Storage temperature -55 150
Lead temperature (soldering, 10 seconds) — 300
CC
B
+ 0.3
+ 0.3
V
W
°C/W
°C
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol Definition Min. Max. Units
V
B
V
S
V
HO
V
CC
V
LO
V
IN
T
A
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
2 www.irf.com
High side floating supply absolute voltage VS + 10 VS + 20
High side floating supply offset voltage Note 1 600
High side floating output voltage V
Low side and logic fixed supply voltage 10 20
Low side output voltage 0 V
Logic input voltage 0 V
Ambient temperature -40 125
S
V
B
CC
CC
V
°C
IR2111(S
) & ( PbF)
Dynamic Electrical Characteristics
V
(VCC, VBS) = 15V, CL = 1000 pF and TA = 25°C unless otherwise specified. The dynamic electrical characteristics
BIAS
are measured using the test circuit shown in figure 3.
Symbol Definition Min. T yp. Max. Units T est Conditions
t
on
t
off
t
t
DT Deadtime, LS turn-off to HS turn-on & 480 650 820
MT Delay matching, HS & LS turn-on/off — 30 —
Turn-on propagation delay 550 750 950 VS = 0V
Turn-off propagation delay — 150 180 VS = 600V
Turn-on rise time — 80 130
r
Turn-off fall time — 40 65
f
HS turn-off to LS turn-on
ns
Static Electrical Characteristics
V
(VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to
BIAS
COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol Definition Min. T yp. Max. Units Test Conditions
V
V
V
V
I
I
QBS
I
QCC
I
IN+
I
IN-
V
BSUV+
V
BSUV-
V
CCUV+
V
CCUV-
I
O+
I
OH
OL
LK
O-
Logic “1” input voltage for HO & logic “0” for LO 6.4 — — VCC = 10V
IH
9.5 — — VCC = 15V
12.6 — — VCC = 20V
Logic “0” input voltage for HO & logic “1” for LO — — 3.8 VCC = 10V
IL
— — 6.0 VCC = 15V
— — 8.3 VCC = 20V
High level output voltage, V
Low level output voltage, V
Offset supply leakage current — — 50 VB = VS = 600V
Quiescent VBS supply current — 50 100 V
Quiescent VCC supply current — 70 180 VIN = 0V or V
Logic “1” input bias current — 30 50 VIN = V
Logic “0” input bias current — — 1.0 VIN = 0V
VBS supply undervoltage positive going threshold 7.6 8.6 9.6
VBS supply undervoltage negative going threshold 7.2 8.2 9.2
VCC supply undervoltage positive going threshold 7.6 8.6 9.6
VCC supply undervoltage negative going threshold 7.2 8.2 9.2
Output high short circuit pulsed current 200 250 — VO = 0V , V
Output low short circuit pulsed current 420 500 — VO = 15V, V
BIAS
O
- V
O
— — 100 IO = 0A
— — 100 IO = 0A
V
mV
µA
V
mA
= 0V or V
IN
IN
PW ≤ 10 µs
PW ≤ 10 µs
CC
IN
CC
CC
= V
= 0V
CC
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IR2111(S
) & ( PbF)
Functional Block Diagram
DEAD
TIME
HV
LEVEL
SHIFT
UV
DETECT
PULSE
FILTER
V
B
R
Q
R
S
HO
PULSE
GEN
IN
DETECT
DEAD
TIME
UV
Lead Definitions
Symbol Description
IN Logic input for high side and low side gate driver outputs (HO & LO), in phase with HO
V
B
HO High side gate drive output
V
S
V
CC
LO Low side gate drive output
COM Low side return
High side floating supply
High side floating supply return
Low side and logic fixed supply
Lead Assignments
V
S
V
CC
LO
COM
8 Lead DIP 8 Lead SOIC
IR2111 IR2111S
Part Number
4 www.irf.com
IR2111(S
IN
HO
LO
Figure 1. Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit
IN
(LO)
50%
t
off
90% 90%
IN
(HO)
t
on
50%
t
r
) & ( PbF)
t
f
LO
HO
Figure 3. Switching Time T est Circuit Figure 4. Switching Time Waveform Definition
IN
50% 50%
(LO)
IN
IN
(HO)
90%
HO
LO
Figure 5. Deadtime Waveform Definitions Figure 6. Delay Matching Waveform Definitions
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10%
DT
90%
10%
10% 10%
50%
LO
MT
50%
HO
10%
MT
90%
HOLO
IR2111(S
400
)
)
)
)
)
)
) & ( PbF)
1500
1250
1000
750
500
250
Turn-On Delay Time (ns
0
-50 -25 0 25 50 75 100 125
o
Temperature (
C)
Figure 11A Turn-On Time vs Temperature
350
300
250
200
150
100
Turn-Off Delay Time (ns
50
0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Max
Typ
Max.
Typ.
Min.
1500
1250
Max.
1000
Typ.
750
Min.
500
250
Turn-On Delay Time (ns
0
10 12 14 16 18 20
V BIAS Supply V oltage (V)
Figure 11B Turn-On Time vs V oltage
400
350
300
250
Max
200
150
Typ
100
50
Turn-Off Delay Time (ns
0
10 12 14 16 18 20
VBIAS Sup ply Voltage (V)
Figure 12A Turn-Off T ime vs Temperature
400
350
300
250
200
150
100
Turn-On rise Time (ns
50
0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Max
Typ
Figure 13A Turn-On RiseT ime vs Temperature
Turn-On Rise Time (ns
Figure 12B Turn-Off T ime vs Voltage
400
350
300
250
200
Max
150
100
Typ
50
0
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 13B Turn-On RiseT ime vs Voltage
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IR2111(S
)
)
) & ( PbF)
200
150
100
50
Turn -Off Fall Time (ns
0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Max
Typ
Figure 14A Turn-Off Fall T ime vs Temperature
1250
1000
750
500
Deadtime (ns)
250
0
-50 -25 0 25 50 75 100 125
o
Temperature (
C)
Figure 15A Dead Time vs T emperature
Max.
Typ.
Min.
200
150
100
Max
50
Turn-Off Fall Time (ns
Typ
0
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 14B Turn-Off Fall Time vs Voltage
1250
1000
Max.
Typ.
750
Min.
500
Deadtime (ns)
250
0
10 12 14 16 18 20
VBIAS Suppl y Voltage (V)
Figure 15B Dead Time vs Voltage
15
12
9
6
3
Logic "1" Input Threshold (V)
0
-50 -25 0 25 50 75 100 125
Temperat ure (°C)
Figure 16A Logic “I” Input voltage for HO &
Logic “0” for LO vs Temperature
Min
Logic " 1 " Input Treshold (V)
03691215
10 12 14 16 18 20
Figure 16B Logic “I” Input voltage for HO &
Logic “0” for LO vs Voltage
Min
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IR2111(S
5
15
5
)
1
5
)
0
12
9
6
) & ( PbF)
Max
Max
3
Logic "0" Input Threshold (V)
0
-50 -25 0 25 50 75 100 12
Temperature (°C)
Figure 17A Logic “0” Input voltage for HO &
Logic “I” for LO vs T emperature
1
0.8
0.6
0.4
Max.
0.2
High Lev el O u tp u t V o lta g e (V )
0
-50 -25 0 25 50 75 10 0 12
Tem perature
Figure 18A. High Level Output vs. Temperature
0.8
Logic " 0 " Input Treshold (V
0 3 6 9 12 15
10 12 14 16 18 20
VCC Logic Supply Voltage (V)
Figure 17B Logic “0” Input voltage for HO &
Logic “I” for LO vs Voltage
1
0.8
0.6
0.4
M ax.
0.2
High Lev el O utput V olt age (V )
0
10 12 14 16 18 20
VBAIS S upply V otage (V )
Figure 18B. High Level Output vs. Voltage
1
0.8
0.6
0.4
0.2
Low Level Output Voltage (V
0
-50 -25 0 25 50 75 100 12
Figure 19A. Low Level Output vs. Temperature
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Max.
Temperature (°C)
0.6
0.4
0.2
Low Level Output Voltage (V)
0
10 12 14 16 18 2
Max.
VBIAS Supply Votage (V)
Figure 19B. Low Level Output vs. Voltage
IR2111(S
)
5
5
500
0
) & ( PbF)
500
400
300
200
100
0
-50 -25 0 25 50 75 100 125
Offset Supply Leakage Current (uA
Max.
Temperature (°C)
Figure 20A Offset Supply Current vs
Temperature
200
150
Max.
100
Typ
.
50
VBS Supply Current (uA)
0
-50 -25 0 25 50 75 100 12
Temperature (°C)
Figure 21A VBS Supply Current vs Temperature
500
400
300
200
100
0
0 100 200 300 400 500 600
Offset Supply Leakage Current (uA)
Max.
VB B oos t V oltage (v)
Figure 20B Offset Supply Current vs Voltage
200
150
Max.
100
Typ
.
50
VBS Supply Current (uA)
0
10 12 14 16 18 20
VBS Floating Supply Vol t age (V )
Figure 21B VBS Supply Current vs Voltage
500
400
300
200
100
Vcc Supply Current (uA)
0
-50 -25 0 25 50 75 100 12
Figure 22A VCC Supply Current vs Temperature
Max
.
Typ
.
Temperature (°C)
400
300
200
100
V cc S upply C u rre n t (u A )
0
10 12 14 16 18 2
Vc c F ixed S upply V olta g e (V )
Max
Typ
Figure 22B VCC Supply Current vs Voltage
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IR2111(S
)
5
L
i
"1
"
I
t
Bi
C
t
(
A)
0
) & ( PbF)
120
u
100
urren
80
as
60
npu
40
c
20
og
0
-50 -25 0 25 50 75 100 12
Temperature (°C)
Figure 23A Logic “1” Input Current vs Temperature
5
4
3
2
Max.
1
0
Logic "0" Input Bias Current (uA)
-50 -25 0 25 50 75 100 125
Temperature (°C
120
100
80
60
40
20
0
10 12 14 16 18 20
Logic " 1" Input Bias Current (uA)
VCC Supply Volt age (V )
Max.
Typ
.
Figure 23B Logic “1” Input Current vs V
5
4
3
2
Max
1
Logic "0" Input Current (uA)
0
10 12 14 16 18 2
.
VCC Supply Voltage (V)
CC
Voltage
Figure 24A. Logic “0” Input Current vs. Temperature
12
11
10
9
8
7
VBS UVLO Threshold +(V)
6
-50 - 25 0 25 50 75 100 125
Max
.
Typ.
Min.
Temperature (°C)
Figure 25 VBS Undervoltage Threshold (+)
vsTemperature
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Figure 24B. Logic “0” Input Current vs. V
12
11
10
9
8
7
VBS UVL O T h re s h o ld -(V )
6
-50 -25 0 25 50 75 10 0 125
Max
.
Typ.
Min
.
Tem peratur e (° C
)
Figure 26 VBS Undervoltage Threshold (-)
vsTemperature
CC
Voltage
IR2111(S
11
)
500
11
) & ( PbF)
10
9
8
Max.
Typ.
Min.
7
6
Vcc Undervoltage Lockout +(V)
-50 -25 0 25 50 75 100 125
Tem perature (°C)
Figure 27 VCC Undervoltage (-) vs Temperature
400
300
Typ.
200
Min.
100
Output source Current (mA)
0
-50-250 255075100125
Temperature (°C)
Figure 29A Output Source Current vs Temperature
10
Max.
9
Typ.
8
Min.
7
VCC Undervoltage Lockout - (V
6
-50-250255075100125
Temperature (°C)
Figure 28 VCC Undervoltage (-) vs Temperature
500
400
Typ.
300
200
Min.
100
Output source Current (mA)
0
10 12 14 16 18 20
VBIAS Supply Voltage (V)
Figure 29B Output Source Current vs Voltage
750
600
Typ.
450
300
150
Output Sink Current (mA)
0
-50 -25 0 25 50 75 100 125
Temperature (°C)
Min.
Figure 30A Output Sink Current vs Temperature
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750
600
450
300
150
Output Sink Current (mA)
0
10 12 14 16 18 20
Typ.
Min.
VBIAS Supply Voltage (V)
Figure 30B Output Sink Current vs Voltage
IR2111(S
) & ( PbF)
150
125
100
75
50
25
Junction Tem perature (°C )
0
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Figure 31. IR2111 TJ vs. Frequency (IRFBC20)
R
GATE
150
ΩΩ
= 33
Ω, VCC = 15V
ΩΩ
320V 160V
125
100
320
160
30V
30V
150
125
100
75
50
25
Junction Tem perature (°C )
0
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Figure 32. IR2111 TJ vs. Frequency (IRFBC30)
R
GATE
ΩΩ
= 22
Ω, VCC = 15V
ΩΩ
150
320V
320V 160V
125
100
160V
30V
30V
75
50
25
Junction Tem per at ur e (°C)
0
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Figure33. IR2111 TJ vs. Frequency (IRFBC40)
R
GATE
ΩΩ
= 15
Ω, VCC = 15V
ΩΩ
75
50
25
Junction Tem perature (°C )
0
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Figure 34. IR2111 TJ vs. Frequency (IRFPC50)
R
GATE
ΩΩ
= 10
Ω, VCC = 15V
ΩΩ
12 www.irf.com
IR2111(S
) & ( PbF)
320V
150
125
100
75
50
25
Junction Tem perature (°C )
0
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Figure 35. IR2111S TJ vs. Frequency (IRFBC20)
R
GATE
ΩΩ
= 33
Ω, VCC = 15V
ΩΩ
320V
140V
150
125
160
30V
30V
140V
320V
150
125
100
75
50
25
Junction Tem per a t ur e (° C)
0
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Figure 36. IR2111S TJ vs. Frequency (IRFBC30)
R
GATE
ΩΩ
= 22
Ω, VCC = 15V
ΩΩ
320V 140V 30V
150
125
30V
100
75
50
25
Junction Tem perature (°C )
0
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Figure 37. IR2111S TJ vs. Frequency (IRFBC40)
R
GATE
ΩΩ
= 15
Ω, VCC = 15V
ΩΩ
100
75
50
25
Junction Tem perature (°C )
0
1E+2 1E+3 1E+4 1E+5 1E+6
Frequency (Hz)
Figure 38. IR2111S TJ vs. Frequency (IRFPC50)
R
GATE
ΩΩ
= 10
Ω, VCC = 15V
ΩΩ
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IR2111(S
Case outlines
) & ( PbF)
A
E
D B
5
87
6
6X
0.25 [ . 010 ]
65
H
4312
0.25 [ . 010 ] A
e
8X b
e1
A1
A
CAB
NOTES:
1. DIMENSIONING & TOLERANCING PER ASME Y14.5M-1994.
2. CONT ROLLING DIM ENSION: MILLIMETER
3. D IMENSIONS ARE SHOWN IN MI LL IMETERS [INCHES].
4. OUTLINE CONFORMS TO JEDEC OUT L INE MS-012AA.
C
0.10 [ . 004 ]
8-Lead PDIP
6.46 [. 2 55]
3X 1.27 [. 05 0]
y
8-Lead SOIC
01-3003 01
DIM
FOOTPRINT
8X 0.72 [. 02 8]
8X 1.78 [. 07 0]
MIN MAX
A
.0532
A1
b
c .0075 .0098 0.19 0.25
D
E
e
e1
H
K
L
y
.0688
.0040
.0098
.013
.020
.189
.1968
.1497
.1574
.050 BASI C
.025 BASIC 0.635 BASIC
.2284
.2440
.0099
.0196
.016
.050
0°
8°
K x 4 5°
8X L
8X c
7
5 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006].
6 DIMENSION DOES NOT INCLUDE MOLD PROTRUSIONS.
MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010].
7 DIMENSION IS THE LENGTH OF LEAD FOR SOLD ERING TO
A SUBSTRATE.
01-0021 11
01-6014
(MS-001AB)
MILLIMETERSINC HES
MIN MAX
1.35
1.75
0.10
0.25
0.33
0.51
4.80
5.00
3.80
4.00
1.27 BASI C
5.80
6.20
0.25
0.50
0.40
1.27
0°
8°
01-6027
(MS-012AA)
14 www.irf.com
IR2111(S
LEADFREE PART MARKING INFORMATION
) & ( PbF)
Part number
Date code
Pin 1
Identifier
?
MARKING CODE
Lead Free Released
P
Non-Lead Free
Released
IRxxxxxx
YWW?
ORDER INFORMATION
Basic Part (Non-Lead Free)
8-Lead PDIP IR2111 order IR2111
8-Lead SOIC IR2111S order IR2111S
IR logo
?XXXX
Lot Code
(Prod mode - 4 digit SPN code)
Assembly site code
Per SCOP 200-002
Leadfree Part
8-Lead PDIP IR2111 order IR2111PbF
8-Lead SOIC IR2111S order IR2111SPbF
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 4/12/2004
www.irf.com 15
This product has been qualified per industrial level
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