International Rrectifier IR2106-4 -S User Manual

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Data Sheet No. PD60162 Rev. V

IR2106(4)

(S)

HIGH AND LOW SIDE DRIVER

Features

Floating channel designed for bootstrap operation

•

Fully operational to +600V Tolerant to negative transient voltage dV/dt immune Gate drive supply range from 10 to 20V (IR2106(4))

•

Undervoltage lockout for both channels

•

3.3V, 5V and 15V input logic compatible

•

Matched propagation delay for both channels

•

Logic and power ground +/- 5V offset.

•

Lower di/dt gate driver for better noise immunity

•

Outputs in phase with inputs (IR2106)

•

Description

The IR2106(4)(S) are high voltage, high speed power MOSFET and IGBT drivers with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL output, down to 3.3V logic. The output driv-

2106/2301//2108//2109/2302/2304

Part

2106/2301

21064

2108 Internal 540ns COM

21084

2109/2302 Internal 540ns COM

21094

2304

ers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.

Packages

8-Lead SOIC

14-Lead SOIC

Input logic

HIN/LIN no none

HIN/LIN yes

IN/SD yes

HIN/LIN

Crossconduction prevention

logic

yes

Dead-Time Ground Pins Ton/Toff

Programmable 0.54~5 µs

Internal 100ns

8-Lead PDIP

14-Lead PDIP

Feature Comparison

COM

VSS/COM

COM

220/200

750/200 160/140

Typical Connection

V

CC

V

CC

HIN

LIN

(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

HIN LIN

HO

V

LOCOM

B

S

IR2106

up to 600V

TO

LOAD

up to 600V

HO

V

CC

HIN LIN

V

SS

HIN LIN

V

CC

B

V

S

IR21064

COM

SS

LO

TO

LOAD

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IR2106(4)

(S)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

IN

V

SS

dVS/dt Allowable offset supply voltage transient — 50 V/ns

P

D

Rth

JA

T

J

T

S

T

L

High side floating absolute voltage -0.3 625 High side floating supply offset voltage VB - 25 VB + 0.3 High side floating output voltage VS - 0.3 V Low side and logic fixed supply voltage -0.3 25 Low side output voltage -0.3 VCC + 0.3 Logic input voltage VSS - 0.3 V Logic ground (IR21064 only) V

Package power dissipation @ TA ≤ +25°C (8 lead PDIP) — 1.0

(8 lead SOIC) — 0.625 (14 lead PDIP) — 1.6 (14 lead SOIC) — 1.0

Thermal resistance, junction to ambient (8 lead PDIP) — 125

(8 lead SOIC) — 200

(14 lead PDIP) — 75

(14 lead SOIC) — 120 Junction temperature — 150 Storage temperature -50 150 Lead temperature (soldering, 10 seconds) — 300

- 25 V

CC

CC CC

B

+ 0.3

+ 0.3 + 0.3

°C/W

V

W

°C

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IR2106(4)

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The V

Symbol Definition Min. Max. Units

VB High side floating supply absolute voltage IR2106(4) VS + 10 VS + 20 V

S

V

HO

V

CC

V

LO

V

IN

V

SS

T

A

Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details).

High side floating supply offset voltage Note 1 600 High side floating output voltage V Low side and logic fixed supply voltage IR2106(4) 10 20 Low side output voltage 0 V Logic input voltage VSS V Logic ground (IR21064 only) -5 5 Ambient temperature -40 125 °C

Dynamic Electrical Characteristics

V

(VCC, VBS) = 15V, VSS = COM, CL = 1000 pF, TA = 25°C.

BIAS

and VSS offset rating are tested with all supplies biased at 15V differential.

S

V

B

CC

V

(S)

Symbol Definition Min. Typ. Max. Units Test Conditions

t

on

t

off

MT Delay matching, HS & LS turn-on/off — 0 30

t t

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Turn-on propagation delay — 220 300 VS = 0V Turn-off propagation delay — 200 280 VS = 0V or 600V

nsec

Turn-on rise time — 1 5 0 220 VS = 0V

r

Turn-off fall time — 50 80 VS = 0V

f

IR2106(4)

(S)

Static Electrical Characteristics

V

(VCC, VBS) = 15V, VSS = COM and TA = 25°C unless otherwise specified. The VIL, VIH and IIN parameters are

BIAS

referenced to VSS/COM and are applicable to the respective input leads. The VO, IO and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO.

Symbol Definition Min. Typ. Max. Units Test Conditions

V

V V V

I

QBS

I

QCC

I

IN+

I

V

CCUV+

V

BSUV+

V

CCUV-

V

BSUV-

V

CCUVH

V

BSUVH

I

OH

OL

LK

IN-

O+

O-

Logic “1” input voltage (IR2106(4))

IH

Logic “0” input voltage (IR2106(4)) —

IL

High level output voltage, V Low level output voltage, V

BIAS

O

- V

O

2.9

— 0.8 1.4 IO = 20 mA

— 0.3 0.6 IO = 20 mA Offset supply leakage current — — 50 VB = VS = 600V Quiescent VBS supply current 20 75 1 30 V Quiescent VCC supply current 60 120 180 VIN = 0V or 5V Logic “1” input bias current

VIN = 5V (IR2106(4))

—

Logic “0” input bias current

VCC and V

VIN = 0V (IR2106(4))

supply undervoltage positive going 8.0 8.9 9.8

BS

—

threshold VCC and VBS supply undervoltage negative going 7.4 8.2 9.0 threshold Hysteresis 0.3 0.7 —

Output high short circuit pulsed current 120 200 — VO = 0V ,

Output low short circuit pulsed current 250 350 — VO = 15V ,

—

5

—

20

2

0.8 V

µA

V

mA

VCC = 10V to 20V

= 10V to 20V

V

CC

= 0V or 5V

IN

PW ≤ 10 µs

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Functional Block Diagrams

IR2106

HIN

LIN

VSS/COM

LEVEL SHIFT

VSS/COM

LEVEL SHIFT

PULSE

GENERATOR

DELAY

HV

LEVEL

SHIFTER

PULSE FILTER

UV

DETECT

IR2106(4)

R

RSQ

UV

(S)

VB

HO

VS

VCC

LO

COM

VB

PULSE FILTER

UV

DETECT

R

Q

R

S

HO

VS

HIN

IR21064

VSS/COM

LEVEL SHIFT

PULSE

GENERATOR

HV

LEVEL

SHIFTER

VCC

UV

LIN

VSS/COM

LEVEL SHIFT

DETECT

DELAY

LO

COM

VSS

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IR2106(4)

(S)

Lead Definitions

Symbol Description

HIN Logic input for high side gate driver output (HO), in phase LIN Logic input for low side gate driver output (LO), in phase VSS Logic Ground (IR21064 only) V

B

HO High side gate drive output V

S

V

CC

LO Low side gate drive output COM Low side return

High side floating supply

High side floating supply return Low side and logic fixed supply

Lead Assignments

1

V

CC

2

HIN

3

LIN

4

COM

V

HO

V LO

8

B

7 6

S

5

V

1

HIN

2

LIN

3

COM

4

8 Lead PDIP 8 Lead SOIC

IR2106 IR2106S

V

HO

V

14

13

B

12 11

S

10

9 8

V

1

CC

HIN

2

LIN

3 4

VSS

5

COM

6

LO

7

14 Lead PDIP 14 Lead SOIC

V

1

CC

HIN

2

LIN

3 4

VSS

5

COM

6

LO

7

IR21064 IR21064S

CC

HO

V

HO

V

V LO

8

B

7 6

S

5

14

13

B

12 11

S

10

9 8

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HIN LIN

HO LO

Figure 1. Input/Output Timing Diagram

IR2106(4)

(S)

HIN

50%

LIN

t

on

t

r

90% 90%

t

off

t

f

HO LO

Figure 2. Switching Time Waveform Definitions

10% 10%

HIN

50%

LIN

MT

LO

50%

HO

10%

MT

90%

HOLO

Figure 3. Delay Matching Waveform Definitions

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