International Rrectifier IR2103-S User Manual

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Data Sheet No. PD60045-N

IR2103

(S)

HALF-BRIDGE DRIVER

Features

• Floating channel designed for bootstrap operation

Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune

• Gate drive supply range from 10 to 20V

• Undervoltage lockout

• 3.3V, 5V and 15V logic compatible

• Cross-conduction prevention logic

• Matched propagation delay for both channels

• Internal set deadtime

• High side output in phase with HIN input

• Low side output out of phase with

LIN

input

Description

The IR2103(S) are high voltage, high speed power
MOSFET and IGBT drivers with dependent high and
low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable rug­gedized monolithic construction. The logic input is
compatible with standard CMOS or LSTTL output,
down to 3.3V logic. The output drivers feature a high

pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to
drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.

Product Summary

V

OFFSET

+/- 130 mA / 270 mA

I

O

V

OUT

t

(typ.) 680 & 150 ns

on/off

Deadtime (typ.) 520 ns

600V max.

10 - 20V

Packages

8-Lead SOIC

IR2103S

8-Lead PDIP

IR2103

Typical Connection

up to 600V

V

CC

V

CC

HIN

LIN

(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only .
Please refer to our Application Notes and DesignTips for proper circuit board layout.

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HIN
LIN

V

HO

V

LOCOM

B

S

TO

LOAD

IR2103

(S)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param­eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

IN

dVs/dt Allowable offset supply voltage transient — 50 V/ns

P

D

Rth

JA

T

J

T

S

T

L

High side floating absolute voltage -0.3 625
High side floating supply offset voltage VB - 25 VB + 0.3
High side floating output voltage VS - 0.3 V
Low side and logic fixed supply voltage -0.3 25
Low side output voltage -0.3 VCC + 0.3
Logic input voltage (HIN &

Package power dissipation @ TA ≤ +25°C (8 Lead PDIP) — 1.0

Thermal resistance, junction to ambient (8 Lead PDIP) — 125

Junction temperature — 150
Storage temperature -55 150
Lead temperature (soldering, 10 seconds) — 3 00

) -0.3 V

LIN

(8 Lead SOIC) — 0.625

(8 Lead SOIC) — 200

CC

B

+ 0.3

+ 0.3

W

°C/W

°C

V

Recommended Operating Conditions

The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

LO

V

IN

T

A

Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).

2 www.irf.com

High side floating supply absolute voltage VS + 10 VS + 20
High side floating supply offset voltage Note 1 600
High side floating output voltage V
Low side and logic fixed supply voltage 10 20
Low side output voltage 0 V
Logic input voltage (HIN &

Ambient temperature -40 125

)0V

LIN

S

V

B

CC

CC

V

°C

IR2103

(S)

Dynamic Electrical Characteristics

V

(VCC, VBS) = 15V, CL = 1000 pF and TA = 25°C unless otherwise specified.

BIAS

Symbol Definition Min. Typ. Max. Units T est Conditions

t

on

t

off

t
t

DT Deadtime, LS turn-off to HS turn-on & 400 520 650

MT Delay matching, HS & LS turn-on/off ——60

Tu rn-on propagation delay — 680 820 VS = 0V
Tu r n-off propagation delay — 150 220 VS = 600V
Tu r n-on rise time — 100 170

r

Tu r n-off fall time — 50 90

f

HS turn-on to LS turn-off

ns

Static Electrical Characteristics

V

(VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to

BIAS

COM. The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.

Symbol Definition Min. Typ. Max. Units T est Conditions

V

V

V

OH

V

I

LK

I

QBS

I

QCC

I

IN+

I

IN-

V

CCUV+

V

CCUV-

I

O+

I

O-

IH

OL

Logic “1” (HIN) & Logic “0” (
Logic “0” (HIN) & Logic “1” (

IL

High level output voltage, V
Low level output voltage, V
Offset supply leakage current ——50 VB = VS = 600V
Quiescent VBS supply current — 30 55 V
Quiescent VCC supply current — 150 270 VIN = 0V or 5V
Logic “1” input bias current — 3 10 HIN = 5V,
Logic “0” input bias current ——1 HIN = 0V,
VCC supply undervoltage positive going 8 8.9 9.8

threshold
VCC supply undervoltage negative going 7.4 8.2 9
threshold
Output high short circuit pulsed current 130 210 — VO = 0V , V

Output low short circuit pulsed current 270 360 — VO = 15V, V

LIN

) input voltage 3 —— VCC = 10V to 20V

LIN

) input voltage ——0.8 VCC = 10V to 20V

BIAS

O

- V

O

——100 IO = 0A
——100 IO = 0A

mV

µA

mA

V

= 0V or 5V

IN

V

PW ≤ 10 µs

PW ≤ 10 µs

LIN

LIN

IN

IN

= 0V
= 5V

= V

= V

IH

IL

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IR2103

(S)

Functional Block Diagram

V

B

HV

LEVEL

SHIFT

HIN

LIN

Vcc

DEAD

TIME

DETECT

DEAD

TIME

UV

PULSE

GEN

Lead Definitions

Symbol Description

HIN Logic input for high side gate driver output (HO), in phase

LIN

V

B

HO High side gate drive output
V

S

V

CC

LO Low side gate drive output
COM Low side return

Logic input for low side gate driver output (LO), out of phase
High side floating supply

High side floating supply return
Low side and logic fixed supply

PULSE

FILTER

Q
R
S

HO

V

V

LO

COM

S

CC

Lead Assignments

V

1

CC

HIN

2

LIN

3

COM

4

V

HO

V
LO

8

B

7
6

S

5

V

1

CC

HIN

2

LIN

3

COM

4

8 Lead PDIP 8 Lead SOIC

IR2103 IR2103S

4 www.irf.com

V

HO

V
LO

8

B

7
6

S

5