International Rrectifier IR20153S User Manual

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Preliminary Data Sheet PD60214 Rev B

IR20153S & (PbF)

HIGH SIDE DRIVER WITH RECHARGE

Features

Product Summary

• Floating channel designed for bootstrap operation

Fully operational up to 150V Tolerant to negative transient voltage, dV/dt immune

• Gate drive supply range from 5V to 20V

• Undervoltage lockout

V

OFFSET

IO+/- 400mA @ VBS=7V,

• Internal recharge FET for bootstrap refresh

• Internal deadtime of 11µs and 0.8µs

• CMOS Schmitt-triggered input logic

• Output out of phase with input

• Reset input

• Split pull-up and pull-down gate drive pins

V

OUT

t

on/off

• Also available LEAD-FREE (PbF)

Description

The IR20153S is a high voltage, high speed power MOSFET driver . Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS output down to 3.3V. The output driver features a high pulse current buffer stage designed for minimum cross-conduction. The floating channel can be used to drive an N-channel power MOSFET in the high or low side configuration which operates up to 150 volts.

Typical Connection

150V max.

1.5A @ VBS=16V

5-20V

1.0 and 0.3 µs

Package

8-Lead SOIC

up to 150V

VCC

IN

RESET

(Refer to Lead Assignments for correct configuration). This/These diagram(s) show electrical connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.

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VCC

IN

GND

RESET

VB

HOH

HOL

VS

Load

IR20153S & (PbF)

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to GND, all currents are defined positive into any lead. This is a stress only rating and operation of the device at these or any conditions exceeding those indicated in the operational sections of this specifications is not implied.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

IN

dV/dt Allowable offset voltage slew rate — 50 V/nsec

T

J

T

S

T

L

High side driver output stage voltage -5.0 170

High side floating supply offset voltage - 8.0 150

Output voltage gate high connection VS - 0.3 V

Low side fixed supply voltage -0.3 25

Input voltage (IN and RESET) -0.3 V

Junction temperature -55 150

Storage temperature -55 150

Lead temperature (soldering, 10 seconds) — 300

B

+ 0.3

CC

°C

V

+0.3

Recommended Operating Conditions

The input/output logic timing diagram is shown in Fig. 2. For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to GND. The VS offset rating is tested with all suppliers biased at Vcc=5V and VBS=7V.

Symbol Definition Min. Max. Units

V

B

V

S

V

HO

V

CC

V

IN

T

A

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High side driver output stage voltage VS + 5 VS + 20

High side floating supply offset voltage -1.6 150

Output voltage gate high connection V

Supply voltage 5 20

Input voltage (IN and RESET) 0 Vcc

Ambient temperature -55 150 °C

S

V

B

V

IR20153S & (PbF)

Electrical Characteristics

Unless otherwise specified,

Unless otherwise noted, these specifications apply for an operating ambient temperature of TA =25°C.

Symbol Definition Min. Typ. Max. Units Test Conditions

VCC Supply Characteristics

V

CCUV+

V

CCUV-

V

CCUVHYSVCC

I

QCC

VBS Supply Characteristics

V

BSUV

V

BSUV

V

BSUVHYSVBS

I

QBS1

I

QBS2

VB. VS Supply Characteristics

I

LK

Gate Driver Characteristics

I

o+1

I

o+2

t

r1

t

r2

I

o-1

I

o-2

t

f1

t

f2

t

on

t

off

t

res,off

VCC supply undervoltage positive going threshold

VCC supply undervoltage negative going threshold 2.5 — — VCC dropping

VCC supply current

+VBS supply undervoltage positive going threshold

-VBS supply undervoltage negative going threshold 2.5

VBS supply current

Offset supply leakage current

Peak output source current 250 400

Peak output source current 800 1500

Output rise time

Peak output sink current 250 400

Peak output sink current 800 1500

Output fall time

Input-to-Output Turn-on propogation delay

(50% input level to 10% output level)

Input-to-Output Turn-off propogation delay

(50% input level to 90% output level)

RES-to-Output Turn-off propogation delay

(50% input level to 90% [t

VCC = 5V, VBS = 7V, VS = 0V, IN = 0V, RES = 5V, load R = 50Ω, C = 6.8nF (see Figure 3).

——

supply undervoltage lockout hysteresis 0.01 0.3 0.60

——

supply undervoltage lockout hysteresis 0.01 0.3 0.60

——

—

] output levels)

phl

4.3

400 uA VCC = 3.6V & 6.5V

4.3 V VBS rising from 0V

——

100

200

50

—

0.2 0.4µsec

0.1 0.2µsec VBS = 16V

—

0.2 0.4µsec IN = 5V

0.1 0.2µsec VBS = 16V, IN = 5V

1.0 2.0µsec

0.3 0.9µsec

V

µ

A static mode, VBS =

µ

A static mode, VBS =

16V, IN = 0V or 5V

µ

AVB = VS = 150V

mA

mA VBS = 16V

mA IN = 5V

mA VBS = 16V, IN = 5V

rising from 0V

CC

from 5V

VBS dropping

from 5V

7V, IN = 0V or 5V

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IR20153S & (PbF)

Electrical Characteristics

Unless otherwise specified,

Unless otherwise noted, these specifications apply for an operating ambient temperature of T

VCC = 5V, VBS = 7V, VS = 0V, IN = 0V, RES = 5V, load R = 50

Symbol Definition Min. Typ. Max. Units Test Conditions

Gate Driver Characteristics cont.

Supply Characteristics

V

CC

t

res,on

RES-to-Output Turn-On Propogation Delay - 1.0 2.0

(50% input level to 10% [t

] output levels)

plh

Input Characteristics

V

INH

V

INL

R

IN

V

H_RES

V

L_RES

R

RES

Recharge Characteristics

t

on_rech

t

off_rech

V

RECH

High Logic Level Input Threshold 3 - - V

Low Logic Level Input Threshold - - 1.4 V

High Logic Level Input Resistance 40 100 220 k

High Logic Level RES Input Threshold 3 - - V

Low Logic Level RES Input Threshold - - 1.4 V

High Logic Level RES Input Resistance 40 100 220 k

(see Figure 3a)

Recharge Transistor Turn-On Propogation Delay 7 11 15

Recharge Transistor Turn-Off Propogation Delay - 0.3 0.9

Recharge Output Transistor On-State Voltage Drop - - 1.2 V IS = 1mA, IN = 5V

Deadtime Characteristics

DT

HOFF

HON

High Side Turn-Off to Recharge gate Turn-On 7 11 15

Recharge gate Turn-Off to High Side Turn-On0. 0.4 0.8 1.5

Ω

, C = 6.8nF (see Figure 3).

=25°C.

A

µ

sec

Ω

µ

sec VS = 5V

µ

sec

µ

sec

µ

sec

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IR20153S & (PbF)

A True table for

,

V

cc

, RESET, IN,

V

BS

LOW IN.

V

cc VBS

<V

ccUVLO-

<V

ccUVLO-

<V

ccUVLO-

<V

ccUVLO-

<V

ccUVLO-

<V

ccUVLO-

<V

ccUVLO-

<V

ccUVLO-

>V

ccUVLO+

>V

ccUVLO+

>V

ccUVLO+

<VBSUVLO-

>VBSUVLO+

<VBSUVLO-

and RechFET is shown as follows.

H

O

RESET- IN-

HIGH HIGH OFF ON

HIGH LOW OFF ON

LOW HIGH OFF ON

LOW LOW OFF ON

HIGH HIGH OFF ON

HIGH LOW OFF ON

LOW HIGH OFF ON

LOW LOW OFF ON

HIGH HIGH OFF ON

HIGH LOW OFF OFF

LOW HIGH OFF ON

This truth table is for ACTIVE

H

O

RechFET

>V

ccUVLO+

>V

ccUVLO+

>V

ccUVLO+

>V

ccUVLO+

>V

ccUVLO+

RESET = HIGH indicates that high side MOSFET is allowed to be turned on.

<VBSUVLO-

>VBSUVLO+

>VBSUVLO+ LOW HIGH OFF ON1

>VBSUVLO+

LOW LOW OFF ON

HIGH HIGH OFF ON

HIGH LOW ON OFF

LOW LOW OFF ON

1

RESET = LOW indicates that high side MOSFET is OFF. IN = LOW indicates that high side MOSFET is on. IN = HIGH indicates that high side MOSFET is off. RechFET = ON indicates that the recharge MOSFET is on. RechFET = OFF indicates that the recharge MOSFET is off.

1

Note: Refer to the RESET functionality graph of Figure 7, for VCC and VBS voltage ranges under which

the functionality is normal.

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