International Rectifier SupIRBuck IR3898 User Manual

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IRDC3898-P3V3
SupIRBuck
TM
DESCRIPTION
The IR3898 is a synchronous buck converter, providing a compact, high performance and flexible solution in a small 4mm X 5 mm Power QFN package.
Key features offered by the IR3898 include internal Digital Soft Start/Soft Stop, precision
0.5Vreference voltage, Power Good, thermal protection, programmable switching frequency, Enable input, input under-voltage lockout for proper start-up, enhanced line/ load regulation with feed forward, external frequency synchronization with smooth clocking, internal LDO and pre-bias start-
up.
3.3Vout
Pulse by pulse current limit and output over-
current protection function is implemented by sensing the voltage developed across the on­resistance of the synchronous rectifier MOSFET for optimum cost and performance and the current limit is thermally compensated.
This user guide contains the schematic and bill of materials for the IR3898 evaluation board. The guide describes operation and use of the evaluation board itself. Detailed application information for IR3898 is available in the IR3898 data sheet.
BOARD FEATURES
V
= +12V (+ 13.2V Max)
in
V
= +3.3V @ 0-6A
out
F
= 1MHz
s
L = 1.0uH
C
= 3x10uF (ceramic 1206) + 1X330uF (electrolytic)
in
C
= 3x22uF (ceramic 0805)
out
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
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IRDC3898-P3V3
CONNECTIONS and OPERATING INSTRUCTIONS
A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum of 6A load should be connected to VOUT+ and VOUT-. The inputs and output connections of the board are listed in Table I.
IR3898 has only one input supply and internal LDO generates Vcc from Vin. If operation with external Vcc is required, then R15 can be removed and external Vcc can be applied between Vcc+ and Vcc- pins. Vin pin and Vcc/LDOout pins should be shorted together for external Vcc operation.
The output can track voltage at the Vp pin. For this purpose, Vref pin is to be connected to ground (use zero ohm resistor for R21). The value of R14 and R28 can be selected to provide the desired tracking ratio
between output voltage and the tracking input.
Table I. Connections
Connection Signal Name
VIN+ Vin (+12V) VIN- Ground of Vin Vout+ Vout(+3.3V)
Vout- Ground for Vout
Vcc+ Vcc/ LDO_out Pin Vcc- Ground for Vcc input Enable Enable P_Good Power Good Signal AGnd Analog ground
LAYOUT
The PCB is a 4-layer board (2.23”x2”) using FR4 material. All layers use 2 Oz. copper. The PCB thickness is 0.062. The IR3898 and other major power components are mounted on the top side of the board.
Power supply decoupling capacitors, the bootstrap capacitor and feedback components are located close to IR3898. The feedback resistors are connected to the output at the point of regulation and are located close to the SupIRBuck IC. To improve efficiency, the circuit board is designed to minimize the
length of the on-board power ground current path.
8/15/2013
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
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IRDC3898-P3V3
Connection Diagram
Enable VDDQ
Vref
Sync
S-Ctrl
AGnd
Vin Gnd Gnd Vout
PGood
Vsns
Vcc+
Vcc-
Top View
Fig. 1: Connection Diagram of IR3899/98/97 Evaluation Boards
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
Bottom View
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IRDC3898-P3V3
Single point connection
between AGnd and PGnd
Fig. 2: Board Layout-Top Layer
Fig. 3: Board Layout-Bottom Layer
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
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IRDC3898-P3V3
Fig. 4: Board Layout-Mid Layer 1
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
Fig. 5: Board Layout-Mid Layer 2
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IRDC3898-P3V3
8/15/2013
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
Fig. 6: Schematic of the IR3898 evaluation board
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Bill of Materials
Item Qty Part Reference Value Description Manufacturer Part Number
1 1 C1 330uF
SMD Electrolytic F size 25V 20%
Panasonic
EEV-FK1E331P
2 3 C3 C4 C5 10uF
1206, 16V, X5R, 20%
TDK C3216X5R1C106M
3 4 C7 C12 C14 C24 0.1uF
0603, 25V, X7R, 10% Murata GRM188R71E104KA01B
4 1 C8 2200pF 0603,50V,X7R Murata GRM188R71H222KA01B
5 1 C11 130pF
0603, 50V, NP0, 5% Murata GRM1885C1H131JA01D
6 3
C15 C16 C17 22uF
0805, 6.3V, X5R, 20%
TDK C2012X5R0J226M
7 1 C23 2.2uF
0603, 16V, X5R, 20%
TDK C1608X5R1C225M
8 1 C26 5.6nF
0603, 25V, X7R, 10%
Murata GRM188R71E562KA01J
9 1 C32 1.0uF
0603, 25V, X5R, 10%
Murata GRM188R61E105KA12D
10 1 L1 1.0uH SMD 7.1x6.5x5mm,4.7mΩ TDK SPM6550T-1R0
11 1 R1 2.49K
Thick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF2491V
12 2 R2 R11 4.42K
Thick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF4421V
13 2 R3 R12 787
Thick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF7870V
14 1 R4 75
Thick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF75R0V
15 1 R6 20
Thick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF20R0V
16 1 R9 23.2K
Thick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF2322V
17 5 R10 R13 R14 R15 R50 0
Thick Film, 0603,1/10W
Panasonic ERJ-3GEY0R00V
18 2 R17 R18 49.9K
Thick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF4992V
19 1 R19 9.09K
Thick Film, 0603,1/10W,1%
Panasonic ERJ-3EKF9091V
20 1 U1 IR3898 PQFN 4x5mm IR IR3898MPBF
BOM IRDC3898 Vin-12V Vout-3.3V/6.0A Freq-1MHz
IRDC3898-P3V3
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=3.3V, Io=0-6A, Room Temperature, no airflow
IRDC3898-P3V3
Fig. 7: Start up at 6A Load
Ch1:Vo, Ch2:Enable, Ch3:Vin, Ch4:PGood
Fig. 9: Start up with 1.0V Pre Bias , 0A
Load, Ch1:V
o
Fig. 8: Start up at 6A Load,
Ch1:Vo, Ch2:Vcc, Ch3:Vin, Ch4:PGood
Fig. 10: Output Voltage Ripple, 6A load
Ch1: V
o
Fig. 11: Inductor node at 6A load
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Ch1:LX
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Fig. 12: Short circuit (Hiccup) Recovery
Ch1:Vo , Ch4:I
o
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=3.3V, Io=0-6A, Room Temperature, no air flow
IRDC3898-P3V3
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
Fig. 13: Transient Response, 3A to 6A step
Ch1:V
o Ch4-Io
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=3.3V, Io=0-6A, Room Temperature
IRDC3898-P3V3
Fig. 14: Bode Plot at 6A load shows a bandwidth of 156.1KHz and phase margin of 49.1 degrees
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
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TYPICAL OPERATING WAVEFORMS Vin=12.0V, Vo=3.3V, Io=0-6A, Room Temperature, no air flow
IRDC3898-P3V3
Fig. 15: Soft start and soft stop using S_Ctrl pin
Fig. 16: Feed Forward for Vin change from 7 to 16V and back to 7V
Ch2-Vo Ch3-Vin
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
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TYPICAL OPERATING WAVEFORMS
85
86
87
88
89
90
91
92
93
94
95
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Efficiency (%)
Load Current (A)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Power Dissipation (W)
Load Current (A)
Vin=12.0V, Vo=3.3V, Io=0-6A, Room Temperature, no air flow
IRDC3898-P3V3
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
Fig. 17: Efficiency versus load current
Fig. 18: Power loss versus load current
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THERMAL IMAGES Vin=12.0V, Vo=3.3V, Io=0-6A, Room Temperature, No Air flow
IRDC3898-P3V3
Fig. 19: Thermal Image of the board at 6A load
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
Test point 1 is IR3898: 60.020C
Test point 2 is inductor: 47.490C
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IRDC3898-P3V3
PCB METAL AND COMPONENT PLACEMENT
Evaluations have shown that the best overall performance is achieved using the substrate/PCB layout as shown in following figures. PQFN devices should be placed to an accuracy of 0.050mm on both X and Y axes. Self-centering behavior is highly dependent on solders and processes, and experiments should be run to confirm the limits of self-centering on specific processes. For further information, please refer to “SupIRBuck™ Multi-Chip Module (MCM) Power Quad Flat No-Lead (PQFN) Board Mounting Application Note.” (AN1132)
Figure 20: PCB Metal Pad Spacing (all dimensions in mm)
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IRDC3898-P3V3
SOLDER RESIST
IR recommends that the larger Power or Land Area pads are Solder Mask Defined (SMD.) This allows the underlying Copper traces to be as large as possible, which helps in terms of current carrying capability and device cooling capability. When using SMD pads, the underlying copper traces should be at least 0.05mm larger (on each edge) than the Solder Mask window, in order to accommodate any layer to layer misalignment. (i.e. 0.1mm in X & Y.) However, for the smaller Signal type leads around the edge of the device, IR recommends that these are Non Solder Mask Defined or Copper Defined. When using NSMD pads, the Solder Resist Window should be larger than the Copper Pad by at least 0.025mm on each edge, (i.e. 0.05mm in X&Y,) in order to accommodate any layer to
layer misalignment. Ensure that the solder resist in-between the smaller signal lead areas are at
least 0.15mm wide, due to the high x/y aspect ratio of the solder mask strip.
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
Figure 21: Solder resist
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IRDC3898-P3V3
STENCIL DESIGN
Stencils for PQFN can be used with thicknesses of 0.100-0.250mm (0.004-0.010"). Stencils thinner than
0.100mm are unsuitable because they deposit insufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. Stencils in the range of 0.125mm-0.200mm (0.005-0.008"), with suitable reductions, give the best results. Evaluations have shown that the best overall performance is achieved using the stencil design shown in following figure. This design is for a stencil thickness of 0.127mm (0.005").The reduction should be adjusted for stencils of other thicknesses.
Figure 22: Stencil Pad Spacing (all dimensions in mm)
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
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PACKAGE INFORMATION
IRDC3898-P3V3
Figure 23: Package Dimensions
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
This product has been designed and qualified for the Consumer market
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This evaluation board is a preliminary version meant for the engineering evaluation of the IR3898. Based on the results of the continuing evaluation, this board can evolve and change without notice
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice.04/11
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