International Rectifier IRS20955SPBF, IRS20955PBF Datasheet

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IRS20955(S)PbF

Data Sheet No. PD60303

PROTECTED DIGITAL AUDIO DRIVER

Features

• Floating PWM input enables easy half-bridge

implementation

• Programmable bidirectional over-current protection

with self-reset function

• Programmable preset deadtime for improved THD

performances

• High noise immunity

• ±100 V ratings deliver up to 500 W in output power

• 3.3 V/5 V logic compatible input

• Operates up to 800 kHz

• RoHS compliant

Description

The IRS20955 is a high voltage, high speed MOSFET driver with a floating PWM input designed for Class D audio amplifier applications.

Bi-directional current sensing detects over-current conditions during positive and negative load currents without any external shunt resistors. A built-in protection control block provides a secure protection sequence against overcurrent conditions and a programmable reset timer.

The internal deadtime generation block enables accurate gate switching and optimum deadtime setting for better audio performance, such as lower THD and lower audio noise floor.

Product Summary

V

OFFSET

(max)

± 100 V

Io+ 1.0 A

Gate driver

I

o-

1.2 A

Selectable deadtime

15 ns, 25 ns,

35 ns, 45ns

Propagation delay 90 ns

OC protection delay 500 ns (max) Shutdown propagation

delay

250 ns (max)

Package

16-Lead PDIP

Typical Connection

(Please refer to Lead Assignments for correct pin configuration. This diagram shows electrical connections only)

IRS20955 (S)

12V

VDD

IN

CSD

VSS

COM

OCSET

LO

VCC

HO

VS

DT

CSH

VB

-B

Vcc

Speaker

+B

PWM

VREF

NC

IRS20955(S)PbF

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions

.

Symbol Definition Min. Max. Units

V

B

High-side floating supply voltage -0.3 220

VS High-side floating supply voltage (Note1) VB-20

VB+0.3

V

HO

High-side floating output voltage Vs-0.3 VB+0.3

V

CSH

CSH pin input voltage Vs-0.3 VB+0.3

V

CC

Low-side fixed supply voltage (Note1) -0.3 20

V

LO

Low-side output voltage -0.3 VCC +0.3

VDD Floating input supply voltage -0.3 210

VSS Floating input supply voltage (Note1) (See I

DDZ

)

VDD+0.3

VIN PWM input voltage VSS -0.3

VDD+0.3

V

CSD

CSD pin input voltage VSS -0.3

VDD+0.3

VDT DT pin input voltage

-0.3 VCC +0.3

V

OCSET

OCSET pin input voltage

-0.3 VCC +0.3

V

REF

VREF pin voltage

-0.3 VCC +0.3

V

I

DDZ

Floating input supply Zener clamp current (Note1) -

10

I

CCZ

Low side supply Zener clamp current (Note1) - 10

I

BSZ

Floating supply Zener clamp current (Note1) - 10

I

OREF

Reference output current - 5

mA

d VS /dt Allowable VS voltage slew rate -

50

d VSS /dt Allowable VSS voltage slew rate (Note2) - 50

V/ns

d VSS /dt Allowable VSS voltage slew rate upon power-up (Note3) - 50 V/ms

PD Maximum power dissipation - 1.0 W

R

th,JA

Thermal resistance, junction to ambient - 115

°C/W

T

J

Junction temperature - 150

T

S

Storage temperature -55 150

T

L

Lead temperature (soldering, 10 seconds) - 300

°C

Note1: V

DD

- VSS, VCC -COM and VB - VS contain internal shunt Zener diodes. Please note that the voltage ratings of these can be limited by the clamping current. Note2: For the rising and falling edges of step signal of 10 V. V

ss

=15 V to 200 V.

Note3: V

ss

ramps up from 0 V to 200 V.

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IRS20955(S)PbF

Recommended Operating Conditions

For proper operation, the device should be used within the recommended conditions below. The Vs and COM offset ratings are tested with supplies biased at I

DD

=5 mA, VCC=12 V and VB-VS=12 V.

Symbol

Definition Min. Max. Units

VB High-side floating supply absolute voltage Vs+10 Vs+18 V

S

High-side floating supply offset voltage Note 1 100

V

I

DDZ

Floating input supply zener clamp current 1 5 mA

VSS Floating input supply absolute voltage 0 200

VHO High-side floating output voltage Vs VB

V

CC

Low-side fixed supply voltage 10 18

VLO Low-side output voltage 0 VCC

VIN PWM input voltage

V

CSD

CSD pin input voltage

VSS V

DD

VDT DT pin input voltage 0 V

CC

V

I

OREF

Reference output current to COM (Note 2) 0.3 0.8 mA

V

OCSET

OCSET pin input voltage 0.5 5 V

T

A

Ambient temperature -40 125

°C

I

pw min

Minimum input pulse width 10 (Note 3) - ns

Note 1: Logic operational for V

S

equal to –5 V to +200 V. Logic state held for VS equal to –5 V to –VBS.

Note 2: Nominal voltage for V

REF

is 5 V. I

OREF

of 0.3 mA – 0.8 mA dictates total external resistor value on V

REF

to be 6.3 kΩ to 16.7 kΩ. Note 3: Output logic status may not respond correctly if input pulse width is smaller than the minimum pulse width.

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IRS20955(S)PbF

Electrical Characteristics

VCC ,VBS= 12 V, IDD=5 mA, VSS=20 V, VS=0 V,CL=1 nF and TA=25 °C unless otherwise specified.

Symbol Definition

Min

Typ

Max Units Test Conditions

Low-Side Supply

UV

CC+

VCC supply UVLO positive threshold 8.4 8.9 9.4

UV

CC-

VCC supply UVLO negative threshold 8.2 8.7 9.2

V

I

QCC

Low-side quiescent current - - 3 mA VDT = VCC

V

CLAMPL

Low-side Zener diode clamp voltage 19.6 20.4 21.6 V ICC=5 mA

High-Side Floating Supply

UV

BS+

High-side well UVLO positive

threshold

8.0 8.5 9.0

UV

BS-

High-side well UVLO negative

threshold

7.8 8.3 8.8

V

I

QBS

High-side quiescent current - - 1 mA

I

LKH

High-side to low-side leakage current - - 50 µA VB=VS =200 V

V

CLAMPH

High-side Zener diode clamp voltage 19.6 20.4 21.6 V IBS=5 mA

Floating Input Supply

UV

DD+

VDD, VSS floating supply UVLO positive threshold

8.2 8.7 9.2 V

SS

=0 V

UV

DD-

VDD, VSS floating supply UVLO

negative threshold

7.7 8.2 8.7

V

SS

=0 V

I

QDD

Floating input quiescent current - - 1 mA VDD=9.5 V +VSS

V

CLAMPM

Floating input Zener diode clamp

voltage

9.8 10.2 10.8 V I

DD

=5 mA

I

LKM

Floating input side to low-side leakage

current

- - 50 µA V

DD=VSS

=200 V

Floating PWM Input

V

IH

Logic high input threshold voltage 2.3 1.9 -

V

IL

Logic low input threshold voltage - 1.9 1.5

V

I

IN+

Logic “1” input bias current - - 40 VIN =3.3 V

I

IN-

Logic “0” input bias current - - 1

µA

VIN = VSS

Protection

V

REF

Reference output voltage 4.8 5.1 5.4 I

OREF

=0.5 mA

V

th,OCL

Low-side OC threshold in Vs 1.1 1.2 1.3

OCSET=1.2 V,

Fig. 3

V

th,OCH

High-side OC threshold in V

CSH

1.1+ VS 1.2+ VS 1.3+ VS

V

S

=200 V,

Fig. 4

V

th,1

CSD pin shutdown release threshold 0.62 x VDD 0.70 x VDD 0.78 x VDD

V

th,2

CSD pin self reset threshold 0.26 x VDD 0.30 x VDD 0.34 x VDD

V

SS

=0 V

I

CSD+

CSD pin discharge current 70 100 130

I

CSD-

CSD pin charge current 70 100 130

µA V

SD

= VSS +5 V

tSD

Shutdown propagation delay from V

CSD

> VSS + V

th,OCH

to Shutdown

- - 250 Fig. 2

t

OCH

Propagation delay time from V

CSH

>

V

th,OCH

to shutdown

- - 500 Fig. 4

t

OCL

Propagation delay time from Vs> V

th,OCL

to shutdown

- - 500

ns

Fig. 3

Gate Driver

Io+

Output high short circuit current (source)

- 1.0 - VO =0 V, PW<10 µs

Io- Output low short circuit current (sink) - 1.2 -

A

VO =12 V, PW<10 µs

VOL

Low level output voltage LO – COM, HO – VS

- - 0.1 V

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IRS20955(S)PbF

Electrical Characteristics (cont.)

VCC ,VBS= 12 V, IDD=5 mA, VSS=20 V, VS=0 V,CL=1 nF and TA=25 °C unless otherwise specified.

VOH

High level output voltage VCC – LO, VB – HO

- - 1.4 V I

O

=0 A

tr Turn-on rise time - 15 tf Turn-off fall time - 10 -

t

on,1

High-side and low-side turn-on propagation delay, floating inputs

- 105 -

t

off,1

High-side and low-side turn-off propagation delay, floating inputs

- 90 -

V

DT

= V

CC,

VS = 100 V, V

SS

= 100 V

t

on,2

High-side and low-side turn-on propagation delay, non-floating inputs

- 105 -

t

off,2

High-side and low-side turn-off propagation delay, non-floating inputs

- 90 -

V

DT

= V

CC,

VS = 100V,

V

SS

= COM

DT1

Deadtime: LO turn-off to HO turn-on (DT

LO-HO

) & HO turn-off to LO turn-on

(DT

HO-LO

)

8 15 22

V

DT>VDT1,

V

SS

= COM

DT2

Deadtime: LO turn-off to HO turn-on (DT

LO-HO

) & HO turn-off to LO turn-on

(DT

HO-LO

)

15 25 35

V

DT1>VDT

> V

DT2,

V

SS

= COM

DT3

Deadtime: LO turn-off to HO turn-on (DT

LO-HO

) & HO turn-off to LO turn-on

(DT

HO-LO

)

20 35 50

V

DT2>VDT

> V

DT3,

V

SS

= COM

DT4

Deadtime: LO turn-off to HO turn-on (DT

LO-HO

) & HO turn-off to LO turn-on

(DT

HO-LO)VDT

= V

DT4

25 45 60

ns

V

DT3>VDT

> V

DT4,

V

SS

= COM

V

DT1

DT mode select threshold 2 0.51(V

cc

) 0.57(V

cc

) 0.63(V

cc

)

V

DT2

DT mode select threshold 3 0.32(V

cc

) 0.36(V

cc

) 0.40(V

cc

)

V

DT3

DT mode select threshold 4 0.21(V

cc

) 0.23(V

cc

) 0.25(V

cc

)

V

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IRS20955(S)PbF

Lead Definitions

Pin # Symbol Description

1

VDD Floating input positive supply

2

CSD Shutdown timing capacitor, referenced to VSS

3

IN PWM non-inverting input, in phase with HO

4

VSS Floating input supply return

5

NC

6

VREF 5 V reference output for setting OCSET

7

OCSET Low-side over-current threshold setting, referenced to COM

8

DT Input for programmable deadtime, referenced to COM

9

COM Low-side supply return

10

LO Low-side output

11

VCC Low-side logic supply

12

NC

13

VS High-side floating supply return

14

HO High-side output

15

VB High-side floating supply

16

CSH High-side over-current sensing input, referenced to VS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

IRS20955(S)

VDD

IN

CSD

VSS

OCSET

DT

VREF

COM

LO

VCC

HO

VS

CSH

VB

NC NC

IRS20955(S)

16-Lead SOIC (narrow body)

16-Lead PDIP

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IRS20955(S)PbF

Block Diagram

HIGH

SIDE

CS

VB

HO

VS

IN

LOW SIDE CS

CSD

UV Q

UV

DETECT

DEAD-TIME

VCC

LO

COM

VDD

VSS

CSH

PROTECTION

CONTROL

SD

OCSET

UV

DETECT

UV

DETECT

CHARGE/

DISCHARGE

HV

LEVEL

SHIFT

HV

LEVEL

SHIFT

HV

LEVEL

SHIFT

FLOATING INPUT

FLOATING HIGH SIDE

HV

LEVEL

SHIFT

HV

LEVEL

SHIFT

5V REG

DT

INPUT LOGIC

10.4V

20.8V

VREF

5.1V REFERENCE

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