International Rectifier IRS2092 Application Note

Application Note AN-1138

IRS2092(S) Functional Description

By Jun Honda, Xiao-chang Cheng, Wenduo Liu

Table of Contents

Page

General Description.................................................................................................1

Typical Implementation............................................................................................1

PWM Modulator.......................................................................................................3

MOSFET Selection..................................................................................................6

Protection Design....................................................................................................7

Deadtime Generator..............................................................................................12

Power Supply........................................................................................................14

Junction Temperature Estimation..........................................................................15

Board Layout Considerations................................................................................15

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IRS2092(S) General Description

The IRS2092(S) is a Class D audio amplifier driver
with integrated PWM modulator and over current
protection. Combined with two external MOSFETs
and a few external components, the IRS2092(S)
forms a complete Class D amplifier with dual over
current, and shoot-through protection, as well as
UVLO protection for the three bias supplies. The
versatile structure of the analog input section with
an error amplifier and a PWM comparator has the
flexibility of implementing different types of PWM
modulator schemes.
Loss-less current sensing utilizes R

DS(on)

of the
MOSFETs. The protection control logic monitors the
status of the power supplies and load current across
each MOSFET.
For the convenience of half bridge configuration, the
analog PWM modulator and protection logic are
constructed on a floating well.
The IRS2092(S) implements start-up click noise
elimination to suppress unwanted audible noise
during PWM start-up and shut-down.

Typical Implementation

The following explanations are based on a typical
application circuit with self-oscillating PWM topology
shown in Figure 1. For further information, refer to
the IRAUDAMP5 reference design.

2.7 kΩ

CSH

VB
HO
VS

VCC

LO

COM

DT

161

15

14

13

12

11

10

9

Vin

10 µF

10 µF

2.7 kΩ

10 µF

8.2 kΩ

3.3 kΩ10 µF

150

1 nF

2.2 nF

1.2 kΩ

2.2 nF

2

3

4

5

6

7

8

VAA
GND

IN-

COMP

CSD
VSS

VREF

OCSET

IRS2092

Figure 1 IRS2092(S) Typical Application Circuit

47 kΩ

BAV19WS

10 kΩ

22 µF

10 µF

3.3 kΩ

8.2 kΩ

Input Section

The audio input stage of IRS2092(S) is configured
as an inverting error amplifier.
In Figure 2, the voltage gain of the amplifier GV is
determined by input resistor RIN and feedback
resistor RFB.

R

G =

FB

V

R

IN

Since the feedback resistor RFB is part of an
integrator time constant, which determines switching
frequency, changing overall voltage gain by RIN is
simpler and, therefore, recommended in most
cases.

Note that the input impedance of the amplifier is
equal to the input resistor RIN.

A DC blocking capacitor C3 should be connected in
series with RIN to minimize DC offset in the output. A
ceramic capacitor is not recommended due to
potential distortion. Minimizing DC offset is essential
for audible noise-less Turn-ON and -OFF.

The connection of the non-inverting input IN+ is a
reference for the error amplifier, and thus is crucial
for audio performance. Connect IN+ to the signal
reference ground in the system, which has same
potential as the negative terminal of the speaker
output.

+B

33 kΩ

MURS120

10 Ω

4.7 Ω

10 Ω

Vcc

12 V

IRF6645

IRF6645

0.1 µF

1 Ω

0.1 µF

22 µH

0.47 µF

-B

35 V

Speaker

4 Ω

35 V

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C1 C2

R1

Vin

C3

R

IN

IN-

GND

+

R

FB

Figure 2 IRS2092(S) Typical Control Loop Design

OTA

The front end error amplifier of the IRS2092(S)
features an operational trans-conductance amplifier
(OTA), which is carefully designed to obtain optimal
audio performance. The OTA outputs a current
output to the COMP pin, unlike a voltage output in
an operational amplifier (OPA). The non-inverting
input is internally tied to the GND pin.
The inverting input has clamping diodes to GND to
improve recovery from clipping as well as ensuring
stable start up. The OTA output COMP is internally
connected to the PWM comparator whose threshold
is (VAA-VSS)/2.

For stable operation of the OTA, a compensation
capacitor Cc minimum of 1nF is required.

The OTA is shut off when V

CSD

<Vth2.

PWM Modulator

The IRS2092(S) allows the user to choose from
numerous ways of PWM modulator
implementations. In this section, all the
explanations are based on a typical application
circuit of a self oscillating PWM.

Self-Oscillating PWM Modulator Design

The typical application features self oscillating
PWM scheme. For better audio performance,
2nd order integration in the front end is chosen.

Cc

COMP

Gate Driver

COMP

PWM

Protection

Self-Oscillating Frequency

Self oscillating frequency is determined mainly
by the following items in Figure 2.

· Integration capacitors, C1 and C2

· Integration resistor, R1

· Propagation delay in the gate driver

· Feedback resistor, RFB

· Duty cycle

Self oscillating frequency has little influences
from bus voltage and input resistance RIN.
Note that as is the nature of a self-oscillating
PWM, the switching frequency decreases as
PWM modulation deviates from idling.

Determining Self-Oscillating Frequency

Choosing switching frequency entails making a
trade off between many aspects.

At lower switching frequency, the efficiency at
MOSFET stage improves, but inductor ripple
current increases. The output carrier leakage
increases.

At higher switching frequency, the efficiency
degrades due to switching loss, but wider
bandwidth can be achieved. The inductor ripple
decreases yet iron loss increases. The junction
temperature of gate driver IC might be a stopper
for going higher frequency.

For these reasons, 400kHz is chosen for a
typical design example, which can be seen in
the IRAUDAMP5 reference design.

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Choosing External Components Value

For suggested values of components for a given
target self oscillating frequency, refer to Table 1.

The OTA output has limited voltage and current
compliances. These sets of components values
are to ensure that OTA operates within its linear
region so optimal THD+N performance can be
achieved.

In case target frequency is somewhere in
between the frequencies listed in the Table 1,
adjust the frequency by tweaking R1, if
necessary.

Target Self-

Oscillation
Frequency

(kHz)

C1=C2

(nF)

R1

(ohms)

500 2.2 200
450 2.2 165
400 2.2 141
350 2.2 124
300 2.2 115
250 2.2 102
200 4.7 41.2
150 10 20.0
100 10 14.0

70 22 4.42

Condition:IRS2092 with IRFB4212, Vbus=+/-35V, DT=25ns,

RFB=47k.

Table 1 External Component Values vs. Self

Oscillation Frequency

Clock Synchronization

In the typical PWM control loop design, the self­oscillating frequency can be set and
synchronized to an external clock. Through a
set of resistor and a capacitor, the external
clock injects periodic pulsating charges into the
integrator, forcing oscillation to lock up to the
external clock frequency. Typical setup with
5Vp-p 50% duty clock signal uses RCK=22k and
CCK=33pF in Figure 3. To maximize audio
performance, the self running frequency without
clock injection should be 20 to 30% higher than
the external clock frequency.

EXT. CLK

Vin

CK

R

C1 C2

CCKR

R1

COMP

IN

IN-

GND

+

R

FB

Figure 3 External Clock Sync

Figure 4 shows how self-oscillating frequency locks
up to an external clock frequency.

600

500

400

300

200

Operating Frequenc y (kHz)

100

0

10% 20% 30% 40% 50% 60% 70% 80% 90%

Duty Cycle

Figure 4 Typical Lock Range to External Clock

Click Noise Elimination

The IRS2092(S) has a unique feature that
minimizes Turn-ON and -OFF audible click noise.
When CSD is in between Vth1 and Vth2 during start
up, an internal closed loop around the OTA enables
an oscillation that generates voltages at COMP and
IN-, bringing them to steady state values. It runs at
around 1MHz, independent from the switching
oscillation.

C3

R

Vin

C1 C2

R1

IN

IN-

GND

+

R

FB

Cc

COMP

COMP

PWM

Start-up

Figure 5 Click Noise Elimination

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As a result, all capacitive components connected to
COMP and IN- pins, such as C1, C2, C3 and Cc in
Figure 5, are pre-charged to their steady state
values during the star up sequence. This allows
instant settling of PWM operation.

To utilize the click noise reduction function, following
conditions must be met.

1. CSD pin has slow enough ramp up from
Vth1 to Vth2 such that the voltages in the
capacitors can settle to their target values.

2. High side bootstrap power supply needs to
be charged up prior to starting oscillation.

3. Audio input has to be zero.

4. For internal local loop to override external
feedback during the startup period, DC
offset at speaker output prior to shutdown
release has to satisfy the following
condition.

RADCoffset ×<m30

FB

CSD Voltage and OTA Operational Mode

The CSD pin determines the operational mode of
the IRS2092(S). The OTA has three operational
modes; cut off, local oscillation and normal
operation while the gate driver section has two
modes; normal and shutdown with CSD voltage.

When V
the OTA is cut off.

When Vth2< V
are still in shutdown mode. The OTA is activated
and starts local oscillation, which pre-biases all the
capacitive components in the error amplifier.

When V
operation starts.

< Vth2, the IC is in shutdown mode and

CSD

< Vth1, the HO and LO outputs

CSD

>Vth1, shutdown is released and PWM

CSD

V

CSD

V

AA

V

th1

V

th2

OTA Operational Mode

Gate Driver Stage

Shutdown

Pop-less

Startup

Shutdown

OTA in Active

Release

Figure 6 V

and OTA Mode

CSD

Self-oscillation Start-up Condition

The IRS2092(S) requires the following
conditions to be met to start PWM oscillation in
the typical application circuit.

- All the control power supplies, VAA,
VSS, VCC and VBS are above the
under voltage lockout thresholds.

- CSD pin voltage is over Vth1 threshold.

-

ii <

FBIN

Where

V

i = ,

IN

IN

R

IN

i

FB

V

= .

R

Note that this condition also limits the maximum
audio input voltage feeding into R1. If this
condition is exceeded, the amplifier stops its
oscillation during the operation period. This
allows a 100% modulation index; however, a
care should be taken so that the high side
floating supply does not decay due to a lack of
low side pulse ON state.

B

+

FB

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MOSFET Selection
There are a couple of limitations on size of MOSFET
to be combined with the IRS2092(S).

1. Power dissipation
Power dissipation from gate driver stage in the
IRS2092(S) is proportional to switching
frequency and gate charge of MOSFET. Higher
the switching frequency the lower the gate
charge that can be used.
Refer to Junction Temperature Estimation later
in this application note for details.

2. Switching Speed
Internal over current protection has a certain
time window to measure the output current. If
switching transition takes too long, the internal
OCP circuitry starts monitoring voltage across
the MOSFET that induces false triggering of
OCP. Less than 40nC of gate charge per output
is recommended.

The IRS2092(S) accommodates a range of IR
Digital Audio MOSFETs, providing a scalable design
for various output power levels. For further
information on MOSFET section, refer to AN-1070,
Class D Amplifier Performance Relationship to
MOSFET Parameters.

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