International Rectifier suggests the following guidelines for safe operation and handling of
IRAUDAMP10 Demo board;
Always wear safety glasses whenever operating Demo Board
Avoid personal contact with exposed metal surfaces when operating Demo Board
Turn off Demo Board when placing or removing measurement probes
TEST PROCEDURES ....................................................................................................................................... 6
PERFORMANCE AND TEST GRAPHS .......................................................................................................... 7
PROTECTION SYSTEM OVERVIEW ............................................................................................................ 21
CLICK AND POP NOISE REDUCTION ......................................................................................................... 23
BUS PUMPING ............................................................................................................................................... 24
INPUT SIGNAL AND GAIN SETTING ........................................................................................................... 24
GAIN SETTING ............................................................................................................................................... 25
The IRAUDAMP10 Demo board is a reference design which uses only one IC (IRS2052M) to derive
appropriate input signals, amplify the audio input, and achieve a two-channel 280 W/ch (4Ω, THD+N=1%)
half-bridge Class D audio power amplifier. The reference design demonstrates how to use the IRS2052M
Class D audio controller and gate driver IC, implement protection circuits, and design an optimum PCB
layout using IRF6775 DirectFET MOSFETs. The reference design contains all the required housekeeping
power supplies for ease of use. The two-channel design is scalable, for power and number of channels.
Applications
AV receivers
Home theater systems
Mini component stereos
Powered speakers
Sub-woofers
Musical Instrument amplifiers
Automotive after market amplifiers
Features
Output Power: 300W x 2 channels (4Ω, THD+N=1%)
or 370W x 2 channels (4Ω, THD+N=10%)
Residual Noise: 220V, IHF-A weighted, AES-17 filter
Distortion: 0.008% THD+N @ 100W, 4Ω
Efficiency: 90% @ 300W, 4Ω, single-channel driven, Class D stage
Multiple Protection Features: Over-current protection (OCP), high side and low side
Over-voltage protection (OVP),
Under-voltage protection (UVP), high side and low side
General Test Conditions (unless otherwise noted) Notes / Conditions
Supply Voltages ±50V
Load Impedance 4Ω
Self-Oscillating Frequency 500kHz No input signal, Adjustable
Gain Setting 30.8dB 1Vrms input yields rated power
Electrical Data Typical Notes / Conditions
IR Devices Used IRS2052M Audio Controller and Gate-Driver,
IRF6775 DirectFET MOSFETs
Modulator Self-oscillating, second order sigma-delta modulation, analog input
Power Supply Range ± 25V to ±50V Bipolar power supply
Output Power CH1-2: (1% THD+N) 300W 1kHz, ±50V
Output Power CH1-2: (10% THD+N) 370W 1kHz, ±50V
www.irf.com Page 3 of 34
IRAUDAMP10 REV 1.1
Page 4
Rated Load Impedance 8-4Ω Resistive load
Standby Supply Current +45/-95mA No input signal
Total Idle Power Consumption 7W No input signal
Channel Efficiency 90% Single-channel driven,
1 CH1 INPUT Analog input for CH1
2 GND Floating ground of Channel 1 input
3 GND Floating ground of Channel 2 input
4 CH2 INPUT Analog input for CH2
1 -B -50V supply referenced to GND.
2 GND Ground signal from MB.
3 +B +50V supply referenced to GND.
1 CH2 OUTPUT Output of Channel 2
2 GND Floating ground of Channel 2 output
1 GND Floating ground of Channel 1 output
2 CH1 OUTPUT Output of Channel 1
www.irf.com Page 5 of 34
IRAUDAMP10 REV 1.1
Page 6
Test Procedures
Test Setup:
1. Connect 4-200 W dummy loads to 2 output connectors (P2 and P3 as shown on Fig 1)
and an Audio Precision analyzer (AP).
2. Connect the Audio Signal Generator to CN1 for CH1~CH2 respectively (AP).
3. Set up the dual power supply with voltages of ±50V; current limit to 5A.
4. TURN OFF the dual power supply before connecting to On of the unit under test (UUT).
5. Connect the dual power supply to P1. as shown on Fig 1
Power up:
6. Turn ON the dual power supply. The ±B supplies must be applied and removed at the
same time.
7. One orange and two blue LED should turn ON immediately and stay ON
8. Quiescent current for the positive supply should be 45mA 10mA at +50V.
9. Quiescent current for the negative supply should be 95mA 10mA at –50V.
Switching Frequency test
10. With an Oscilloscope, monitor the switching waveform at test points VS1~VS2. Adjust
VR1A and VR1B to set the self oscillating frequency to 500 kHz 25 kHz when DUT in
free oscillating mode.
Functionality Audio Tests:
11. Set the signal generator to 1kHz, 20 mV
12. Connect the audio signal generator to CN1(Input of CH1,CH2,CH3)
13. Sweep the audio signal voltage from 15 mV
14. Monitor the output signals at P2/P3 with an oscilloscope. The waveform must be a non
distorted sinusoidal signal.
15. Observe that a 1 V
input generates an output voltage of 34.88 V
RMS
ratio, R4x/(R3x) and R30x/(R31x), determines the voltage gain of IRAUDAMP10.
output.
RMS
RMS
to 1 V
RMS
.
(CH1/CH2). The
RMS
Test Setup using Audio Precision (Ap):
16. Use an unbalanced-floating signal from the generator outputs.
17. Use balanced inputs taken across output terminals, P2 and P3.
18. Connect Ap frame ground to GND at terminal P1.
19. Select the AES-17 filter(pull-down menu) for all the testing except frequency response.
20. Use a signal voltage sweep range from 15 mV
21. Run Ap test programs for all subsequent tests as shown in Fig 2- Fig 7below.
to 1.5 V
RMS
RMS
.
www.irf.com Page 6 of 34
IRAUDAMP10 REV 1.1
Page 7
Performance and test graphs
10
5
2
1
0.5
0.2
0.1
%
0.05
0.02
0.01
0.005
0.002
0.001
100m500200m500m125102050100200
ColorSweep TraceLine Style Thick DataA xis C omm ent
11BlueSolid2Anlr.TH D+N Ratio LeftCH2
13M agenta Solid2Anlr.THD+ N Ratio LeftCH1
±B Supply = ±50V, 4 Ω Resistive Load
Fig 2 IRAUDAMP10, THD+N versus Power, Stereo, 4 Ω
W
.
+4
+2
+0
d
-2
B
r
-4
A
-6
-8
-10
20200k501002005001k2k5k10k20k50k100k
Hz
ColorSweep TraceLine Style Thick DataAxis Comment
11BlueSolid2Anlr.Level B LeftCH2
12Magenta Sol id2Anlr. Level A LeftCH1
T
±B Supply = ±50V, 4 Ω Resistive Load
Fig 3 IRAUDAMP10, Frequency response
www.irf.com Page 7 of 34
IRAUDAMP10 REV 1.1
Page 8
100
10
1
0.1
%
0.01
0.00 1
0.0001
2020k501002005001k2k5k10k
Hz
Col orSweep TraceLine St yle Thick DataAxi s Comment
11GreenSolid2Anlr.THD+N Ratio Left10W
21Yell ow Solid2Anlr.THD+N Ratio Left50W
31RedSol i d2A nl r . THD+N Rati o Left100W
Fig 4 THD+N Ratio vs. Frequency
+0
-10
-20
-30
-40
d
-50
B
-60
V
-70
-80
-90
-100
-110
1020k20501002005001k2k5k10k
ColorSweep TraceLine Sty le Thick DataAxis Comm ent
11BlueSolid2Fft.Ch.1 Ampl LeftCH2
12Magenta S olid2Fft.Ch.2 Am pl LeftCH1
Hz
Fig 5, 1V output Frequency Spectrum
www.irf.com Page 8 of 34
IRAUDAMP10 REV 1.1
Page 9
+20
+0
-20
-40
d
-60
B
V
-80
-100
-120
-140
1020k20501002005001k2k5k10k
Hz
ColorSweep TraceLine Style Thick DataAxis Comment
11BlueS olid2Fft.Ch.1 Ampl LeftCH2
12Magenta S olid2Fft.Ch.2 Ampl LeftCH1
No signal, Self Oscillator @ 500kHz
Fig 6, IRAUDAMP10 Noise Floor
.
+0
-10
-20
-30
-40
d
B
r
-50
A
-60
-70
-80
-90
-100
2020k501002005001k2k5k10k
ColorSweep TraceLine Style Thick D ataAxis Comm ent
11BlueSolid2Anlr.Ampl Left CH2-CH1
12Magenta Solid2Anlr.Ampl LeftCH1-CH2
Fig 7, Channel separation vs. frequency
Hz
www.irf.com Page 9 of 34
.
IRAUDAMP10 REV 1.1
Page 10
Soft Clipping
IRS2052M has Clipping detection function, it monitors error voltage in COMP pin with a window
comparator and pull an open drain nmos referenced to GND. Threshold to detect is at 10% and
90% of VAA-VSS. Each channel has independent CLIP outputs. Once IRS2052M detects
Clipping, the CLIP pin can generate pulses to trigger soft clipping circuit, which can limit output’s
maximum power as Fig 9(soft clipping circuit is not available on AMP10 reference board).
Soft Clipping
Audio signal INPUT
C0A
10uF,50V
R27A
3.3K
R28A
1K
C15A
10uF, 16V
VSS
R29A
220K
D
S
GND
D3A
1N4148
Q6
MMBFJ112
R7A
470K
G
C6A
1uF,50V
R5A
47K
R6A
47K
C5A
10uF, 50V
R3A1K
Fig 9 Soft Clipping Circuit
Q5
DTA144EKA
GND
VAA
CLIP Detection
IN-
www.irf.com Page 10 of 34
IRAUDAMP10 REV 1.1
Page 11
)
Efficiency
Fig 10 shows efficiency characteristics of the IRAUDAMP10. The high efficiency is achieved by
following major factors:
1) Low conduction loss due to the DirectFETs offering low R
2) Low switching loss due to the DirectFETs offering low input capacitance for fast rise and
fall times
Secure dead-time provided by the IRS2052M, avoiding cross-conduction.
With this high efficiency, the IRAUDAMP10 design can handle one-eighth of the continuous rated
power, which is generally considered to be a normal operating condition for safety standards,
without additional heatsinks or forced air-cooling.
www.irf.com Page 11 of 34
IRAUDAMP10 REV 1.1
Page 12
Thermal Interface Material’s Pressure Control
The pressure between DirectFET & TIM (Thermal Interface Material) is controlled by depth of Heat
Spreader’s groove. Choose TIM which is recommended by IR. (Refer to AN-1035 for more
details). TIM’s manufacturer thickness, conductivity, & etc. determine pressure requirement.
Below shows selection options recommended:
www.irf.com Page 12 of 34
Fig 11 TIM Information
IRAUDAMP10 REV 1.1
Page 13
Check the TIM’s compression deflection with constant rate of strain (example as Fig.12) base on
manufacturer’s datasheet. According to the stress requirement, find strain range for the TIM. Then,
calculate heat spreader groove depth as below:
**DirectFET’s height should be measured from PCB to the top of DirectFET after reflow. The
average height of IRF6775 is 0.6mm.
Fig 12 compression deflection with constant rate of strain
www.irf.com Page 13 of 34
IRAUDAMP10 REV 1.1
Page 14
Power Supply Rejection Ratio (PSRR)
The IRAUDAMP10 obtains good power supply rejection ratio of -60 dB at 1kHz shown in Fig 13.
With this high PSRR, IRAUDAMP10 accepts any power supply topology when the supply voltages
fit between the min and max range.
+0
-10
-20
-30
-40
d
B
-50
-60
-70
-80
-90
2040k501002005001k2k5k10k20k
Hz
ColorSweep TraceLine St yle Thick DataA xis Comment
21RedSolid2Anlr. Ratio Left
Fig 13 Power Supply Rejection Ratio (PSRR)
www.irf.com Page 14 of 34
IRAUDAMP10 REV 1.1
Page 15
Short Circuit Protection Response
Figs 14-15 show over current protection reaction time of the IRAUDAMP10 in a short circuit event.
As soon as the IRS2052M detects an over current condition, it shuts down PWM. After one
second, the IRS2052M tries to resume the PWM. If the short circuit persists, the IRS2052M
repeats try and fail sequences until the short circuit is removed.
Short Circuit in Positive and Negative Load Current
VS pin
VS pin
VS pin
CSD pin
CSD pin
VS pin
Load current
Positive OCP
Fig 14 Positive and Negative OCP Waveforms
.
OCP Waveforms Showing CSD Trip and Hiccup
VS pin
VS pin
Load current
Load current
Load current
Load current
CSD pin
Load current
Negative OCP
CSD pin
Fig 15 OCP Response with Continuous Short Circuit
www.irf.com Page 15 of 34
IRAUDAMP10 REV 1.1
Page 16
IRAUDAMP10 Overview
The IRAUDAMP10 features a 2CH self-oscillating type PWM modulator for the smallest space,
highest performance and robust design. This topology represents an analog version of a secondorder sigma-delta modulation having a Class D switching stage inside the loop. The benefit of the
sigma-delta modulation, in comparison to the carrier-signal based modulation, is that all the error
in the audible frequency range is shifted to the inaudible upper-frequency range by nature of its
operation. Also, sigma-delta modulation allows a designer to apply a sufficient amount of error
correction.
The IRAUDAMP10 self-oscillating topology consists of following essential functional blocks.
Referring to Fig 16 below, the input operational amplifier of the IRS2052M forms a front-end
second-order integrator with R3x, C2x, C3x, and R2x. The integrator that receives a rectangular
feedback signal from the PWM output via R4x and audio input signal via R3x generates a
quadratic carrier signal at the COMP pin. The analog input signal shifts the average value of the
quadratic waveform such that the duty cycle varies according to the instantaneous voltage of the
analog input signal.
PWM Comparator
The carrier signal at the COMP pin is converted to a PWM signal by an internal comparator that
has a threshold at middle point between VAA and VSS. The comparator has no hysteresis in its
input threshold.
Level Shifters
The internal input level-shifter transfers the PWM signal down to the low-side gate driver section.
The gate driver section has another level-shifter that level shifts up the high-side gate signal to the
high-side gate driver section.
www.irf.com Page 16 of 34
IRAUDAMP10 REV 1.1
Page 17
Gate Drivers and DirectFETs
The received PWM signal is sent to the dead-time generation block where a programmable
amount of dead time is added into the PWM signal between the two gate output signals of LO and
HO to prevent potential cross conduction across the output power DirectFETs. The high-side levelshifter shifts up the high-side gate drive signal out of the dead-time block.
Each channel of the IRS2052M’s drives two DirectFETs, high- and low-sides, in the power stage
providing the amplified PWM waveform.
Output LPF
The amplified PWM output is reconstructed back to an analog signal by the output LC LPF.
Demodulation LC low-pass filter (LPF) formed by L1 and C13, filters out the Class D switching
carrier signal leaving the audio output at the speaker load. A single stage output filter can be used
with switching frequencies of 500 kHz and greater; a design with a lower switching frequency may
require an additional stage of LPF.
Fig 16 Simplified Block Diagram of IRAUDAMP10 Class D Amplifier
www.irf.com Page 17 of 34
IRAUDAMP10 REV 1.1
Page 18
Functional Descriptions
IRS2052M Gate Driver IC
The IRAUDAMP10 uses the IRS2052M, a 2 Channel high-voltage (up to 200 V), high-speed
power MOSFET driver with internal dead-time and protection functions specifically designed for
Class D audio amplifier applications. These functions include OCP and UVP. The IRS2052M
integrates bi-directional over current protection for both high-side and low-side MOSFETs. The
dead-time can be selected for optimized performance according to the size of the MOSFET,
minimizing dead-time while preventing shoot-through. As a result, there is no gate-timing
adjustment required externally. Selectable dead-time through the DT pin voltage is an easy and
reliable function which requires only two external resistors, R12 and R13 as shown on Fig 17 or
Fig 23 below.
The IRS2052M offers the following functions.
PWM modulator
Dead-time insertion
Over current protection
Under voltage protection
Level shifters
Refer to IRS2052M datasheet and AN-1159 for more details.
R14A
4.7R
C16A
0.01uF
R12 8.2K
C9A 10uF,16V
GND
C12A
220pF
R0A
100K
R31A 10K
C0A
10uF,50V
CN1
GND
CH2
4
3
GND
2
GND
1
CH1
C0B
10uF,50V
R31B
10K
R0B
100K
C12B
220pF
GND
C62
0.01uF, 50V
10k
R62
GND
GND
For EMI
R27A
15K
R30A
R30B
15K
C8A
3.3K
470pF
C8B
470pF
IC3
5
4
2IN+
GND
3
6
1IN+
2IN-
2
7
1IN-
2OUT
1
8
1OUT
VDD
NE5532AN
R27B
3.3K
C9
C10
4.7uF,10V
4.7uF,10V
GND
R14
R15
10R
10R
R4A
100K
R26A
37
10K
C2A
DSA
2.2nF,50V
VR1A
200R
R3A
C5A
GND
1K
10uF, 50V
R3B
C5B
1K
10uF, 50V
VR1B
200R
C2B
2.2nF,50V
R4B
100K
R2A 120R
R2B 120R
R26B 10K
C40
220uF/10V
C41
220uF/10V
38
C3A 2.2nF,50V
C4A
39
1nF,50V
40
41
R6 10R
C6 4.7uF,10V
VSS
42
VAA
43
C7
R7 10R
4.7uF,10V
44
C4B1nF,50V
C3B
45
2.2nF,50V
46
47
DSB
48
R22
10R
CSD
D3
1N4148
C8
10uF, 16V
D4
1N4148
SD
+5v
Q8MJD44H11T4G
Z5
5.6V
Z6
5.6V
Q9
MJD45H11T4G
-5v
R13 1K
R11 ** * R10 2.2K
31
34
33
36
32
35
NC
NC
VCC
VREF
NC
OCSET
CLIP2
COMP2
IN2
GND
VSS
VAA
IN1
COMP1
CLIP1
CSD
NC
R45
10k
R46
10k
IC1
IRS2052M
FAULT3OTW2NC
X1B
X1A
CKO
1
5
6
4
10K
10K
R511KR52
R105
R104
Y1
1 2
XTAL
DS2
DS3
C11
C12
330pF
330pF
VAA
VAA
R43
R47
470R,1W
470R,1W
S2
R44
R48
470R,1W
470R,1W
30
COM
0
-B
X2B
7
C13
330pF
Q3
MMBT5551
1K
1 2
29
NC28DT
OTP
-B
-B
X2A
XSL9NC
8
Y2
XTAL
C14
330pF
R32A 10R
27
25
26
NC
NC
VS2
VS111NC
10
12
R106 1k
C15
N/A
R54
10k
R56
47k
Z3
***
R53
10k
Q4
MMBT55 51
R55
47k
OVPUVP
RpA 90C
R22A
***
C10A
22uF,16V
R15A
R17A
***
24
NC
10K
R16A
23
HO2
22
VB2
21
CSH2
20
LO2
19
COM2
18
VCC2
17
LO1
16
CSH1
15
VB1
14
HO1
13
NC
R108
R57
47k
D1A
RF071M2STR
3.9K
R18A
4.7R
D2A
RF071M2STR
C9B
10uF,16V
R14B 4.7R
RF071M2STR
R18B
D2B
4.7R
R16B
3.9K
D1B
R17B
R15B
10K
***
RF071M2STR
C10B
22uF,16V
S1
3way SW
R22B
***
R107
3.9K
3.9K
VAAVSS
R50
47k
Z4
24V
R31
10k
DS1
R58
47k
C32
100uF, 25V
Q1
MJD44H11T4G
Q1A,C
IRF6665/6775M
R20A
10R
R9A
10R
Q2A,C
R71A
IRF6665/6775M
10K
DS4
DS5
R71B
10K
Q1B,D
IRF6665/6775M
R20B
10R
R9B
10R
Q2B,D
IRF6665/6775M
R36
100R,1W
R37
100R,1W
R39
R38
100R,1W
100R,1W
R40 10k
R41 10 k
Z1
12V
1R
R19A
C19A
0.1uF,100V
1R
R19B
C19B
0.1uF,100V
R12A
N/A
R12B
N/A
IRF6665 Ve rsion
Q1A, Q1B, Q1A, Q1B
IRF6775M Version
Q1C, Q1D, Q2C, Q2D
L1A
22uH
C13A
0.47uF, 400V
0.47uF, 400V
C13B
L1B
22uH
C17C
0.1uF,100V
C17D
0.1uF,100V
CH2 OUTPUT
CH1 OUTPUT
D1A, D1B
R11
R15A, R15B
D1C, D1D
1N4148
8.2k
RF071M 2
10k
5.6k
5.6k
CH3 OUTPUT
R24A 2.2K
GND
R21A
10R,1W
C14A
0.1uF, 63V
GND
C14B
0.1uF, 63V
R21B
10R,1W
GND
R24B 2.2K
CH1 OUTPUT
+B
R23A
C17A
100k
470uF,63V
GND
C17B
R23B
470uF,63V
100k
-B
P2
1
CH2
GND
2
1
-B
2
GND
3P1+B
P3
1
GND
CH1
2
R22A, R22B
Z3
22k
39V
33k
51V
Fig 17 System-level View of IRAUDAMP10
www.irf.com Page 18 of 34
IRAUDAMP10 REV 1.1
Page 19
Self-Oscillating Frequency
Self-oscillating frequency is determined by the total delay time along the control loop of the
system; the propagation delay of the IRS2052M, the DirectFETs switching speed, the timeconstant of front-end integrator (R2x, R3x, R4x, Vr1x, C2x, C3x ). Variations in +B and –B supply
voltages also affect the self-oscillating frequency.
The self-oscillating frequency changes with the duty ratio. The frequency is highest at idling. It
drops as duty cycle varies away from 50%.
Adjustments of Self-Oscillating Frequency
Use VR1x to set different self-oscillating frequencies. The PWM switching frequency in this type of
self-oscillating switching scheme greatly impacts the audio performance, both in absolute
frequency and frequency relative to the other channels. In absolute terms, at higher frequencies,
distortion due to switching-time becomes significant, while at lower frequencies, the bandwidth of
the amplifier suffers. In relative terms, interference between channels is most significant if the
relative frequency difference is within the audible range.
Normally, when adjusting the self-oscillating frequency of the different channels, it is suggested to
either match the frequencies accurately, or have them separated by at least 25kHz. Under the
normal operating condition with no audio input signal, the switching-frequency is set around
500kHz in the IRAUDAMP10.
Internal Clock Oscillator
The IRS2052M integrates two clock oscillators and synchronization networks for each PWM
channel. To prevent AM radio reception interference, two PWM frequencies are selectable via XSL
pin. As shown in Table 2, when XSL is bias to VAA, X1A and X1B are active. When XSL is GND
X2A and X2B are active. When XSL is VSS, both clock oscillators are disabled.
XSL pin X1A/B X2A/B
VAA
GND
VSS
CKO outputs internal clock with VAA/VSS amplitude. The CKO can distribute clock signal to
multiple IRS2052 devices to synchronize PWM switching timing.
Activated Disabled
Disabled Activated
Disabled Disabled
www.irf.com Page 19 of 34
IRAUDAMP10 REV 1.1
Page 20
Selectable Dead-time
The dead-time of the IRS2052 is set based on the voltage applied to the DT pin. Fig 18 lists the
suggested component value for each programmable dead-time between 45 and 105 ns.
All the IRAUDAMP10 models use DT1 (45ns) dead-time.
Dead-time Mode R1 R2 DT/SD Voltage
DT1 <10k Open Vcc
DT2
DT3
5.6k
4.7k
8.2k
3.3k
DT4 Open <10k COM
Recommended Resistor Values for Dead Time Selection
0.46 x Vcc
0.29 x Vcc
Dead- time
45nS
65nS
85nS
>0.5mA
R1
IRS2052M
Vcc
DT
105nS
Vcc 0.57 xVcc 0.36xVcc 0.23xVcc
V
DT
R2
COM
Fig 18 Dead-time Settings vs. VDT Voltage
www.irf.com Page 20 of 34
IRAUDAMP10 REV 1.1
Page 21
Protection System Overview
The IRS2052M integrates over current protection (OCP) inside the IC. The rest of the protections,
such as over-voltage protection (OVP), under-voltage protection (UVP), and over temperature
protection (OTP), are detected externally to the IRS2052M (Fig 19).
The external shutdown circuit will disable the output by pulling down CSD pins, (Fig 20). If the
fault condition persists, the protection circuit stays in shutdown until the fault is removed.
SD
R56
47k
Q3
MMBT5551
R54
10k
Z3
***
R53
10k
Q4
MMBT5551
R55
47k
GND
R57
47k
OTP pin from IRS2052M
R50
47k
R32A
10R
Z4
24V
RpA
90C
R58
47k
C16A
0.01uF
OVPUVP
-B
OTP
Fig 19 DCP, OTP, UVP and OVP Protection Circuits
.
Fig 20 Simplified Functional Diagram of OCP
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IRAUDAMP10 REV 1.1
Page 22
Over-Current Protection (OCP)
Low-Side Current Sensing
The low-side current sensing feature protects the low side DirectFET from an overload condition
from negative load current by measuring drain-to-source voltage across R
during its on state.
DS(ON)
OCP shuts down the switching operation if the drain-to-source voltage exceeds a preset trip level.
The voltage setting on the OCSET pin programs the threshold for low-side over-current sensing.
When the VS voltage becomes higher than the OCSET voltage during low-side conduction, the
IRS2052 turns the outputs off and pulls CSD down to -VSS.
High-Side Current Sensing
The high-side current sensing protects the high side DirectFET from an overload condition from
positive load current by measuring drain-to-source voltage across R
during its on state. OCP
DS(ON)
shuts down the switching operation if the drain-to-source voltage exceeds a preset trip level.
High-side over-current sensing monitors drain-to-source voltage of the high-side DirectFET during
the on state through the CSH and VS pins. The CSH pin detects the drain voltage with reference
to the VS pin, which is the source of the high-side DirectFET. In contrast to the low-side current
sensing, the threshold of the CSH pin to trigger OC protection is internally fixed at 1.2V. An
external resistive divider R15, R16 and R17 are used to program a threshold as shown in Fig 20.
An external reverse blocking diode D1 is required to block high voltage feeding into the CSH pin
during low-side conduction. By subtracting a forward voltage drop of 0.6V at D1, the minimum
threshold which can be set for the high-side is 0.6V across the drain-to-source.
Over-Voltage Protection (OVP)
OVP is provided externally to the IRS2052M. OVP shuts down the amplifier if the bus voltage
between GND and -B exceeds 51V. The threshold is determined by a Zener diode Z3. OVP
protects the board from harmful excessive supply voltages, such as due to bus pumping at very
low frequency-continuous output in stereo mode.
Under-Voltage Protection (UVP)
UVP is provided externally to the IRS2052M. UVP prevents unwanted audible noise output from
unstable PWM operation during power up and down. UVP shuts down the amplifier if the bus
voltage between GND and -B falls below a voltage set by Zener diode Z4.
Offset Null (DC Offset) Adjustment
The IRAUDAMP10 requires no output-offset adjustment. DC offsets are tested to be less than ±20
mV.
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IRAUDAMP10 REV 1.1
Page 23
Over-Temperature Protection (OTP)
The over temperature protection input OTP is for an external PTC Thermistor to monitor
temperature of MOSFET. The OTP pin equips a 0.6mA internal current source to bias the external
PTC resistor. Over temperature warning activates when the voltage at any of OTP input pin goes
higher than 1.4V. Over temperature protection activates when the voltage at any of OTP input pin
goes higher than 2.8V. A PTC thermistors, Rpa in Fig 19, is placed on bottom side PCB; which is
close to the 4 DirectFETs; and monitors DirectFETs’ temperature. If the temperature rises above
90 C on the bottom side, make OTP input pin goes high and shuts down all 2 channels by pulling
down the CSD pins of the IRS2052M. OTP recovers once the temperature cools down.
On-chip Over Temperature Protection
If the junction temperature TJ of IRS2052M becomes higher than on-chip thermal warning
threshold 127C, the on-chip over temperature protection pulls OTW pin down to GND. If the
junction temperature TJ keeps increasing and exceed on-chip thermal shutdown threshold 147C,
the on-chip over temperature protection shuts down PWM, pulls OTW up to VAA and pulls FAULT
pin down to GND as long as the junction temperature is higher than the threshold.
Over Temperature Warning Output (OTW)
OTW output is an open drain output referenced to GND to report whether the IRS2052M is
experiencing high temperature from either OTP input or on-chip OTP. OTW activates if OTP pin
voltage becomes higher than warning threshold, or if junction temperature reaches warning
threshold.
Fault Output
FAULT output is an open drain output referenced to GND to report whether the IRS2052M is in
shutdown mode or in normal operating condition. If FAULT pin is open, the IRS2052M is in normal
operation mode.
Following conditions triggers shutdown internally and pulls FAULT pin down to GND.
• Over Current Protection
• Over Temperature Protection (internal or external via OTP pin)
• Shutdown mode from CSD pin voltage
Click and POP Noise Reduction
Thanks to the click and pop elimination function built into the IRS2052M, the IRAUDAMP10 does
not require any additional components for this function.
www.irf.com Page 23 of 34
IRAUDAMP10 REV 1.1
Page 24
Power Supply Requirements
For convenience, the IRAUDAMP10 has all the necessary housekeeping power supplies onboard
and only requires a pair of symmetric power supplies.
House Keeping Power Supply
The internally-generated housekeeping power supplies include ±5V for analog signal processing,
and +12V supply (V
driver section of the IRS2052M uses VCC to drive gates of the DirectFETs. V
) referred to the negative supply rail -B for DirectFET gate drive. The gate
CC
is referenced to –
CC
B (negative power supply). D2x, R18x and C10x form a bootstrap floating supply for the HO gate
driver.
Bus Pumping
When the IRAUDAMP10 is running in stereo mode, the bus pumping effect takes place with low
frequency, high output. Since the energy flowing in the Class D switching stage is bi-directional,
there is a period where the Class D amplifier feeds energy back to the power supply. The majority
of the energy flowing back to the supply is from the energy stored in the inductor in the output LPF.
Usually, the power supply has no way to absorb the energy coming back from the load.
Consequently the bus voltage is pumped up, creating bus voltage fluctuations.
Following conditions make bus pumping worse:
1. Lower output frequencies (bus-pumping duration is longer per half cycle)
2. Higher power output voltage and/or lower load impedance (more energy transfers between
supplies)
3. Smaller bus capacitance (the same energy will cause a larger voltage increase)
The OVP protects IRAUDAMP10 from failure in case of excessive bus pumping. Bus voltage
detection monitors only +B supply, assuming the bus pumping on the supplies is symmetric in +B
and -B supplies.
Load Impedance
Each channel is optimized for a 4 Ω speaker load in half bridge.
Input Signal and Gain Setting
A proper input signal is an analog signal ranging from 20Hz to 20kHz with up to 3 V
with a source impedance of no more than 600 Ω. Input signal with frequencies from 30kHz to
60kHz may cause LC resonance in the output LPF, causing a large reactive current flowing
through the switching stage, especially with greater than 8 Ω load impedances, and the LC
resonance can activate OCP.
amplitude
RMS
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IRAUDAMP10 REV 1.1
Page 25
The IRAUDAMP10 has an RC network called a Zobel network (R21 and C14) to damp the
resonance and prevent peaking frequency response with light loading impedance. (Fig 21)
Fig 21 Output Low Pass Filter and Zobel Network
Gain Setting
The ratio of resistors {R4x/(R3x+R27x)}*(R30x/R31x) in Fig 22 sets voltage gain. The
IRAUDAMP10 has no on board volume control. To change the voltage gain, change the input
resistor term R27x and R3x. Changing R4x affects PWM control loop design and may result poor
audio performance.
www.irf.com Page 25 of 34
IRAUDAMP10 REV 1.1
Page 26
www.irf.com Page 26 of 34
IRAUDAMP10 REV 1.1
C4A
1nF,50V
C2A
2.2nF,50V
R2A 120R
C3B
2.2nF,50V
C4B1nF,50V
R7 10R
C6 4.7uF,10V
C7
4.7uF,10V
C2B
2.2nF,50V
R6 10R
R20A
10R
R9A
10R
R9B
10R
R20B
10R
R21A
10R,1W
C13A
0.47uF, 400V
C13B
0.47uF, 400V
C14A
0.1uF, 63V
CH3 OUTPUT
CH1 OUTPUT
R15B
***
R16B
3.9K
R17B
10K
D1B
RF071M2STR
R14B 4.7R
C9B
10uF,16V
R16A
3.9K
D1A
RF071M2STR
R15A
***
R17A
10K
R14A
4.7R
C9A 10uF,16V
R13 1K
R12 8.2K
R11 ***R10 2.2K
R4A
100K
R2B 120R
R3B
1K
R4B
100K
R3A
1K
C3A 2.2nF,50V
D2A
RF071M2STR
R18A
4.7R
D2B
RF071M2STR
R18B
4.7R
R21B
10R,1W
C14B
0.1uF, 63V
C19A
0.1uF,100V
R19A
1R
C19B
0.1uF,100V
R19B
1R
R22
10R
D3
1N4148
R22B
***
Q1A,C
IRF6665/6775M
Q2A,C
IRF6665/6775M
Q2B,D
IRF6665/6775M
Q1B,D
IRF6665/6775M
GND
GND
GND
CSD
GND
D4
1N4148
C5A
10uF, 50V
C5B
10uF, 50V
R24A 2.2K
R24B 2.2K
220uF/10V
C40
220uF/10V
C41
C8
10uF, 16V
R43
470R,1W
R44
470R,1W
C17B
470uF,63V
C17A
470uF,63V
C17C
0.1uF,100V
C17D
0.1uF,100V
R23B
100k
R23A
100k
C32
100uF, 25V
R31
10k
DS1
R40 10k
R37
100R,1W
Z1
12V
R36
100R,1W
Q3
MMBT5551
Q4
MMBT55 51
R54
10k
R55
47k
R53
10k
R57
47k
R50
47k
R58
47k
Z3
***
Z4
24V
OVPUVP
+B
GND
-B
R46
10k
1
2
P3
1
2
3P1+B
GND
-B
CH2 OUTPUT
CH1 OUTPUT
GND
GND
-5v
+5v
C12A
220pF
VSS
VAA
-B
R22A
***
SD
R56
47k
CH2
CH1
C12B
220pF
Q8 MJD44H11T4G
Q9
MJD4 5H1 1T4 G
R45
10k
Z5
5.6V
Z6
5.6V
GND
GND
R62
10k
For EMI
C62
0.01uF, 50V
R12A
N/A
R12B
N/A
DSB
R26B 10 K
R30A
15K
R31A 10K
R31B
10K
R47
470R,1W
GND
GND
L1A
22uH
L1B
22uH
C10A
22uF,16V
C10B
22uF,16V
R27A
3.3K
R14
10R
C9
4.7uF,10V
DSA
R26A
10K
GND
RpA 90 C
R15
10R
C10
4.7uF,10V
R30B
15K
C16A
0.01uF
R32A 10R
FAULT3OTW2NC
1
NC
48
GND
41
IN2
40
NC
37
COMP2
39
VAA
43
X1B
5
NC
27
COM
30
NC
36
COMP1
45
CSH1
16
LO1
17
HO2
23
VS2
26
X2A
8
NC
28
DT
32
CSD
47
VB2
22
NC
35
VREF
34
VB1
15
CSH2
21
NC
24
NC
25
LO2
20
VCC2
18
X1A
6
VCC
31
XSL9NC
10
CKO
4
VS111NC
12
NC
13
HO1
14
OTP
29
OCSET
33
IN1
44
CLIP1
46
X2B
7
COM2
19
CLIP2
38
VSS
42
-B
0
IC1
IRS2052M
DS2
R105
10K
VAA
DS3
R104
10K
VAA
R511KR52
1K
1 2
Y1
XTAL
1 2
Y2
XTAL
330pF
C11
330pF
C12
330pF
C13
330pF
C14
VAAVSS
-B
1OUT
1
1IN-
2
1IN+
3
VDD
8
2IN+
5
2IN-
6
2OUT
7
GND
4
IC3
NE5532AN
1
2
3
4
CN1
R27B
3.3K
C8A
470pF
C8B
470pF
GND
R48
470R,1W
10uF,50V
C0A
10uF,50V
C0B
R0A
100K
R0B
100K
R71B
10K
R71A
10K
DS5
DS4
1
2
P2
S1
3way SW
Q1
MJD44H 11T4G
R106 1k
R107
3.9K
N/A
C15
R39
100R,1W
R38
100R,1W
R41 10k
S2
R108
3.9K
200R
VR1A
200R
VR1B
IRF6665 Version
IRF6775M Version
D1A, D1B
1N4148
RF071M2
Q1A, Q1B, Q1A, Q1B
Q1C, Q1D, Q2C, Q2D
R11
8.2k
5.6k
R15A, R15B
10k
5.6k
R22A, R 22B
22k
33k
Z3
39V
51V
D1C, D1D
Fig 22 IRAUDAMP10 Schematic
Schematic
Page 27
IRAUDAMP10 Fabrication Materials
Table 1 IRAUDAMP10 Electrical Bill of Materials
Quantity Value Description Designator Part Number Vender
6. Solder Mask to be Green enamel EMP110 DBG (CARAPACE) or Enthone Endplate
DSR-3241or equivalent.
7. Silk Screen to be white epoxy non conductive per IPC–RB 276 Standard.
8. All exposed copper must finished with TIN-LEAD Sn 60 or 63 for 100u inches thick.
9. Tolerance of PCB size shall be 0.010 –0.000 inches
10. Tolerance of all Holes is -.000 + 0.003”
11. PCB acceptance criteria as defined for class II PCB’S standards.
Gerber Files Apertures Description:
All Gerber files stored in the attached CD-ROM were generated from Protel Altium Designer
Altium Designer 6. Each file name extension means the following:
1. .gtl Top copper, top side
2. .gbl Bottom copper, bottom side
3. .gto Top silk screen
4. .gbo Bottom silk screen
5. .gts Top Solder Mask
6. .gbs Bottom Solder Mask
7. .gko Keep Out,
8. .gm1 Mechanical1
9. .gd1 Drill Drawing
10. .gg1 Drill locations
11. .txt CNC data
12. .apr Apertures data
Additional files for assembly that may not be related with Gerber files:
13. .pcb PCB file
14. .bom Bill of materials
15. .cpl Components locations
16. .sch Schematic
17. .csv Pick and Place Components
18. .net Net List
19. .bak Back up files
20. .lib PCB libraries
www.irf.com Page 31 of 34
IRAUDAMP10 REV 1.1
Page 32
Fig 27 IRAUDAMP10 PCB Top Overlay (Top View)
www.irf.com Page 32 of 34
IRAUDAMP10 REV 1.1
Page 33
Fig 28 IRAUDAMP10 PCB Bottom Layer (Top View)
www.irf.com Page 33 of 34
IRAUDAMP10 REV 1.1
Page 34
Revision changes descriptions
Revision Changes description Date
Rev 1.0 Released March, 29 2011
Rev 1.1 Correct polarity of XSL pin function in
Internal Clock Oscillator
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 01/29/2009
Jan, 25 2012
www.irf.com Page 34 of 34
IRAUDAMP10 REV 1.1
Page 35
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
International Rectifier: IRAUDAMP10
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