Inter-m GEQ-1231D, GEQ-2231D Service Manual

www.inter-m.com

MADE IN KOREA

2003.2 9017100300

SERVICE

MANUAL

STEREO/DUAL 31-BAND GRAPHIC

EQUALIZER

GEQ-1231D/2231D

MICOM DATA

MM74HC4051 8-CHANNEL ANALOG MULTIPLEXER

GENERAL DESCRIPTION

The MM74HC4051, MM74HC4052 and MM74HC4053 Multiplexers are digitally controlled analog switches implemented in advanced silicon-gate CMOS technology. These switches have low “on” resistance and low “off” leakages. They are bidirectional switches, thus any analog input may be used as an output and vice-versa. Also These switches contain linearization circuity which lowers the on resistance and increases switch linearity. These devices allow control of up to ± 6V(peak) analog signals with digital control signals of 0 to 6V. Three supply pins are provided for VCC, ground, and VEE. This enables the connection of 0-5V

logic signals when V

= 5V and an analog input range of ± 5V when VEE= 5V. All three devices also have

an inhibit control which when HIGH will disable all switches to their off state. All analog inputs and outputs and digital inputs are protected from electrostatic damage by diodes to V

and ground.

This device connects together the outputs of 8 switches, thus achieving an 8 channel multiplexer. The binary code placed on the A, B, and C select lines determines which one of the eight switches is “on”, and connects one of the eight inputs to the common output.

FEATURES

• Wide analog input voltage range: ±6V

• Low

on resistance: 50 typ.(VCC-V

= 4.5V), 30 typ.(VCC-V

= 9V)

• Logic level translation to enable 5V logic with ± 5V analog signals

• Low quiescent current: 80µA maximum (74HC)

• Matched Switch characteristic

ORDERING CODE:

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Order Number

Package Number

Package Description

MM74HC4051M M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012,0.150˝ Narrow MM74HC4051WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013,0.300˝ Wide MM74HC4051SJ M16D 16-Lead Small Outline Package (SOP), ELAJ TYPE ll, 5.3mm Wide

MM74HC4051MTC MTC16

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,4.4mm Wide MM74HC4051N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-0010.300˝ Wide

Micom Data 1 ~ 21 Specifications

22 Electrical Parts List 23 ~ 24 Top and Bottom View of P.C. Board

25 ~ 29 Wiring Diagram 30 Block Diagram 31~ 32 Schematic Diagram

33 ~ 50 Exploded View of Cabinet & Chassis / Mechanical Parts List

51 ~ 54 Ass’y Drawing 55 ~ 58

CONTENTS

PHYSICAL DIMENSIONS inches (millimeters) unless otherwise noted

TRUTH TABLES

LOGIC DIAGRAMS

CONNECTION DIAGRAMS (Pin Assignments for DIP, SOIC, SOP and TSSO)

Input

Inh C B A

“ON”

Channel

H L L L L L L L L

X L L L L H H H H

X L L H H L L H H

X L H L H L H L H

None

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

Top V iew

PIN CONFIGURATION

LOGIC SYMBOL (IEEE/IEC)

PIN DESCRIPTION

Pin Number Symbol Function

1, 2 Dsa, D

Date inputs

3, 4, 5, 6 Q

to Q

Outputs 10, 11, 12, 13 7 GND Ground(ov) 8 CP Clock input (LOW-to-HIGH, edge-trig-gered) 9 MR Master reset input (active LOW) 14 V

Positive supply voltage

SV00381

LOGIC SYMBOL

FUNCTIONAL DIAGRAM

SV00382 SV00383

SV00384

NOTES 1: CPDis used to determine the dynamic power dissipation (PDin µW)

PD= CPD x V

x fi + ∑(CL x V

x fO) where: fi= input frequency in MHz; CL= output load capacitance in pF; fO= output frequency in MHz; VCC= supply voltage in V; ∑(C

x V

x fO) = sum of the outputs.

2: The condition is V

= GND to V

Symbol Parameter Conditions Typical Unit

PHL

, t

PLH

Propagation delay CL=15pF 12 ns CP to Q

VCC=3.3V 12

MR to Q

max

Maximum clock frequency 78 MH

Input capacitance 3.5 pF

Power dissipation capacitance per gate VCC=3.3V 40 pF

Notes 1 and 2

ORDERING INFORMATION

Packages Temperature Range Outside North Amerlca North Amerlca Pkg. Dwg.#

14-Pin Plastic DIL

-40°C to + 125°C 74LV164N 74LV164N SOT27-1

14-Pin Plastic SO

-40°C to + 125°C 74LV164D 74LV164D SOT108-1

14-Pin Plastic SSOP Type II

-40°C to + 125°C 74LV164DB 74LV164DB SOT337-1

14-Pin Plastic TSSOP Type I

-40°C to + 125°C 74LV164PW 74LV164PW DH SOT402-1

74LV164 8-bit SERIAL-IN / PARALLEL-OUT SHIFT REGISTER

FEATURES

–Wide operating voltage: 1.0 to 5.5V – Optimized for Low Voltage applications: 1.0 to 3.6V – Accepts TTL input levels between VCC=2.7V and VCC=3.6V

–Typical V

OLP

(output ground bounce) < 0.8V@VCC=3.3V, T

amb

=25°C

–Typical V

OHV

(output VOHundershoot) > 2V@VCC=3.3V,T

amb

=25°C

– Gated serial data inputs – Asynchronous master reset – Output capability: standard – I

category: MSl

DESCRIPTION

The 74LV164 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT164.

The 74LV164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs(Dsaor Dsb); either input can be used as an

active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock (CP) input and enters into Q

which is the logical AND of the two data inputs (D

, Dsb) that existed one set-up time prior to the rising clock edge.

A LOW on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.

QUICK REFERENCE DATA

GND = OV; T

amb

= 25°C; tr=t

≤ 2.5ns

GENERAL DESCRIPTION

The AD7819 is a high speed, microprocessor-compatible, 8-bit analog-to-digital converter with a maximum throughput of 200kSPS. The converter operates off a single 2.7V to 5.5V supply and contains a 4.5µs successive approximation A/D converter, track/hold circuitry, on-chip clock oscillator and 8-bit wide parallel interface. The parallel interface is designed to allow easy interfacing to microprocessors and DSPs. Using only address decoding logic the AD7819 is easily mapped into the microprocessor address space.

When used in its power-down mode, the AD7819 automatically powers down at the end of a conversion and powers up at the start of a new conversion. This feature significantly reduces the power consumption of the part at lower throughput rates. The AD7819 can also operate in a high speed mode where the part is not powered down between conversions. In this mode of operation the part is capable of providing 200 kSPS throughput.

The part is available in a small, 16-lead 0.3" wide, plastic dual-in-line package (DIP); in a 6-lead, 0.15" wide, narrow body small outline IC (SOIC) and in a 16-lead, narrow body, thin shrink small outline package (TSSOP).

AD7819 2.7V to 5.5V, 200 kSPS 8-bit SAMPLING ADC

FEATURES

– 8-Bit ADC with 4.5 µs Conversion Time – On-Chip Track and Hold – Operating Supply Range : 2.7V to 5.5V – Specifications at 2.7V-3.6V and 5V ± 10% – 8-Bit Parallel Interface : 8-Bit Read – Power Performance

Normal Operation : 10.5mW,VDD=3V

– Automatic Power-Down : 57.75µW@1kSPS,V

=3V

– Analog Input Range : 0V to V

REF

– Reference Input Range : 1.2V to V

FUNCTIONAL BLOCK DIAGRAM

SO14 : plastic small outline package; 14 leads; body width 3.9 mm

NOTE : Plastic or metal protrusions of 0.15 mm maximum per side are not included.

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Unit

max.

A1A2A3bpcD

(1)E(1)

eHELLPQvwyz

(1)

European Projection

Issue Date

SOT108-1 076E06S MS-012AB

91-08-13 95-01-23

inches

1.75

0.069

0.25

0.10

0.0098

0.0039

0.49

0.36

0.019

0.014

4.0

3.8

0.16

0.15

6.2

5.8

0.24

0.23

1.05

0.041

0.25

0.01

0.25

0.01

0.1

0.004

8° 0°

0.7

0.3

0.028

0.012

1.0

0.4

0.039

0.016

0.7

0.6

0.028

0.024

1.27

0.050

8.75

8.55

0.35

0.34

0.25

0.19

0.0098

0.0075

1.45

1.25

0.057

0.049

0.25

0.01

Outline Version

Iec Jedec Eiaj

References

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charge as high as 4000V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7819 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges, Therefore, proper ESD precaution are recommended to avoid performance degradation or loss of functionality.

PIN FUNCTION DESCRIPTION

Pin No. Mnemonic Description

REF

Reference Input, 1.2V to VDD.

Analog Input, 0V to V

REF

. 3 GND Analog and Digital Ground. 4 CONVST Convert Start. A low-to-high transition on this pin initiates a 1.5

s pulse on an internally generated CONVST signal. A high-to-low transition on this line initiates the conversion process if the internal CONVST signal is low. Depending on the signal on this pin at the end of a conversion, the AD7819 automatically powers down.

5CS Chip Select. This is a logic input. CS is used in conjunction with RD to enable outputs. 6RD Read Pin. This is a logic input. When CS is low and RD goes low, the DB7-DB0 leave

their high impedance state and data is driven onto the data bus.

7 BUSY ADC Bus y Sig nal. T his i s a lo gic output. This signal goes logic high during the

conversion process.

8-15 DB0-DB7 Data Bit 0 to 7. These outputs are three-state TTL-compatible.

16 V

Positive power supply voltage, 2.7V to 5.5V.

PIN CONFIGURATION DIP/SOIC

*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only;

functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ORDERING GUIDE

Model Linearity Error(LSB) Package Description Package Option

AD7819YN ± 1 LSB Plastic DIP N-16 AD7819YR ± 1 LSB Small Outline IC R-16A AD7819YRU ± 1 LSB Thin Shark Small RU-16

Outline (TSSOP)

ABSOLUTE MAXIMUM RATINGS*

VDDto DGND ..............................................................................................................................-0.3V to + 7V

Digital Input Voltage to DGND

(CONVST, RD, CS)...............................................................................................................-0.3V, V

+ 0.3V

Digital Output Voltage to DGND

(BUSY, DB0-DB7) .................................................................................................................-0.3V, V

+ 0.3V

REF

to AGND......................................................................................................................-0.3V, VDD+ 0.3V

Analog Input ..........................................................................................................................-0.3V, V

+ 0.3V

Storage Temperature Range.................................................................................................-65

to + 150°C

Junction Temperature ........................................................................................................................... 150°C

Plastic DIP Package, Power Dissipation .............................................................................................450mW

Thermal Impedance...................................................................................................................105°C/W

Lead Temperature, (Soldering 10 sec)................................................................................................260°C

SOIC Package, Power Dissipation ......................................................................................................450mW

Thermal Impedance .....................................................................................................................75°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) ....................................................................................................................215°C

Infrared (15 sec)............................................................................................................................220°C

SSOP Package, Power Dissipation.....................................................................................................450mW

Thermal Impedance ...................................................................................................................115°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) ....................................................................................................................215°C

Infrared (15 sec).............................................................................................................................220°C

Figure 1. Load Circuit for Digital Output Timing Specifications

1110

BLOCK DIAGRAM

AK4524 24 bit 96kHz AUDIO CODEC

GENERAL DESCRIPTION

The AK4524 is a high performance 24bit CODEC for the 96kHz recording system. The ADC has an Enhanced Dual Bit architecture with wide dynamic range. The DAC uses the new developed Advanced Multi Bit architecture and achieves low outband noise and high jitter tolerance by use of SCF(switched capacitor filter) techniques.The AK4524 has an input PGA and is well suited MD, DVTR system and musical instruments.

FEATURES

• 24bit 2ch ADC

– 64x Oversampling – Single-End inputs – S/(N+D):90dB – Dynamic Range, S/N:100dB – Digital HPF for offset cancellation – Input PGA with +8dB gain & 0.5dB step – Input DATT with -72dB att – I/F format:MSB justified or I2S

• 24bit 2ch DAC

– 128 x Oversampling – 24bit 8 times Digital Filter

Ripple:±0.005dB, Attenuation:75dB – SCF – Differential Outputs – S/(N+D):94dB – Dynamic Range, S/N:110dB – De-emphasis for 32kHz, 44.1kHz, 48kHz sampling – Output DATT with -72dB att – Soft Mute – I/F format:MSB justified, LSB justified or l

• High Jitter Tolerance

• 3-wire Serial Interface for Volume Control

• Master Clock

– X’tal Oscillating Circuit – 256fs/384fs/768fs/1024fs

• Master Mode/Slave Mode

• 5V operation

• 3V Power Supply Pin for 3V I/F

• Small 28pin VSOP package

PIN LAYOUT

ORDERING GUIDE

AK4524VF -10~+70°C 28pin VSOP (0.65mm pitch) AKD4524 Evaluation Board

1312

PACKAGE & LEAD FRAME MATERIAl

Package molding compound: Epoxy Lead frame material: Cu Lead frame surface treatment: Solder plate

PACKAGZ

Note : Dimension

“*” does not include moid flash.

ADSP-21065L DSP MICROCOMPUTER

SUMMARY

– High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and

Industrial Applications

– Super Harvard Architecture Computer (SHARC®)

Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle –32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-Point Arithmetic – 544 Kbits On-Chip SRAM Memory and Integrated I/O Peripheral –I

S Support, for Eight Simultaneous Receive and Transmit Channels

KEY FEATURES

– 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Performance – User-Configurable 544 Kbits On-Chip SRAM Memory –Two External Port, DMA Channels and Eight Serial Port, DMA Channels – SDRAM Controller for Glueless Interface to Low Cost External Memory (@66 MHz) – 64M Words External Address Range –12 Programmable I/O Pins and Two Timers with Event Capture Options – Code-Compatible with ADSP-2106x Family – 208-Lead MQFP or 196-Ball Mini-BGA Package – 3.3 Volt Operation

Flexible Data Formats and 40-Bit Extended Precision

– 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats –32-Bit Fixed-Point Data Format, Integer and Fractional, with Dual 80-Bit Accumulators

Parallel Computations

– Single-Cycle Multiply and ALU Operations in Parallel with Dual Memory Read/Writes and Instruction

Fetch – Multiply with Add and Subtract for Accelerated FFT Butterfly Computation – 1024-Point Complex FFT Benchmark: 0.274 ms (18,221 Cycles)

544 Kbits Configurable On-Chip SRAM

– Dual-Ported for Independent Access by Core Processor and DMA – Configurable in Combinations of 16-, 32-, 48-Bit Data and Program Words in Block 0 and Block 1

DMA Controller

–Ten DMA Channels–Two Dedicated to the External Port and Eight Dedicated to the Serial Ports – Background DMA Transfers at up to 66 MHz, in Parallel with Full Speed Processor Execution – Performs Transfers Between:

Internal RAM and Host

Internal RAM and Serial Ports

Internal RAM and Master or Slave SHARC

Internal RAM and External Memory or I/O Devices

External Memory and External Devices

Host Processor Interface

–Efficient Interface to 8-, 16-, and 32-Bit Microprocessors – Host Can Directly Read/Write ADSP-21065L IOP Registers

1514

Multiprocessing

– Distributed On-Chip Bus Arbitration for Glueless, Parallel Bus Connect Between Two ADSP-21065Ls

Plus Host

– 132 Mbytes/s Transfer Rate Over Parallel Bus

Serial Ports

– Independent Transmit and Receive Functions –Programmable 3-Bit to 32-Bit Serial Word Width –I2S Support Allowing Eight Transmit and Eight Receive Channels – Glueless Interface to Industry Standard Codecs –TDM Multichannel Mode with µ-Law/A-Law Hardware Companding – Multichannel Signaling Protocol

BLOCK DIAGRAM

PIN DESCRIPTIONS

ADSP-21065L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN (or to TCK for TRST). Unused inputs should be tied or pulled to VDD or GND, except for ADDR

23-0

, DATA

31-0

, FLAG

11-0

, SW, and inputs that have internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI)–these pins can be left floating. These pins have a logic-level hold circuit that prevents the input from floating internally. I=Input S=Synchronous P=Power Supply (O/D)=Open Drain O=Output A=Asynchronous G=Ground (A/D)=Active Drive T=Three-state (when SBTS is asserted, or when the ADSP-2106x is a bus slave)

Pin Type Function

ADDR

23-0

I/O/T External Bus Address. The ADSP-21065L outputs addresses for external

memory and peripherals on these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the IOP registers of the other ADSP-21065L. The ADSP-21065L inputs addresses when a host processor or multiprocessing bus master is reading or writing its IOP registers.

DATA

31-0

I/O/T External Bus Data. The ADSP-21065L inputs and outputs data and

instructions on these pins. The external data bus transfers 32-bit singleprecision floating-point data and 32-bit fixed-point data over bits 31-0. 16-bit short word data is transferred over bits 15-0 of the bus. Pull-up resistors on unused DATA pins are not necessary.

3-0

I/O/T Memory Select Lines. These lines are asserted as chip selects for the

corresponding banks of external memory. Internal ADDR

25-24

are decoded

into MS

3-0

. The MS

3-0

lines are decoded memory address lines that change at the same time as the other address lines. When no external memory access is occurring the MS

3-0

lines are inactive; they are active, however, when a conditional memory access instruction is executed, whether or not the condition is true. Additionally, an MS

3-0

line which is mapped to SDRAM may be asserted even when no SDRAM access is active. In a multiprocessor system, the MS

3-0

lines are output by the bus master.

RD I/O/T Memory Read Strobe. This pin is asserted when the ADSP-21065L reads

from external memory devices or from the IOP register of another ADSP21065L. External devices (including another ADSP-21065L) must assert RD to read from the ADSP-21065L’s IOP registers. In a multiprocessor system, RD is output by the bus master and is input by another ADSP-21065L.

WR I/O/T Memory Write Strobe. This pin is asserted when the ADSP-21065L writes

to external memory devices or to the IOP register of another ADSP-21065L. External devices must assert WR to write to the ADSP-21065L’s IOP registers. In a multiprocessor system, WR is output by the bus master and is input by the other ADSP-21065L.

SW I/O/T Synchronous Write Select. This signal interfaces the ADSP-21065L to

synchronous memory devices (including another ADSP-21065L). The ADSP-21065L asserts SW to provide an early indication of an impending write cycle, which can be aborted if WR is not later asserted (e.g., in a conditional write instruction). In a multiprocessor system, SW is output by the bus master and is input by the other ADSP-21065L to determine if the multiprocessor access is a read or write. SW is asserted at the same time as the address output.

ACK I/O/S Memory Acknowledge. External devices can deassert ACK to add wait

states to an external memory access. ACK is used by I/O devices, memory controllers, or other peripherals to hold off completion of an external memory

1716

Pin Type Function

access. The ADSP-21065L deasserts ACK as an output to add wait states to a synchronous access of its IOP registers. In a multiprocessor system, a slave ADSP-21065L deasserts the bus master’s ACK input to add wait state(s) to an access of its IOP registers. The bus master has a keeper latch on its ACK pin that maintains the input at the level to which it was last driven.

SBTS I/S Suspend Bus Three-State. External devices can assert SBTS to place the

external bus address, data, selects, and strobes–but not SDRAM control pins–in a high impedance state for the following cycle. If the ADSP-21065L attempts to access external memory while SBTS is asserted, the processor will halt and the memory access will not finish until SBTS is deasserted. SBTS should only be used to recover from host processor/ADSP-21065L deadlock.

IRQ

2-0

I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.

FLAG

11-0

I/O/A Flag Pins. Each is configured via control bits as either an input or an output.

As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals.

HBR I/A Host Bus Request. Must be asserted by a host processor to request control

of the ADSP-21065L’s external bus. When HBR is asserted in a multiprocessing system, the ADSP-21065L that is bus master will relinquish the bus and assert HBG. To relinquish the bus, the ADSP-21065L places the address, data, select, and strobe lines in a high impedance state. It does, however, continue to drive the SDRAM control pins. HBR has priority over all ADSP-21065L bus requests (BR

2-1

) in a multiprocessor system.

HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the

host processor may take control of the external bus. HBG is asserted by the ADSP-21065L until HBR is released. In a multiprocessor system, HBG is output by the ADSP-21065L bus master.

CS I/A Chip Select. Asserted by host processor to select the ADSP-21065L.

REDY(O/D)

O Host Bus Acknowledge. The ADSP-21065L deasserts REDY to add wait

states to an asynchronous access of its internal memory or IOP registers by a host. Open drain output (O/D) by default; can be programmed in ADREDY bit of SYSCON register to be active drive (A/D). REDY will only be output if the CS and HBR inputs are asserted.

DMAR

I/A DMA Request 1 (DMA Channel 9).

DMAR

I/A DMA Request 2 (DMA Channel 8).

DMAG

O/T DMA Grant 1 (DMA Channel 9).

DMAG

O/T DMA Grant 2 (DMA Channel 8).

2-1

I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21065L’s

to arbitrate for bus mastership. An ADSP-21065L drives its own BRx line (corresponding to the value of its ID

2-0

inputs) only and monitors all others. In

a uniprocessor system, tie both BRx pins to VDD.

1-0

I Multiprocessing ID. Determines which multiprocessor bus request

(BR

–BR2) is used by ADSP-21065L. ID=01 corresponds to BR1, ID=10

corresponds to BR

. ID=00 in single-processor systems. These lines are a system configuration selection which should be hard-wired or changed only at reset.

CPA (O/D) I/O Core Priority Access. Asserting its CPA pin allows the core processor of an

ADSP-21065L bus slave to interrupt background DMA transfers and gain

Pin Type Function

SBTS I/S Suspend Bus Three-State. External devices can assert SBTS to place the

IRQ

2-0

I/A Interrupt Request Lines. May be either edge-triggered or level-sensitive.

FLAG

11-0

I/O/A Flag Pins. Each is configured via control bits as either an input or an output.

As an input, it can be tested as a condition. As an output, it can be used to signal external peripherals.

HBR I/A Host Bus Request. Must be asserted by a host processor to request control

2-1

) in a multiprocessor system.

HBG I/O Host Bus Grant. Acknowledges an HBR bus request, indicating that the

host processor may take control of the external bus. HBG is asserted by the ADSP-21065L until HBR is released. In a multiprocessor system, HBG is output by the ADSP-21065L bus master.

CS I/A Chip Select. Asserted by host processor to select the ADSP-21065L.

REDY(O/D)

O Host Bus Acknowledge. The ADSP-21065L deasserts REDY to add wait

DMAR

I/A DMA Request 1 (DMA Channel 9).

DMAR

I/A DMA Request 2 (DMA Channel 8).

DMAG

O/T DMA Grant 1 (DMA Channel 9).

DMAG

O/T DMA Grant 2 (DMA Channel 8).

2-1

I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21065L’s

to arbitrate for bus mastership. An ADSP-21065L drives its own BRx line (corresponding to the value of its ID

2-0

inputs) only and monitors all others. In

a uniprocessor system, tie both BRx pins to VDD.

1-0

I Multiprocessing ID. Determines which multiprocessor bus request

(BR

–BR2) is used by ADSP-21065L. ID=01 corresponds to BR1, ID=10

corresponds to BR

. ID=00 in single-processor systems. These lines are a system configuration selection which should be hard-wired or changed only at reset.

CPA (O/D) I/O Core Priority Access. Asserting its CPA pin allows the core processor of an

ADSP-21065L bus slave to interrupt background DMA transfers and gain

+ 22 hidden pages

Inter-m GEQ-1231D, GEQ-2231D Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual