Intel Corporation TSB80C196KC20, TSB80C196KC, TS87C196KC20, TS87C196KC Datasheet
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changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
November 1994COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 270942-005
8XC196KC/8XC196KC20
COMMERCIAL/EXPRESS CHMOS
MICROCONTROLLER
87C196KCÐ16 Kbytes of On-Chip OTPROM
83C196KCÐ16 Kbytes ROM
80C196KCÐROMless
Y
16 and 20 MHz Available
Y
488 Byte Register RAM
Y
Register-to-Register Architecture
Y
28 Interrupt Sources/16 Vectors
Y
Peripheral Transaction Server
Y
1.4 ms 16 x 16 Multiply (20 MHz)
Y
2.4 ms 32/16 Divide (20 MHz)
Y
Powerdown and Idle Modes
Y
Five 8-Bit I/O Ports
Y
16-Bit Watchdog Timer
Y
Extended Temperature Available
Y
Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y
Full Duplex Serial Port
Y
High Speed I/O Subsystem
Y
16-Bit Timer
Y
16-Bit Up/Down Counter with Capture
Y
3 Pulse-Width-Modulated Outputs
Y
Four 16-Bit Software Timers
Y
8- or 10-Bit A/D Converter with
Sample/Hold
Y
HOLD/HLDA Bus Protocol
Y
OTPROM One-Time Programmable
Version
The 80C196KC 16-bit microcontroller is a high performance member of the MCSÉ96 microcontroller family.
The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 and 20 MHz operation and an
optional 16 Kbytes of ROM/OTPROM. Intel’s CHMOS III process provides a high performance processor
along with low power consumption.
The 87C196KC is an 80C196KC with 16 Kbytes on-chip OTPROM. The 83C196KC is an 80C196KC with 16
Kbytes factory programmed ROM. In this document, the 80C196KC will refer to all products unless otherwise
stated.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of 0
§
Ctoa70§C. With the extended (Express) temperature range option, operational charac-
teristics are guaranteed over the temperature range of
b
40§Ctoa85§C. Unless otherwise noted, the specifi-
cations are the same for both options.
See the Packaging information for extended temperature designators.
8XC196KC/8XC196KC20
270942– 1
Figure 1. 8XC196KC Block Diagram
IOC3 (0CH HWIN1 READ/WRITE)
270942– 45
NOTE:
*RSVÐReserved bits must be
e
0
Figure 2. 8XC196KC New SFR Bit (CLKOUT Disable)
2
8XC196KC/8XC196KC20
PROCESS INFORMATION
This device is manufactured on PX29.5 or PX29.9, a
CHMOS III process. Additional process and reliability information is available in Intel’s
Components
Quality and Reliability Handbook,
Order Number
210997.
270942– 43
EXAMPLE: N87C196KC is 68-Lead PLCC OTPROM,
16 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 3. The 8XC196KC Family Nomenclature
Table 1. Thermal Characteristics
Package
i
ja
i
jc
Type
PLCC 35§C/W 13§C/W
QFP 55§C/W 16§C/W
SQFP TBD TBD
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel
Packaging Handbook
(order number 240800) for a
description of Intel’s thermal impedance test methodology.
Table 2. 8XC196KC Memory Map
Description Address
External Memory or I/O 0FFFFH
06000H
Internal ROM/OTPROM or External 5FFFH
Memory (Determined by EA
)
2080H
Reserved. Must contain FFH. 207FH
(Note 5)
205EH
PTS Vectors 205DH
2040H
Upper Interrupt Vectors 203FH
2030H
ROM/OTPROM Security Key 202FH
2020H
Reserved. Must contain FFH. 201FH
(Note 5)
201AH
Reserved. Must Contain 20H 2019H
(Note 5)
CCB 2018H
Reserved. Must contain FFH. 2017H
(Note 5)
2014H
Lower Interrupt Vectors 2013H
2000H
Port 3 and Port 4 1FFFH
1FFEH
External Memory 1FFDH
0200H
488 Bytes Register RAM (Note 1) 01FFH
0018H
CPU SFR’s (Notes 1, 3, 4) 0017H
0000H
NOTES:
1. Code executed in locations 0000H to 01FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KC User’s manual for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these locations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
8XC196KC/8XC196KC20
270942– 2
Figure 4. 68-Lead PLCC Package
4
8XC196KC/8XC196KC20
270942– 40
Figure 5. S8XC196KC 80-Pin QFP Package
5
8XC196KC/8XC196KC20
270942– 44
Figure 6. 80-Pin SQFP Package
6
8XC196KC/8XC196KC20
PIN DESCRIPTIONS
Symbol Name and Function
V
CC
Main supply voltage (5V).
V
SS
Digital circuit ground (0V). There are multiple VSSpins, all of which must be connected.
V
REF
Reference voltage for the A/D converter (5V). V
REF
is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.
ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as
V
SS
.
V
PP
Timing pin for the return from powerdown circuit. This pin also supplies the programming
voltage on the EPROM device.
XTAL1 Input of the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter.
CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator
frequency.
RESET Reset input and open drain output.
BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH isa0an
8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI A positive transition causes a vector through 203EH.
INST Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.
EA Input for memory select (External Access). EA equal high causes memory accesses to
locations 2000H through 5FFFH to be directed to on-chip ROM/EPROM. EA
equal to low
causes accesses to those locations to be directed to off-chip memory. Also used to enter
programming mode.
ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV
, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during
external memory accesses.
RD Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL
will go low only for external writes where an even byte is
being written. WR
/WRL is activated only during external memory writes.
BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will
go low for external writes to the high byte of the data bus. WRH
will go low for external
writes where an odd byte is being written. BHE
/WRH is activated only during external
memory writes.
READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. When the external memory is not being used, READY has no effect.
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
Port 1 8-bit quasi-bidirectional I/O port.
Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KC.
Pins 2.6 and 2.7 are quasi-bidirectional.
7
8XC196KC/8XC196KC20
PIN DESCRIPTIONS (Continued)
Symbol Name and Function
Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
HOLD Bus Hold input requesting control of the bus.
HLDA Bus Hold acknowledge output indicating release of the bus.
BREQ Bus Request output activated when the bus controller has a pending external memory
cycle.
PMODE Determines the EPROM programming mode.
PACT A low signal in Auto Programming mode indicates that programming is in process. A high
signal indicates programming is complete.
CPVER Cummulative Program Output Verification. Pin is high if all locations have programmed
correctly since entering a programming mode.
PALE A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode
indicates that ports 3 and 4 contain valid programming address/command information
(input to slave).
PROG A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid
programming data (input to slave).
PVER A high signal in Slave Programmig Mode and Auto Configuration Byte Programming Mode
indicates the byte programmed correctly.
AINC Auto Increment. Active low input signal indicates that the auto increment mode is enabled.
Auto Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
8
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