*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
November 1994COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 270942-005
8XC196KC/8XC196KC20
COMMERCIAL/EXPRESS CHMOS
MICROCONTROLLER
87C196KCÐ16 Kbytes of On-Chip OTPROM
83C196KCÐ16 Kbytes ROM
80C196KCÐROMless
Y
16 and 20 MHz Available
Y
488 Byte Register RAM
Y
Register-to-Register Architecture
Y
28 Interrupt Sources/16 Vectors
Y
Peripheral Transaction Server
Y
1.4 ms 16 x 16 Multiply (20 MHz)
Y
2.4 ms 32/16 Divide (20 MHz)
Y
Powerdown and Idle Modes
Y
Five 8-Bit I/O Ports
Y
16-Bit Watchdog Timer
Y
Extended Temperature Available
Y
Dynamically Configurable 8-Bit or
16-Bit Buswidth
Y
Full Duplex Serial Port
Y
High Speed I/O Subsystem
Y
16-Bit Timer
Y
16-Bit Up/Down Counter with Capture
Y
3 Pulse-Width-Modulated Outputs
Y
Four 16-Bit Software Timers
Y
8- or 10-Bit A/D Converter with
Sample/Hold
Y
HOLD/HLDA Bus Protocol
Y
OTPROM One-Time Programmable
Version
The 80C196KC 16-bit microcontroller is a high performance member of the MCSÉ96 microcontroller family.
The 80C196KC is an enhanced 80C196KB device with 488 bytes RAM, 16 and 20 MHz operation and an
optional 16 Kbytes of ROM/OTPROM. Intel’s CHMOS III process provides a high performance processor
along with low power consumption.
The 87C196KC is an 80C196KC with 16 Kbytes on-chip OTPROM. The 83C196KC is an 80C196KC with 16
Kbytes factory programmed ROM. In this document, the 80C196KC will refer to all products unless otherwise
stated.
Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.
With the commercial (standard) temperature option, operational characteristics are guaranteed over the temperature range of 0
§
Ctoa70§C. With the extended (Express) temperature range option, operational charac-
teristics are guaranteed over the temperature range of
b
40§Ctoa85§C. Unless otherwise noted, the specifi-
cations are the same for both options.
See the Packaging information for extended temperature designators.
8XC196KC/8XC196KC20
270942– 1
Figure 1. 8XC196KC Block Diagram
IOC3 (0CH HWIN1 READ/WRITE)
270942– 45
NOTE:
*RSVÐReserved bits must be
e
0
Figure 2. 8XC196KC New SFR Bit (CLKOUT Disable)
2
8XC196KC/8XC196KC20
PROCESS INFORMATION
This device is manufactured on PX29.5 or PX29.9, a
CHMOS III process. Additional process and reliability information is available in Intel’s
Components
Quality and Reliability Handbook,
Order Number
210997.
270942– 43
EXAMPLE: N87C196KC is 68-Lead PLCC OTPROM,
16 MHz.
For complete package dimensional data, refer to the
Intel Packaging Handbook (Order Number 240800).
NOTE:
1. EPROMs are available as One Time Programmable
(OTPROM) only.
Figure 3. The 8XC196KC Family Nomenclature
Table 1. Thermal Characteristics
Package
i
ja
i
jc
Type
PLCC 35§C/W 13§C/W
QFP 55§C/W 16§C/W
SQFP TBD TBD
All thermal impedance data is approximate for static air
conditions at 1W of power dissipation. Values will change
depending on operation conditions and application. See
the Intel
Packaging Handbook
(order number 240800) for a
description of Intel’s thermal impedance test methodology.
Table 2. 8XC196KC Memory Map
Description Address
External Memory or I/O 0FFFFH
06000H
Internal ROM/OTPROM or External 5FFFH
Memory (Determined by EA
)
2080H
Reserved. Must contain FFH. 207FH
(Note 5)
205EH
PTS Vectors 205DH
2040H
Upper Interrupt Vectors 203FH
2030H
ROM/OTPROM Security Key 202FH
2020H
Reserved. Must contain FFH. 201FH
(Note 5)
201AH
Reserved. Must Contain 20H 2019H
(Note 5)
CCB 2018H
Reserved. Must contain FFH. 2017H
(Note 5)
2014H
Lower Interrupt Vectors 2013H
2000H
Port 3 and Port 4 1FFFH
1FFEH
External Memory 1FFDH
0200H
488 Bytes Register RAM (Note 1) 01FFH
0018H
CPU SFR’s (Notes 1, 3, 4) 0017H
0000H
NOTES:
1. Code executed in locations 0000H to 01FFH will be
forced external.
2. Reserved memory locations must contain 0FFH unless
noted.
3. Reserved SFR bit locations must contain 0.
4. Refer to 8XC196KC User’s manual for SFR descriptions.
5. WARNING: Reserved memory locations must not be
written or read. The contents and/or function of these locations may change with future revisions of the device.
Therefore, a program that relies on one or more of these
locations may not function properly.
3
8XC196KC/8XC196KC20
270942– 2
Figure 4. 68-Lead PLCC Package
4
8XC196KC/8XC196KC20
270942– 40
Figure 5. S8XC196KC 80-Pin QFP Package
5
8XC196KC/8XC196KC20
270942– 44
Figure 6. 80-Pin SQFP Package
6
8XC196KC/8XC196KC20
PIN DESCRIPTIONS
Symbol Name and Function
V
CC
Main supply voltage (5V).
V
SS
Digital circuit ground (0V). There are multiple VSSpins, all of which must be connected.
V
REF
Reference voltage for the A/D converter (5V). V
REF
is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D
and Port 0 to function.
ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as
V
SS
.
V
PP
Timing pin for the return from powerdown circuit. This pin also supplies the programming
voltage on the EPROM device.
XTAL1 Input of the oscillator inverter and of the internal clock generator.
XTAL2 Output of the oscillator inverter.
CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator
frequency.
RESET Reset input and open drain output.
BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus
cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH isa0an
8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus.
NMI A positive transition causes a vector through 203EH.
INST Output high during an external memory read indicates the read is an instruction fetch. INST
is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.
EA Input for memory select (External Access). EA equal high causes memory accesses to
locations 2000H through 5FFFH to be directed to on-chip ROM/EPROM. EA
equal to low
causes accesses to those locations to be directed to off-chip memory. Also used to enter
programming mode.
ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options
provide a signal to demultiplex the address from the address/data bus. When the pin is
ADV
, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during
external memory accesses.
RD Read signal output to external memory. RD is activated only during external memory reads.
WR/WRL Write and Write Low output to external memory, as selected by the CCR. WR will go low for
every external write, while WRL
will go low only for external writes where an even byte is
being written. WR
/WRL is activated only during external memory writes.
BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE will
go low for external writes to the high byte of the data bus. WRH
will go low for external
writes where an odd byte is being written. BHE
/WRH is activated only during external
memory writes.
READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory,
or for bus sharing. When the external memory is not being used, READY has no effect.
HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3.
Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.
HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,
HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.
Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as
analog inputs to the on-chip A/D converter.
Port 1 8-bit quasi-bidirectional I/O port.
Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the 80C196KC.
Pins 2.6 and 2.7 are quasi-bidirectional.
7
8XC196KC/8XC196KC20
PIN DESCRIPTIONS (Continued)
Symbol Name and Function
Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the
multiplexed address/data bus which has strong internal pullups.
HOLD Bus Hold input requesting control of the bus.
HLDA Bus Hold acknowledge output indicating release of the bus.
BREQ Bus Request output activated when the bus controller has a pending external memory
cycle.
PMODE Determines the EPROM programming mode.
PACT A low signal in Auto Programming mode indicates that programming is in process. A high
signal indicates programming is complete.
CPVER Cummulative Program Output Verification. Pin is high if all locations have programmed
correctly since entering a programming mode.
PALE A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode
indicates that ports 3 and 4 contain valid programming address/command information
(input to slave).
PROG A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid
programming data (input to slave).
PVER A high signal in Slave Programmig Mode and Auto Configuration Byte Programming Mode
indicates the byte programmed correctly.
AINC Auto Increment. Active low input signal indicates that the auto increment mode is enabled.
Auto Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write.
8
8XC196KC/8XC196KC20
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature
Under Bias ААААААААААААААААА
b
55§Ctoa125§C
Storage Temperature ААААААААААb65§Ctoa150§C
Voltage On Any Pin to V
SS
ААААААb0.5V toa7.0V
(1)
Voltage from EA or
V
PP
to VSSor ANGNDААААААААААААААААa13.00V
Power Dissipation ААААААААААААААААААААААА1.5W
(2)
NOTE:
1. This includes V
PP
and EA on ROM or CPU only devices.
2. Power dissipation is based on package heat transfer limitations, not device power consumption.
NOTICE: This is a production data sheet. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
*
WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
OPERATING CONDITIONS
Symbol Description Min Max Units
T
A
Ambient Temperature Under Bias Commercial Temp. 0
a
70
§
C
T
A
Ambient Temperature Under Bias Extended Temp.
b
40
a
85
§
C
V
CC
Digital Supply Voltage 4.50 5.50 V
V
REF
Analog Supply Voltage 4.00 5.50 V
ANGND Analog Ground Voltage V
SS
b
0.4 V
SS
a
0.4 V
(1)
F
OSC
Oscillator Frequency (8XC196KC) 8 16 MHz
F
OSC
Oscillator Frequency (8XC196KC20) 8 20 MHz
NOTE:
1. ANGND and V
SS
should be nominally at the same potential.
DC CHARACTERISTICS (Over Specified Operating Conditions)
Symbol Description Min Typ Max Units Test Conditions
V
IL
Input Low Voltage
b
0.5 0.8 V
V
IH
Input High Voltage (Note 1) 0.2 V
CC
a
1.0 V
CC
a
0.5 V
V
IH1
Input High Voltage on XTAL 1 0.7 V
CC
V
CC
a
0.5 V
V
IH2
Input High Voltage on RESET 2.2 V
CC
a
0.5 V
V
HYS
Hysteresis on RESET 300 mV V
CC
e
5.0V
V
OL
Output Low Voltage 0.3 V I
OL
e
200 mA
0.45 V I
OL
e
2.8 mA
1.5 V I
OL
e
7mA
V
OL1
Output Low Voltage
0.8 V
I
OL
ea
0.4 mA
in RESET on P2.5 (Note 2)
V
OH
Output High Voltage V
CC
b
0.3 V I
OH
eb
200 mA
(Standard Outputs) V
CC
b
0.7 V I
OH
eb
3.2 mA
V
CC
b
1.5 V I
OH
eb
7mA
9
8XC196KC/8XC196KC20
DC CHARACTERISTICS (Over Specified Operating Conditions) (Continued)
Symbol Description Min Typ Max Units Test Conditions
V
OH1
Output High Voltage V
CC
b
0.3 V I
OH
eb
10 mA
(Quasi-bidirectional Outputs) V
CC
b
0.7 V I
OH
eb
30 mA
V
CC
b
1.5 V I
OH
eb
60 mA
I
OH1
Logical 1 Output Current in Reset.
b
0.8 mA V
IH
e
V
CC
b
1.5V
on P2.0. Do not exceed this
or device may enter test modes.
I
IL2
Logical 0 Input Current in Reset TBD mA V
IN
e
0.45V
on P2.0. Maximum current that
must be sunk by external
device to ensure test mode entry.
I
IH1
Logical 1 Input Current.
a
200 mAV
IN
e
V
CC
e
2.4V
Maximum current that external
device must source to initiate NMI.
I
LI
Input Leakage Current (Std. Inputs)
g
10 mA0kV
IN
k
V
CC
b
0.3V
I
LI1
Input Leakage Current (Port 0)
g
3 mA0kV
IN
k
V
REF
I
TL
1 to 0 Transition Current (QBD Pins)
b
650 mAV
IN
e
2.0V
I
IL
Logical 0 Input Current (QBD Pins)
b
70 mAV
IN
e
0.45V
I
IL1
Ports 3 and 4 in Reset
b
70 mAV
IN
e
0.45V
I
CC
Active Mode Current in Reset 65 75 mA XTAL1e16 MHz
(8XC196KC)
V
CC
e
V
PP
e
V
REF
e
5.5V
I
CC
Active Mode Current in Reset 80 92 mA XTAL1e20 MHz
(8XC196KC20)
V
CC
e
V
PP
e
V
REF
e
5.5V
I
IDLE
Idle Mode Current (8XC196KC) 17 25 mA XTAL1e16 MHz
V
CC
e
V
PP
e
V
REF
e
5.5V
I
IDLE
Idle Mode Current (8XC196KC20) 21 30 mA XTAL1e20 MHz
V
CC
e
V
PP
e
V
REF
e
5.5V
I
PD
Powerdown Mode Current 8 15 mAV
CC
e
V
PP
e
V
REF
e
5.5V
I
REF
A/D Converter Reference Current 2 5 mA V
CC
e
V
PP
e
V
REF
e
5.5V
R
RST
Reset Pullup Resistor 6K 65K X V
CC
e
5.5V, V
IN
e
4.0V
C
S
Pin Capacitance (Any Pin to VSS)10pF
NOTES:
1. All pins except RESET and XTAL1.
2. Violating these specifications in Reset may cause the part to enter test modes.
3. Commercial specifications apply to express parts except where noted.
4. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7.
5. Standard Outputs include AD0 – 15, RD
,WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4,
TXD/P2.0 and RXD (in serial mode 0). The V
OH
specification is not valid for RESET. Ports 3 and 4 are open-drain outputs.
6. Standard Inputs include HSI pins, READY, BUSWIDTH, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4.
7. Maximum current per pin must be externally limited to the following values if V
OL
is held above 0.45V or VOHis held
below V
CC
b
0.7V:
I
OL
on Output pins: 10 mA
I
OH
on quasi-bidirectional pins: self limiting
I
OH
on Standard Output pins: 10 mA
8. Maximum current per bus pin (data and control) during normal operation is
g
3.2 mA.
9. During normal (non-transient) conditions the following total current limits apply:
Port 1, P2.6 I
OL
:29mA IOHis self limiting
HSO, P2.0, RXD, RESET
IOL:29mA IOH:26mA
P2.5, P2.7, WR
, BHE IOL:13mA IOH:11mA
AD0–AD15 I
OL
:52mA IOH:52mA
RD
, ALE, INST – CLKOUT IOL:13mA IOH:13mA
10
8XC196KC/8XC196KC20
270942– 17
ICCMaxe4.13cFrequencya9mA
I
CC
Type3.50cFrequencya9mA
I
IDLE
Maxe1.25cFrequencya5mA
I
IDLE
Type0.88cFrequencya3mA
NOTE:
Frequencies below 8 MHz are shown for reference only; no testing is performed.
Figure 7. ICCand I
IDLE
vs Frequency
AC CHARACTERISTICS
For use over specified operating conditions.
Test Conditions: Capacitive load on all pinse100 pF, Rise and fall timese10 ns, F
OSC
e
16 MHz
The system must meet these specifications to work with the 80C196KC:
Symbol Description Min Max Units Notes
T
AVYV
Address Valid to READY Setup 2 T
OSC
b
68 ns
T
YLYH
Non READY Time No upper limit ns
T
CLYX
READY Hold after CLKOUT Low 0 T
OSC
b
30 ns (Note 1)
T
LLYX
READY Hold after ALE Low T
OSC
b
15 2 T
OSC
b
40 ns (Note 1)
T
AVGV
Address Valid to Buswidth Setup 2 T
OSC
b
68 ns
T
CLGX
Buswidth Hold after CLKOUT Low 0 ns
T
AVDV
Address Valid to Input Data Valid 3 T
OSC
b
55 ns (Note 2)
T
RLDV
RD Active to Input Data Valid T
OSC
b
22 ns (Note 2)
T
CLDV
CLKOUT Low to Input Data Valid T
OSC
b
45 ns
T
RHDZ
End of RD to Input Data Float T
OSC
ns
T
RXDX
Data Hold after RD Inactive 0 ns
NOTES:
1. If max is exceeded, additional wait states will occur.
2. If wait states are used, add 2 T
OSC
* N, where Nenumber of wait states.
11
8XC196KC/8XC196KC20
AC CHARACTERISTICS (Continued)
For user over specified operating conditions.
Test Conditions: Capacitive load on all pins
e
100 pF, Rise and fall timese10 ns, F
OSC
e
16 MHz
The 80C196KC will meet these specifications:
Symbol Description Min Max Units Notes
F
XTAL
Frequency on XTAL1 (8XC196KC) 8 16 MHz (Note 1)
F
XTAL
Frequency on XTAL1 (8XC196KC20) 8 20 MHz (Note 1)
T
OSC
I/F
XTAL
(8XC196KC) 62.5 125 ns
T
OSC
I/F
XTAL
(8XC196KC20) 50 125 ns
T
XHCH
XTAL1 High to CLKOUT High or Low
a
20
a
110 ns
T
CLCL
CLKOUT Cycle Time 2 T
OSC
ns
T
CHCL
CLKOUT High Period T
OSC
b
10 T
OSC
a
15 ns
T
CLLH
CLKOUT Falling Edge to ALE Rising
b
5
a
15 ns
T
LLCH
ALE Falling Edge to CLKOUT Rising
b
20
a
15 ns
T
LHLH
ALE Cycle Time 4 T
OSC
ns (Note 4)
T
LHLL
ALE High Period T
OSC
b
10 T
OSC
a
10 ns
T
AVLL
Address Setup to ALE Falling Edge T
OSC
b
15
T
LLAX
Address Hold after ALE Falling Edge T
OSC
b
35 ns
T
LLRL
ALE Falling Edge to RD Falling Edge T
OSC
b
30 ns
T
RLCL
RD Low to CLKOUT Falling Edge
a
4
a
30 ns
T
RLRH
RD Low Period T
OSC
b
5 ns (Note 4)
T
RHLH
RD Rising Edge to ALE Rising Edge T
OSC
T
OSC
a
25 ns (Note 2)
T
RLAZ
RD Low to Address Float
a
5ns
T
LLWL
ALE Falling Edge to WR Falling Edge T
OSC
b
10 ns
T
CLWL
CLKOUT Low to WR Falling Edge 0
a
25 ns
T
QVWH
Data Stable to WR Rising Edge T
OSC
b
23 (Note 4)
T
CHWH
CLKOUT High to WR Rising Edge
b
5
a
15 ns
T
WLWH
WR Low Period T
OSC
b
20 ns (Note 4)
T
WHQX
Data Hold after WR Rising Edge T
OSC
b
25 ns
T
WHLH
WR Rising Edge to ALE Rising Edge T
OSC
b
10 T
OSC
a
15 ns (Note 2)
T
WHBX
BHE, INST after WR Rising Edge T
OSC
b
10 ns
T
WHAX
AD8–15 HOLD after WR Rising T
OSC
b
30 ns (Note 3)
T
RHBX
BHE, INST after RD Rising Edge T
OSC
b
10 ns
T
RHAX
AD8–15 HOLD after RD Rising T
OSC
b
25 ns (Note 3)
NOTES:
1. Testing performed at 8 MHz. However, the device is static by design and will typically operate below 1 Hz.
2. Assuming back-to-back bus cycles.
3. 8-Bit bus only.
4. If wait states are used, add 2 T
OSC
* N, where Nenumber of wait states.
12
8XC196KC/8XC196KC20
System Bus Timings
270942– 18
13
8XC196KC/8XC196KC20
READY Timings (One Wait State)
270942– 20
Buswidth Timings
270942– 35
14
8XC196KC/8XC196KC20
HOLD/HLDA Timings
Symbol Description Min Max Units Notes
T
HVCH
HOLD Setup
a
55 ns (Note 1)
T
CLHAL
CLKOUT Low to HLDA Low
b
15
a
15 ns
T
CLBRL
CLKOUT Low to BREQ Low
b
15
a
15 ns
T
HALAZ
HLDA Low to Address Float
a
15 ns
T
HALBZ
HLDA Low to BHE, INST, RD,WRWeakly Driven
a
20 ns
T
CLHAH
CLKOUT Low to HLDA High
b
15
a
15 ns
T
CLBRH
CLKOUT Low to BREQ High
b
15
a
15 ns
T
HAHAX
HLDA High to Address No Longer Float
b
15 ns
T
HAHBV
HLDA High to BHE, INST, RD,WRValid
b
10
a
15 ns
T
CLLH
CLKOUT Low to ALE High
b
5
a
15 ns
NOTE:
1. To guarantee recognition at next clock.
DC SPECIFICATIONS IN HOLD
Description Min Max Units
Weak Pullups on ADV, RD, 50K 250K V
CC
e
5.5V, V
IN
e
0.45V
WR
,WRL, BHE
Weak Pulldowns on 10K 50K V
CC
e
5.5V, V
IN
e
2.4
ALE, INST
15
8XC196KC/8XC196KC20
270942– 36
Maximum Hold Latency
Bus Cycle Type
Internal Execution 1.5 States
16-Bit External Execution 2.5 States
8-Bit External Execution 4.5 States
EXTERNAL CLOCK DRIVE (8XC196KC)
Symbol Parameter Min Max Units
1/T
XLXL
Oscillator Frequency 8 16.0 MHz
T
XLXL
Oscillator Period 62.5 125 ns
T
XHXX
High Time 20 ns
T
XLXX
Low Time 20 ns
T
XLXH
Rise Time 10 ns
T
XHXL
Fall Time 10 ns
16
8XC196KC/8XC196KC20
EXTERNAL CLOCK DRIVE (8XC196KC20)
Symbol Parameter Min Max Units
1/T
XLXL
Oscillator Frequency 8 20.0 MHz
T
XLXL
Oscillator Period 50 125 ns
T
XHXX
High Time 17 ns
T
XLXX
Low Time 17 ns
T
XLXH
Rise Time 8 ns
T
XHXL
Fall Time 8 ns
EXTERNAL CLOCK DRIVE WAVEFORMS
270942– 21
EXTERNAL CRYSTAL CONNECTIONS
270942– 41
NOTE:
Keep oscillator components close to chip and use
short, direct traces to XTAL1, XTAL2 and V
SS
. When
using crystals, C1
e
C2&20 pF. When using ceramic
resonators, consult manufacturer for recommended circuitry.
EXTERNAL CLOCK CONNECTIONS
270942– 42
NOTE:
*Required if TTL driver used.
Not needed if CMOS driver is used.
AC TESTING INPUT, OUTPUT WAVEFORMS
270942– 22
AC Testing inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for
a Logic ‘‘0’’ Timing measurements are made at 2.0V for a Logic
‘‘1’’ and 0.8V for a Logic ‘‘0’’.
FLOAT WAVEFORMS
270942– 23
For Timing Purposes a Port Pin is no Longer Floating when a
150 mV change from Load Voltage Occurs and Begins to Float
when a 150 mV change from the Loaded V
OH/VOL
Level occurs;
I
OL/IOH
e
g
15 mA.
17
8XC196KC/8XC196KC20
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its
condition, respectively. Symbols represent the time between the two signal/condition points.
Conditions:
HÐ High
LÐ Low
VÐ Valid
XÐ No Longer Valid
ZÐ Floating
Signals:
AÐ Address
BÐ BHE
CÐ CLKOUT
DÐ DATA
GÐ Buswidth
HÐ HOLD
HAÐ HLDA
LÐ ALE/ADV
BRÐ BREQ
RÐ RD
WÐ WR/WRH/WRL
XÐ XTAL1
YÐ READY
QÐ Data Out
AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT TIMINGÐSHIFT REGISTER MODE (MODE 0)
Symbol Parameter Min Max Units
T
XLXL
Serial Port Clock Period (BRRt8002H) 6 T
OSC
ns
T
XLXH
Serial Port Clock Falling Edge 4 T
OSC
b
50 4 T
OSC
a
50 ns
to Rising Edge (BRR
t
8002H)
T
XLXL
Serial Port Clock Period (BRRe8001H) 4 T
OSC
ns
T
XLXH
Serial Port Clock Falling Edge 2 T
OSC
b
50 2 T
OSC
a
50 ns
to Rising Edge (BRR
e
8001H)
T
QVXH
Output Data Setup to Clock Rising Edge 2 T
OSC
b
50 ns
T
XHQX
Output Data Hold after Clock Rising Edge 2 T
OSC
b
50 ns
T
XHQV
Next Output Data Valid after Clock Rising Edge 2 T
OSC
a
50 ns
T
DVXH
Input Data Setup to Clock Rising Edge T
OSC
a
50 ns
T
XHDX
Input Data Hold after Clock Rising Edge 0 ns
T
XHQZ
Last Clock Rising to Output Float 1 T
OSC
ns
WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE
SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE (MODE 0)
270942– 24
18
8XC196KC/8XC196KC20
A to D CHARACTERISTICS
The A/D converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of V
REF
.
10-BIT MODE A/D OPERATING CONDITIONS
Symbol Description Min Max Units
T
A
Ambient Temperature Commercial Temp. 0
a
70
§
C
T
A
Ambient Temperature Extended Temp.
b
40
a
85
§
C
V
CC
Digital Supply Voltage 4.50 5.50 V
V
REF
Analog Supply Voltage 4.00 5.50 V
T
SAM
Sample Time 1.0 ms
(1)
T
CONV
Conversion Time 10 20 ms
(1)
F
OSC
Oscillator Frequency (8XC196KC) 8.0 16.0 MHz
F
OSC
Oscillator Frequency (8XC196KC20) 8.0 20.0 MHz
NOTE:
ANGND and V
SS
should nominally be at the same potential, 0.00V.
1. The value of ADÐTIME is selected to meet these specifications.
10-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)
Parameter Typical
(1)
Minimum Maximum Units* Notes
Resolution 1024 1024 Levels
10 10 Bits
Absolute Error 0
g
3 LSBs
Full Scale Error 0.25g0.5 LSBs
Zero Offset Error 0.25g0.5 LSBs
Non-Linearity 1.0g2.0 0
g
3 LSBs
Differential Non-Linearity Error
l
b
1
a
2 LSBs
Channel-to-Channel Matching
g
0.1 0
g
1 LSBs
Repeatability
g
0.25 LSBs
Temperature Coefficients:
Offset 0.009 LSB/
§
C
Full Scale 0.009 LSB/§C
Differential Non-Linearity 0.009 LSB/
§
C
Off Isolation
b
60 dB 1, 2
Feedthrough
b
60 dB 1
VCCPower Supply Rejection
b
60 dB 1
Input Series Resistance 750 1.2K X 4
Voltage on Analog Input Pin ANGNDb0.5 V
REF
a
0.5 V 5, 6
DC Input Leakage 0
g
3.0 mA
Sampling Capacitor 3 pF
NOTES:
*An ‘‘LSB’’ as used here has a value of approxiimately 5 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).
1. These values are expected for most parts at 25
§
C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if the pin current is limited to
g
2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted.
7. All conversions performed with processor in IDLE mode.
19
8XC196KC/8XC196KC20
8-BIT MODE A/D OPERATING CONDITIONS
Symbol Description Min Max Units
T
A
Ambient Temperature Commercial Temp. 0
a
70
§
C
T
A
Ambient Temperature Extended Temp.
b
40
a
85
§
C
V
CC
Digital Supply Voltage 4.50 5.50 V
V
REF
Analog Supply Voltage 4.00 5.50 V
T
SAM
Sample Time 1.0 ms
(1)
T
CONV
Conversion Time 7 20 ms
(1)
F
OSC
Oscillator Frequency (8XC196KC) 8.0 16.0 MHz
F
OSC
Oscillator Frequency (8XC196KC20) 8.0 20.0 MHz
NOTE:
ANGND and V
SS
should nominally be at the same potential, 0.00V.
1. The value of ADÐTIME is selected to meet these specifications.
8-BIT MODE A/D CHARACTERISTICS (Over Specified Operating Conditions)
Parameter Typical Minimum Maximum Units* Notes
Resolution 256 256 Levels
8 8 Bits
Absolute Error 0
g
1 LSBs
Full Scale Error
g
0.5 LSBs
Zero Offset Error
g
0.5 LSBs
Non-Linearity 0
g
1 LSBs
Differential Non-Linearity Error
l
b
1
a
1 LSBs
Channel-to-Channel Matching
g
1 LSBs
Repeatability
g
0.25 LSBs
Temperature Coefficients:
Offset 0.003 LSB/§C
Full Scale 0.003 LSB/
§
C
Differential Non-Linearity 0.003 LSB/
§
C
Off Isolation
b
60 dB 2, 3
Feedthrough
b
60 dB 2
VCCPower Supply Rejection
b
60 dB 2
Input Series Resistance 750 1.2K Xs4
Voltage on Analog Input Pin V
SS
b
0.5 V
REF
a
0.5 V 5, 6
DC Input Leakage 0
g
3.0 mA
Sampling Capacitor 3 pF
NOTES:
*An ‘‘LSB’’ as used here has a value of approximately 20 mV. (See Embedded Microcontrollers and Processors Handbook
for A/D glossary of terms).
1. These values are expected for most parts at 25
§
C but are not tested or guaranteed.
2. DC to 100 KHz.
3. Multiplexer Break-Before-Make is guaranteed.
4. Resistance from device pin, through internal MUX, to sample capacitor.
5. These values may be exceeded if pin current is limited to
g
2 mA.
6. Applying voltages beyond these specifications will degrade the accuracy of all channels being converted.
7. All conversions performed with processor in IDLE mode.
20
8XC196KC/8XC196KC20
EPROM SPECIFICATIONS
OPERATING CONDITIONS DURING PROGRAMMING
Symbol Description Min Max Units
T
A
Ambient Temperature During Programming 20 30 C
V
CC
Supply Voltage During Programming 4.5 5.5 V
(1)
V
REF
Reference Supply Voltage During Programming 4.5 5.5 V
(1)
V
PP
Programming Voltage 12.25 12.75 V
(2)
V
EA
EA Pin Voltage 12.25 12.75 V
(2)
F
OSC
Oscillator Frequency During Auto and Slave 6.0 8.0 MHz
Mode Programming
F
OSC
Oscillator Frequency During 6.0 16.0 MHz
Run-Time Programming (8XC196KC)
F
OSC
Oscillator Frequency During 6.0 20.0 MHz
Run-Time Programming (8XC196KC20)
NOTES:
1. V
CC
and V
REF
should nominally be at the same voltage during programming.
2. V
PP
and VEAmust never exceed the maximum specification, or the device may be damaged.
3. V
SS
and ANGND should nominally be at the same potential (0V).
4. Load capacitance during Auto and Slave Mode programming
e
150 pF.
AC EPROM PROGRAMMING CHARACTERISTICS
Symbol Description Min Max Units
T
SHLL
Reset High to First PALE Low 1100 T
OSC
T
LLLH
PALE Pulse Width 50 T
OSC
T
AVLL
Address Setup Time 0 T
OSC
T
LLAX
Address Hold Time 100 T
OSC
T
PLDV
PROG Low to Word Dump Valid 50 T
OSC
T
PHDX
Word Dump Data Hold 50 T
OSC
T
DVPL
Data Setup Time 0 T
OSC
T
PLDX
Data Hold Time 400 T
OSC
T
PLPH
(1)
PROG Pulse Width 50 T
OSC
T
PHLL
PROG
High to Next PALE Low 220 T
OSC
T
LHPL
PALE High to PROG Low 220 T
OSC
T
PHPL
PROG High to Next PROG Low 220 T
OSC
T
PHIL
PROG High to AINC Low 0 T
OSC
T
ILIH
AINC Pulse Width 240 T
OSC
T
ILVH
PVER Hold after AINC Low 50 T
OSC
T
ILPL
AINC Low to PROG Low 170 T
OSC
T
PHVL
PROG High to PVER Valid 220 T
OSC
NOTE:
1. This specification is for the Word Dump Mode. For programming pulses, use the Modified Quick Pulse Algorithm. See
user’s manual for further information.
21
8XC196KC/8XC196KC20
DC EPROM PROGRAMMING CHARACTERISTICS
Symbol Description Min Max Units
I
PP
VPPSupply Current (When Programming) 100 mA
NOTE:
Do not apply V
PP
until VCCis stable and within specifications and the oscillator/clock has stabilized or the device may be
damaged.
EPROM PROGRAMMING WAVEFORMS
SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE
270942– 27
NOTE:
P3.0 must be high (‘‘1’’)
SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT
270942– 28
NOTE:
P3.0 must be low (‘‘0’’)
22
8XC196KC/8XC196KC20
SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM
WITH REPEATED PROG PULSE AND AUTO INCREMENT
270942– 29
8XC196KB TO 8XC196KC DESIGN
CONSIDERATIONS
1. Memory Map. The 8XC196KC has 512 bytes of
RAM/SFRs and an optional 16K of
ROM/OTPROM. The extra 256 bytes of RAM will
reside in locations 100H – 1FFH and the extra 8K
of ROM/OTPROM will reside in locations
4000H–5FFFH. These locations are external
memory on the 8XC196KB.
2. The CDE pin on the KB has become a V
SS
pin on
the KC to support 16/20 MHz operation.
3. EPROM programming. The 8XC196KC has a different programming algorithm to support 16K of
on-board memory. When performing Run-Time
Programming, use the section of code in the
8XC196KC User’s Guide.
4. ONCE Mode Entry. The ONCE mode is entered
on the 8XC196KC by driving the TXD pin low on
the rising edge of RESET. The TXD pin is held
high by a pullup that is specified by I
OH1
. This
Pullup must not be overridden or the 8XC196KC
will enter the ONCE mode.
5. During the bus HOLD state, the 8XC196KC
weakly holds RD
,WR, ALE, BHE and INST in
their inactive states. The 8XC196KB only holds
ALE in its inactive state.
6. A RESET pulse from the 8XC196KC is 16 states
rather than 4 states as on the 8XC196KB (i.e., a
watchdog timer overflow). This provides a longer
RESET pulse for other devices in the system.
8XC196KC ERRATA
1. Missed EXTINT on P0.7.
The 80C196KC20 could possibly miss an
EXTINT on P0.7. See techbit MC0893.
2. HSIÐMODE divide-by-eight.
See Faxback
Ý
2192.
3. IPD hump.
See FaxbackÝ2311.
23
8XC196KC/8XC196KC20
DATA SHEET REVISION HISTORY
This data sheet is valid for devices with a ‘‘H’’, ‘‘L’’ or ‘‘M’’ at the end of the topside tracking number. The
topside tracking number consists of nine characters and is the second line on the top side of the device. Data
sheets are changed as new device information becomes available. Verify with your local Intel sales office that
you have the latest version before finalizing a design or ordering devices.
The following are differences between the 270942-004 and 270942-005 datasheets:
1. Removed ‘‘Word Addressable Only’’ from Port 3 and 4 in Table 2.
2. Renamed PVAL to CPVER.
3. Removed T
LLYV
and T
LLGV
from the waveform diagrams.
4. Added HSIÐMODE divide-by-eight and IPD hump to 8XC196KC errata.
The following are important differences between the 270942-002 and 270942-004 data sheets:
1. NMI during PTS, QBD port glitch and Divide HOLD/READY erratas were fixed and have been removed
from the data sheet. The HSI errata is also removed as this is now considered normal operation.
2. Combined 16 and 20 MHz data sheets. Data sheet 270924-001 (20 MHz) is now obsolete.
3. Added 80-lead SQFP package pinout.
4. Added documentation for CLKOUT disable bit.
5. i
JA
for QFP package was changed to 55§C/W from 42§C/W.
6. iJCfor QFP package was changed to 16§C/W from TBD§C/W.
7. T
SAM
(MIN) in 10-bit mode was changed to 1.0 ms from 3.0 ms.
8. T
SAM
(MIN) in 8-bit mode was changed to 1.0 ms from 2.0 ms.
9. I
IL1
specification for port 2.0 was renamed I
IL2
.
10. I
IL2
(MAX) is changed to TBD fromb6 mA.
11. I
IH1
(MAX) is changed toa200 mA froma100 mA.
12. I
IH1
test condition changes to V
IN
e
2.4V from V
IN
e
5.5V.
13. V
HYS
is changed to 300 mV from 150 mV.
14. ICC(TYP) at 16 MHz is changed to 65 mA from 50 mA.
15. ICC(MAX) at 16 MHz is changed to 75 mA from 70 mA.
16. I
CC
(TYP) at 20 MHz is changed to 80 mA from 60 mA.
17. ICC(MAX) at 20 MHz is changed to 92 mA from 86 mA.
18. I
IDLE
(TYP) at 16 MHz is changed to 17 mA from 15 mA.
19. I
IDLE
(MAX) at 16 MHz is changed to 25 mA from 30 mA.
20. I
IDLE
(TYP) at 20 MHz is changed to 21 mA from 15 mA.
21. I
IDLE
(MAX) at 20 MHz is changed to 30 mA from 35 mA.
22. IPD(TYP) at 16 MHz is changed to 8 mA from 15 mA.
23. IPD(MAX) at 16 MHz is changed to 15 mA from TBD.
24. IPD(TYP) at 20 MHz is changed to 8 mA from 18 mA.
25. IPD(MAX) at 20 MHz is changed to 15 mA from TBD.
26. T
CLDV
(MAX) is changed to T
OSC
b
45 ns from T
OSC
b
50 ns.
27. T
LLAX
(MIN) is changed to T
OSC
b
35 ns from T
OSC
b
40 ns.
28. T
CHWH
(MIN) is changed tob5 ns fromb10 ns.
29. T
RHAX
(MIN) is changed to T
OSC
b
25 ns from T
OSC
b
30 ns.
30. T
HALAZ
(MAX) is changed toa15 ns froma10 ns.
31. T
HALBZ
(MAX) is changed toa20 ns froma15 ns.
24
8XC196KC/8XC196KC20
32. T
HAHBV
(MAX) is now specified ata15 ns, was formerly unspecified.
33. The T
LLYV
and T
LLGV
specifications were removed. These specifications are not required in high-speed
systems designs.
34. Added EXTINT, P0.7 errata to Errata section.
The following are the important differences between the -001 and -002 versions of data sheet 270942.
1. Express and Commercial devices are combined into one data sheet. The Express only data sheet
270794-001 is obsolete.
2. Removed KB/KC feature set differences, pin definition table, and SFR locations and bitmaps.
3. Added programming pin function to package drawings and pin descriptions.
4. Changed absolute maximum temperature under bias from 0
§
Ctoa70§Ctob55§Ctoa125§C.
5. Replaced V
OH2
specification with I
OH1
and I
IL1
specifications.
6. Added I
IH1
specification for NMI pulldown resistors.
7. Added maximum hold latency table.
8. Added external oscillator and external clock circuit drawings.
9. Changed Clock Drive T
XHXX
and T
XLXX
Min spec to 20 ns.
10. Fixed Serial Port T
XLXH
specification.
11. Added 8- and 10-bit mode A/D operating conditions tables.
12. Specified operating range for sample and convert times.
13. Added specification for voltage on analog input pin.
14. Put operating conditions for EPROM programming into tabular format.
25
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