Intel Corporation TP28F010-90, TP28F010-150, TP28F010-120, TN28F010-150, TN28F010-120 Datasheet
...
E
December 1997
28F010 1024K (128K X 8) CMOS
FLASH MEMORY
8
n
Flash Electrical Chip-Erase
1 Second Typical Chip-Erase
n
Quick-Pulse Programming Algorithm
10 µs Typical Byte-Program
2 Second Chip-Program
n
100,000 Erase/Program Cycles
n
12.0 V ±5% V
n
High-Performance Read
90 ns Maximum Access Time
n
CMOS Low Power Consumption
10 mA Typical Active Current
50 µA Typical Standby Current
0 Watts Data Retention Power
n
Integrated Program/Erase Stop Timer
Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory content s can be rewrit ten: in a t est s ocket ; in a PROM-program mer sock et; onboard during subassembly test; in-system during final test; and in-system after sale. The 28F010 increases
memory flexibility, while contributing to time and cost savings.
PP
n
Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
n
Noise Immunity Features
±10% V
Maximum Latch-Up Immunity
through EPI Processing
n
ETOX™ Nonvolatile Flash Technology
EPROM-Compatible Process Base
High-Volume Manufacturing
Experience
n
JEDEC-Standard Pinouts
32-Pin Plastic Dip
32-Lead PLCC
32-Lead TSOP
(See Packaging Spec., Order #231369)
n
Extended Temperature Options
Tolerance
CC
The 28F010 is a 1024 kilobit nonvolatile memory organized as 131,072 byt es of eight bits. Intel’s 28F010 is
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel's ETOX™ (EPROM Tunnel Oxide)
process technology. A dvanced oxide processing, an optimized t unneling structure, and lower elect ric field
combine to extend reliable cycling beyond that of traditional EEPROMs. With the 12.0 V V
28F010 performs 100,000 erase and program cycles—well within the time limits of the quick-pulse
programming and quick-erase algorithms.
Intel's 28F010 employs adv anced CMOS circuitry for systems requiring high-performance access speeds,
low power consumption, and immunity to nois e. Its 90 ns acc ess time provides z ero wait-state performanc e
for a wide range of microprocessors and microcontrol lers. Max imum st andby c urrent of 100 µA t ranslat es i nto
power savings when the device is deselected. Finall y, the highest degree of latc h-up protection is achieved
through Intel's unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA on
address and data pins, from –1 V to V
With Intel's ETOX process technology bas e, the 28F010 builds on years of EPROM experience to yield t he
highest levels of quality, reliability, and cost-effectiveness.
CC
+ 1 V.
Order Number: 290207-012
supply, the
PP
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F010 may contain design defects or errors known as errata. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 5937
Denver, CO 80217-9808
or call 1-800-548-4725
or visit Intel’s website at http://www.intel.com
Copyright © Intel Corporation 1996, 1997.
* Third-party brands and names are the property of their respective owners.
E 28F010
CONTENTS
PAGE PAGE
1.0 APPLICATIONS..............................................5
2.0 PRINCIPLES OF OPERATION .......................8
2.1 Integrated Stop Timer ..................................8
2.2 Write Protection ...........................................9
2.2.1 Bus Operations......................................9
2.2.1.1 Read...............................................9
2.2.1.2 Output Disable................................9
2.2.1.3 Standby ........................................10
2.2.1.4 Intelligent Identifier Operation.......10
2.2.1.5 Write.............................................10
2.2.2 Command Definitions..........................10
2.2.2.1 Read Command............................11
2.2.2.2 Intelligent Identifier Command ......11
2.2.2.3 Set-Up Erase/Erase Commands...12
2.2.2.4 Erase Verify Command.................12
2.2.2.5 Set-Up Program/Program
Commands ..................................12
2.2.2.6 Program Verify Command ............12
2.2.2.7 Reset Command...........................13
2.2.3 Extended Erase/Program Cycling........13
2.2.4 Quick-Pulse Programming Algorithm...13
2.2.5 Quick-Erase Algorithm.........................13
3.0 DESIGN CONSIDERATIONS........................16
3.1 Two-Line Output Control............................16
3.2 Power Supply Decoupling..........................16
Trace on Printed Circuit Boards...........16
3.3 V
PP
3.4 Power-Up/Down Protection........................16
3.5 28F010 Power Dissipation .........................16
4.0 ELECTRICAL SPECIFICATIONS..................18
4.1 Absolute Maximum Ratings........................18
4.2 Operating Conditions..................................18
4.3 Capacitance...............................................18
4.4 DC Characteristics—TTL/NMOS
Compatible—Commercial Products...........19
4.5 DC Characteristics—CMOS Compatible—
Commercial Products................................20
4.6 DC Characteristics—TTL/NMOS
Compatible—Extended Temperature
Products....................................................22
4.7 DC Characteristics—CMOS Compatible—
Extended Temperature Products...............23
4.8 AC Characteristics—Read-Only
Operations—Commercial and Extended
Temperature Products...............................25
4.9 AC Characteristics—Write/Erase/Program
Only Operations —Commercial and
Extended Temperature Products...............27
4.10 AC Characteristics—Alternative CE#Controlled Writes— Commercial and
Extended Temperature..............................31
4.11 Erase and Programming Performance......32
5.0 ORDERING INFORMATION..........................33
6.0 ADDITIONAL INFORMATION.......................33
3
28F010 E
REVISION HISTORY
Number Description
-007 Removed 200 ns Speed Bin
-008 Corrected AC Waveforms
-009 Added 28F010-65 and 28F010-90 speeds
Revised Erase Maximum Pulse Count for Figure 4 from 3000 to 1000
Clarified AC and DC Test Conditions
Added “dimple” to F TSOP Package
Corrected Serpentine Layout
Added Extended Temperature Options
———— ———
Revised Symbols, i.e., CE, OE, etc. to CE#, OE#, etc.
-010 Completion of Read Operation Table
Labelling of Program Time in Erase/Program Table
Textual Changes or Edits
Corrected Erase/Program Times
-011 Minor changes throughout document
-012 Removed 65 ns speed bin
Removed TSOP package
Added Extended Temperature options
Modified
Modified
AC Test Conditions
AC Characteristics
4
E 28F010
1.0 APPLICATIONS
The 28F010 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These
features make the 28F010 an innovat ive alt ernative
to disk, EEPROM, and battery-backed st atic RAM.
Where periodic updates of code and data tables are
required, the 28F010’s reprogrammability and
nonvolatility make it the obvious and ideal
replacement for EPROM.
Primary applications and operat ing systems stored
in flash eliminate the s low disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption—a considerat i on particularly important
in portable equipment. Flash memory increases
flexibility with electrical chip eras ure and in-system
update capability of operating systems and
application code. With updatable code, system
manufacturers can easil y ac commodat e last -minute
changes as revisions are made.
In diskless workstations and terminals, network
traffic reduces to a minimum and systems are
instant-on. Reliability exceeds that of electromechanical media. Often in these environments,
power interruptions force ext ended re-boot periods
for all networked terminals. This mishap is no
longer an issue if boot code, operating systems,
communication protocols and primary applications
are flash resident in each terminal.
For embedded systems that rely on dynamic
RAM/disk for main system memory or nonvolatile
backup storage, the 28F010 flas h memory offers a
solid state alternati ve in a minimal form factor. The
28F010 provides higher performance, lower power
consumption, instant-on capability, and allows an
“eXecute in place” (XIP) m emory hierarc hy for code
and data table reading. Additionally, the flash
memory is more rugged and reliable in harsh
environments where extreme temperatures and
shock can cause disk-based systems to fail.
The need for code updates pervades all phases of
a system's life—from prototyping to system
manufacture to after sale service. The electrical
chip-erasure and reprogramming ability of the
28F010 allows in-circuit alterability; this eliminates
unnecessary handling and less reliable socketed
connections, while adding greater test,
manufacture, and update flexibility.
Material and labor costs associated with code
changes increases at higher levels of system
integration—the most costly being code updates
after sale. Code “bugs,” or the desire to augment
system functionality, prompt after sale code
updates. Field revisions to EPROM-based code
requires the removal of EPROM components or
entire boards. With the 28F010, code updates are
implemented locally via an edge connector, or
remotely over a communcation link.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory's inherent nonvolatility eliminat es the
need for battery backup. The concern for battery
failure no longer exists, an important consi deration
for portable equipment and medical instruments,
both requiring continuous performanc e. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Flash memory's electrical chip erasure, byte
programmability and complete nonvolatility fit well
with data accumulation and recording needs.
Electrical chip-eras ure gives the designer a “blank
slate” in which to log or record dat a. Data can be
periodically off-loaded for analysis and the flash
memory erased producing a new “blank slate.”
A high degree of on-chip feature integration
simplifies memory -to-processor interfacing. Fi gure 3
depicts two 28F010s tied to the 80C186 system
bus. The 28F010's architect ure minimizes interface
circuitry needed for complete in-circuit updates of
memory contents.
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 m m thick ness. TSOP i s
particularly suited for portable equipment and
applications requiring large amounts of flash
memory.
With cost-effective in-system reprogramming,
extended cycling capability, and true nonvolatility,
the 28F010 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straightforward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today's designs.
5
28F010 E
Figure 1. 28F010 Block Diagram
Table 1. Pin Description
Symbol Type Name and Function
A0–A
16
INPUT ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
DQ0–DQ7INPUT/OUTPUT DATA INPUT/OUTPUT: Inputs data during memory write cycles; outputs
data during memory read cycles. The data pins are active high and float to
tri-state off when the chip is deselected or the outputs are disabled. Data is
internally latched during a write cycle
CE# INPUT CHIP ENABLE: Activates the device's control logic, input buffers, decoders
and sense amplifiers. CE# is active low; CE# high deselects the memory
device and reduces power consumption to standby levels.
OE# INPUT OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OE# is active low.
WE# INPUT WRITE ENABLE: Controls writes to the control register and the array. Write
enable is active low. Addresses are latched on the falling edge and data is
latched on the rising edge of the WE# pulse.
Note: With V
≤ 6.5 V, memory contents cannot be altered.
PP
6
290207-1
E 28F010
Table 1. Pin Description (Continued)
Symbol Type Name and Function
V
PP
V
CC
V
SS
NC NO INTERNAL CONNECTION to device. Pin may be driven or left floating.
ERASE/PROGRAM POWER SUPPLY for writing the command register,
erasing the entire array, or programming bytes in the array.
DEVICE POWER SUPPLY (5 V ±10%)
GROUND
Figure 2. 28F010 Pin Configurations
7
28F010 E
Figure 3. 28F010 in a 80C186 System
2.0 PRINCIPLES OF OPERATION
Flash memory augments EPROM func tionality with
in-circuit electric al erasure and reprogramm ing. The
28F010 introduces a command regist er to manage
this new functionality. The c ommand regis ter allows
for: 100% TTL-level control inputs; fixed power
supplies during erasure and programming; and
maximum EPROM compatibility.
In the absence of high volt age on the V
28F010 is a read-only memory. Manipulation of the
external memory control pins yields the standard
EPROM read, standby, output disable, and
intelligent identifier operations.
The same EPROM read, standby, and output
disable operations are available when high voltage
is applied to the V
on V
enables erasure and programming of the
PP
pin. In addition, high volt age
PP
device. All functions associated with altering
memory contents—intelligent identifier, erase,
erase verify, program, and program verify—are
accessed via the command register.
8
pin, the
PP
290207-4
Commands are written to the register using
standard microprocessor write timings. Register
contents serve as input to an i nternal s tat e machi ne
which controls the erase and programm ing c irc uit ry.
Write cycles also internally latch addresses and
data needed for programming or erase operations .
With the appropriate command written to the
register, standard microprocessor read timings
output array data, access the intelligent identifier
codes, or output data for erase and program
verification.
2.1 Integrated Stop Timer
Successive command write cycles define the
durations of program and erase operations;
specifically, the program or erase time durations are
normally terminated by associated Program or
Erase Verify commands. An integrated stop timer
provides simplified timing control over these
operations; thus eliminati ng the need for maximum
program/erase timing specifications. Programming
and erase pulse durations are minimums only.
When the stop timer terminat es a program or erase
operation, the device enters an inactive state and
remains inactive until receiving the appropriate
Verify or Reset command.
E 28F010
Table 2. 28F010 Bus Operations
Mode V
Read V
Output Disable V
READ-ONLY Standby V
Intelligent Identifier (Mfr)
(2)
Intelligent Identifier (Device)
Read V
READ/WRITE Output Disable V
(5)
Standby
Write V
NOTES:
1. Refer to
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
3. V
4. Read operations with V
5. With V
6. Refer to Table 3 for valid data-in during a write operation.
7. X can be V
DC Characteristics
addresses low.
is the intelligent identifier high voltage. Refer to
ID
at high voltage, the standby current equals ICC + IPP (standby).
PP
or VIH.
IL
. When VPP = V
= V
may access array data or the intelligent identifier codes.
PP
PPH
memory contents can be read but not written or erased.
PPL
(1)
PP
PPLA0
PPL
PPL
V
PPLVILVID
(2)
V
PPLVIHVID
PPHA0
PPH
V
PPH
PPHA0
DC Characteristics
A
A9CE# OE# WE# DQ0–DQ
0
A
VILVILVIHData Out
9
XXVILVIHVIHTri-State
XXVIHX X Tri-State
(3)
VILVILVIHData = 89H
(3)
VILVILVIHData = B4H
A
VILVILVIHData Out
9
XXVILVIHVIHTri-State
XXVIHX X Tri-State
A
VILVIHVILData In
9
.
7
(4)
(6)
2.2 Write Protection
The command register is only ac tive when VPP is at
high voltage. Depending upon the application, the
system designer may choose to make the V
power supply switchable—available only when
memory updates are desired. When V
= V
PP
contents of the register default to the Read
command, making the 28F010 a read-only mem ory.
In this mode, the memory contents cannot be
altered.
Or, the system designer may choose to “hardwire”
V
, making the high voltage supply constantly
PP
available. In this case, all command register
functions are inhibited whenev er V
write lockout voltage V
Power-Up/Down Protection
. (See Section 3.4,
LKO
.) The 28F010 is
is below the
CC
designed to accommodate either design practice,
and to encourage optimization of the processor
memory interface.
The two-step program/erase write sequence t o the
command register provides additional software
write protections.
PPL
PP
, the
2.2.1 BUS OPERATIONS
2.2.1.1 Read
The 28F010 has two control functions, both of
which must be logically active, to obtain dat a at t he
outputs. Chip Enable (CE#) is the power control
and should be used for device selection. Output
Enable (OE#) is the output control and should be
used to gate data from the output pins , independent
of device selection. Refer to the AC read timing
waveforms.
When V
is high (V
PP
), the read operation can be
PPH
used to access array data, to output t he intelligent
identifier codes, and to access data for
program/erase verificati on. When V
is low (V
PP
PPL
the read operation can only access the array data.
2.2.1.2 Output Disable
With OE# at a logic-high level (V
), output from the
IH
device is disabled. Output pins are placed i n a highimpedance state.
),
9
28F010 E
2.2.1.3 Standby
With CE# at a logic-high level, the standby
operation disables most of the 28F010’s circuitry
and substantially reduces device power
consumption. The outputs are placed in a highimpedance state, independent of the OE# signal. I f
the 28F010 is deselected during erasure,
programming, or program/erase verification, the
device draws active current until the operation is
terminated.
2.2.1.4 Intelligent Identifier Operation
The intelligent identifier operation outputs the
manufacturer code (89H) and device code (B4H).
Programming equipment automatical ly matches t he
device with its proper erase and programming
algorithms.
With CE# and OE# at a logic low lev el, raisi ng A
high voltage V
(see
DC Characteristics
ID
to
9
) activates
the operation. Data read from locations 0000H and
0001H represent the manufacturer's code and the
device code, respectively.
The manufacturer and device codes can also be
read via the command register, for ins tances where
the 28F010 is erased and reprogrammed in the
target system. Following a write of 90H to the
command register, a read from address location
0000H outputs the manufacturer code (89H). A
read from address 0001H outputs the dev ice code
(B4H).
2.2.1.5 Write
Device erasure and programming are acc ompli shed
via the command register, when high voltage is
applied to the V
pin. The contents of the register
PP
serve as input to the internal state machine. The
state machine outputs dictate the function of the
device.
The command register itself does not occupy an
addressable memory location. The register is a
latch used to store the command, along with
address and data information needed to execute
the command.
The command register is writ ten by bringing WE# to
a logic-low level (V
), while CE# is low. Addresses
IL
are latched on the falling edge of WE#, while data is
latched on the rising edge of the WE# pulse.
Standard microprocessor write timings are used.
Refer to
Only Operations
AC Characteristics—Write/Erase/Program
and the erase/programming
waveforms for specific timing parameters.
2.2.2 COMMAND DEFINITIONS
When low voltage is applied to the V
pin, the
PP
contents of the command register default to 00H,
enabling read-only operations.
Placing high voltage on the V
pin enables
PP
read/write operations. Device operations are
selected by writing specific data patterns into the
command register. Table 3 defines these 28F010
register commands.
10
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