Intel Corporation TG80960JA-25 Datasheet
80960JA/JF/JD/JT 3.3 V EMBEDDED
32-BIT MICROPROCESSOR
Advance Information Datasheet
Product Features
■ Pin/Code Compatible with all 80 960Jx
Processors
■ High-Performance Embedded Architecture
—One Instruction/Clock Execution
—Core Clock Rate is:
80960JA/JF 1x the Bus Clock
80960JD 2x the Bus Clock
80960JT 3x the Bus Clock
—Load/Store Programming Model
—Sixteen 32-Bit Global Registers
—Sixteen 32-Bit Local Registers (8 sets)
—Nine Addressing Modes
—User/Supervisor Protection Model
■ Two-Way Set Associative Instruction
Cache
—80960JA - 2 Kbyte
—80960JF/JD - 4 Kbyte
—80960JT - 16 Kbyte
—Programmable Cache-Locking
Mechanism
■ Direct Mapped Data Cache
—80960JA - 1 Kbyte
—80960JF/JD - 2 Kbyte
—80960JT - 4 Kbyte
—Write Through Operation
■ On-Chip Stack Frame Cache
—Seven Register Sets Can Be Saved
—Automatic Allocation on Call/Return
—0-7 Frames Reserved for High-Priority
Interrupts
■ On-Chip Data RAM
—1 Kbyte Critical Variable Storage
—Single-Cycle Access
■ 3.3 V Supply Voltage
—5 V Tolerant Inputs
—TTL Compatible Outputs
■ High Bandwidth Burst B us
—32-Bit Multiplexed Address/Data
—Programmable Memory Configuration
—Selectable 8-, 16-, 32-Bit Bus Widths
—Supports Unaligned Accesses
—Big or Little Endian Byte Ordering
■ High-Speed Interrupt Controller
—31 Programmable Priorities
—Eight Maskable Pins plus NMI
—Up to 240 Vectors in Expanded Mode
■ Two On-Chip Timers
—Independent 32-Bit Counting
—Clock Prescaling by 1, 2, 4 or 8
—lnternal Interrupt Sources
■ Halt Mode for Low Power
■ IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
■ Packages
—132-Lead Pin Grid Array (PGA)
—132-Lead Plastic Quad Flat Pack
(PQFP)
—196-Ball Mini Plastic Ball Grid Array
(MPBGA)
Notice: This document contains information on products in the sampling and initial production
phases of development. The specifications are subject to change without notice. Verify with your
local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 273159-001
March, 1998
80960JA/JF/JD/JT 3.3 V Microprocessor
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
80960JA/JF/JD/JT 3.3 V Microprocessor
The
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
may contain design defects or errors known as errata which may cause the product to deviate from
Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Contents
1.0 Introduction..................................................................................................................7
2.0 80960Jx Overview....................................... ...............................................................7
2.1 80960 Processor Core ..........................................................................................9
2.2 Burst Bus............................ ....... ..........................................................................10
2.3 Timer Unit............................................................................................................10
2.4 Priority Interrupt Controller..................................................................................10
2.5 Instruction Set Summary.....................................................................................11
2.6 Faults and Debugging .........................................................................................11
2.7 Low Power Operation..........................................................................................11
2.8 Test Features......................................................................................................12
2.9 Memory-Mapped Control Registe rs ....................................... ...... ....... ...... ....... ...12
2.10 Data Types and Memory Addressing Modes ......................................................12
3.0 Package Information...............................................................................................14
3.1 Pin Descriptions ................. ....... ..........................................................................16
3.1.1 Functional Pin Definitions.......................................................................16
3.1.2 80960Jx 132-Lead PGA Pinout..............................................................22
3.1.3 80960Jx 132-Lead PQFP Pinout............................................................26
3.1.4 80960Jx 196-Ball MPBGA Pinout ..........................................................29
3.2 Package Thermal Specifications.........................................................................34
3.3 Thermal Management Accessori es. ....... ...... ....... ................................................38
3.3.1 Heatsinks.. ....... ...... ....... ...... ....... ...... ....... ................................................38
4.0 Electrical Specifications........................................................................................39
4.1 Absolute Maximum Ratings.................................................................................39
4.2 Operating Conditions...........................................................................................39
4.3 Connection Recommendations...........................................................................40
4.4 VCC5 Pin Requirements (VDIFF) .......................................................................40
4.5 VCCPLL Pin Requirements.................................................................................41
4.6 DC Specifications................................................................................................42
4.7 AC Specifications ................................................................................................44
4.7.1 AC Test Conditions and Derating Curves ..............................................47
4.7.2 AC Timing Waveforms ...........................................................................52
5.0 Bus Functional Waveforms..................................................................................58
5.1 Basic Bus States .................................................................................................68
5.2 Boundary-Scan Register .....................................................................................69
6.0 Device Identification ...............................................................................................74
7.0 Revision History.......................................................................................................77
Advance Information Datasheet 3
80960JA/JF/JD/JT 3.3 V Microprocessor
Figures
1 80960Jx Microprocessor Package Options...........................................................7
2 80960Jx Block Diagram ........................................................................................9
3 132-Lead Pin Grid Array Bottom View - Pins Facing Up.....................................22
4 132-Lead Pin Grid Array Top View - Pins Facing Down .....................................23
5 132-Lead PQFP - Top View ................................................................................26
6 196-Ball Mini Plastic Ball Grid Array Bottom View - Balls Facing Up..................29
7 196-Ball Mini Plastic Ball Grid Array Top View - Balls Facing Down ..................30
8 VCC5 Current-Limiting Resistor..........................................................................40
9 VCCPLL Lowpass Filter............... ...... ....... ...... ....... ...... .......................................41
10 AC Test Load ......................................................................................................47
11 Output Delay or Hold vs. Load Capacitance.......................................................48
12 T
13 80960JA/JF I
14 80960JA/JF I
15 80960JD I
16 80960JD I
17 80960JT I
18 80960JT I
19 CLKIN Waveform ................................................................................................52
20 T
21 T
22 T
23 T
24 T
25 T
26 T
27 DT/R
28 TCK Waveform....................................................................................................56
29 T
30 T
31 T
32 T
33 Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus .........58
34 Burst Read and Write Transactions Without Wait States, 32-Bit Bus.................59
35 Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus...........................60
36 Burst Read and Write Transactions Without Wait States, 8-Bit Bus...................61
37 Burst Read and Write Transactions With 1, 0 Wait States and
38 Double Word Read Bus Request, Misaligned One Byte From
39 HOLD/HOLDA Waveform For Bus Arbitration ....................................................64
40 Cold Reset Waveform.........................................................................................65
41 Warm Reset Waveform... ...... ....... ...... ....... ...... ....... ...... ....... ...... ..........................6 6
42 Entering the ONCE State....................................................................................67
43 Bus States with Arbitration ..................................................................................68
44 Summary of Aligned and Unaligned Accesses (32-Bit Bus) ...............................72
45 Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ...........73
46 80960JT Device Identification Register...............................................................74
47 80960JD Device Identification Register ..............................................................75
48 80960JA/JF Device Identification Register .........................................................76
vs. AD Bus Load Capacitance......................................................................48
LX
Output Delay Waveform.............................................................................52
OV1
Output Float Waveform................................................................................53
OF
and T
IS1
and T
IS2
and T
IS3
and T
IS4
, T
LX
LXL
Active (Power Supply) vs. Frequency.......................................49
CC
Active (Thermal) vs. Frequency................................................49
CC
Active (Power Supply) vs. Frequency............................................50
CC
Active (Thermal) vs. Frequency.....................................................50
CC
Active (Power Supply) vs. Frequency...........................................51
CC
Active (Thermal) vs. Frequency .....................................................51
CC
Input Setup and Hold Waveform...................................................53
IH1
Input Setup and Hold Waveform...................................................53
IH2
Input Setup and Hold Waveform...................................................54
IH3
Input Setup and Hold Waveform...................................................54
IH4
and T
LXA
and DEN Timings Waveform .....................................................................55
and T
BSIS1
BSOV1
BSOV2
BSIS2
and T
and T
and T
BSIH1
BSOF1
BSOF2
BSIH2
Extra Tr State on Read, 16-Bit Bus.....................................................................62
Quad Word Boundary, 32-Bit Bus, Little Endian.................................................63
Relative Timings Waveform.................................................55
Input Setup and Hold Waveforms .........................................56
Output Delay and Output Float Waveform..........................56
Output Delay and Output Float Waveform..........................57
Input Setup and Hold Waveform...........................................57
4
Advance Information Datasheet
Tables
80960JA/JF/JD/JT 3.3 V Microprocessor
1 80960Jx Instruction Set.......................................................................................13
2 Pin Description Nomenclature... ...... ....................................................................16
3 Pin Description — External Bus Signals .............................................................17
4 Pin Description — Processor Control Signals, Test Signals and Power.............20
5 Pin Description — Interrupt Unit Signals.............................................................21
6 132-Lead PGA Pinout — In Signal Order............................................................24
7 132-Lead PGA Pinout — In Pin Order ................................................................25
8 132-Lead PQFP Pinout — In Signal Order .........................................................27
9 132-Lead PQFP Pinout — In Pin Order..............................................................28
10 196-Ball MPBGA Pinout — In Signal Order ........................................................31
11 196-Ball MPBGA Pinout — In Pin Order.............................................................33
12 132-Lead PGA Package Thermal Characteristics...............................................35
13 196-Ball MPBGA Package Thermal Characteristics ...........................................35
14 132-Lead PQFP Package Thermal Characteristics ............................................36
15 Maximum T
16 Maximum T
17 Maximum T
at Various Airflows in °C (80960JT)...............................................36
A
at Various Airflows in °C (80960JD) ..............................................37
A
at Various Airflows in °C (80960JA/JF)..........................................37
A
18 Absolute Maximum Ratings.................................................................................39
19 80960Jx Operating Conditions............................................................................39
20 VDIFF Parameters ..............................................................................................40
21 80960Jx DC Characteristics................................................................................42
22 80960Jx I
Characteristics............ ....................................................................42
CC
23 80960Jx AC Characteristics................................................................................44
24 Note Definitions for Table 23, 80960Jx AC Characteristics (pg. 44) ...................47
25 Boundary-Scan Register Bit Order......................................................................69
26 Natural Boundaries for Load and Store Accesses ..............................................70
27 Summary of Byte Load and Store Accesses.......................................................70
28 Summary of Short Word Load and Store Accesses............................................70
29 Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)...........................71
30 80960Jx Device Type and Stepping Reference..................................................74
31 Fields of 80960JT Device ID...............................................................................75
32 80960JT Device ID Model Types........................................................................75
33 Fields of 80960JD Device ID...............................................................................76
34 80960JD Device ID Model Types........................................................................76
35 Fields of 80960JA/JF Device ID..........................................................................77
36 80960JA/JF Device ID Model Types...................................................................77
37 Data Sheet Revision History ...............................................................................77
Advance Information Datasheet 5
1.0 Introduction
This document contains information for the 80960Jx microprocessor, including electrical
characteristics and package pinout information. Detailed functional descriptions — other than
parametric performance — are published in the i960
(272483).
Figure 1. 80960Jx Microprocessor Package Options
80960JA/JF/JD/JT 3.3 V Microprocessor
®
Jx Microprocessor Developer’s Manual
A80960JX
XXXXXXXXSS
M
©19xx
i
132-Pin PGA
Throughout this data sheet, references to “80960Jx” indicate features that apply to all of the
following:
• 80960JA — 3.3 V (5 V Tolerant), 2 Kbyte instruction cache, 1 Kbyte data cache
• 80960JF — 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache
• 80960JD — 3.3 V (5 V Tolerant), 4 Kbyte instruction cache, 2 Kbyte data cache and clock
doubling
• 80960JT — 3.3 V (5 V Tolerant), 16 Kbyte instruction cache, 4 Kbyte data cache and clock
tripling
2.0 80960Jx Overview
i960
NG80960JX
XXXXXXXX SS
M
i
132-Pin PQFP
®
© 19xx
GD80960JX
XXXXXXXSS
M
i
©19xx
136-Ball MPBGA
The 80960Jx of fers high perform ance to cost-s ensitive 32-bi t emb edded ap plicat ions . The 80 960Jx
is object code compatible with the 80960 Core Architecture and is capable of sustained execution
at the rate of one instruction per clock. This processor’s features include generous instruction
cache, data cache and data RAM. It also boasts a fast interrupt mechanism and dual-programmable
timer units.
The 80960Jx’s clock multiplication operates the processor core at two or three times the bus clock
rate to improve execution performance without increasing the complexity of board designs.
Memory subsystems for cost-sensitive emb e dded applications often impose substantial wait state
penalties. The 80960Jx integrates considerable storage resources on-chip to decouple CPU
execution from the external bus.
Advance Information Datasheet 7
80960JA/JF/JD/JT 3.3 V Microprocessor
The 80960Jx rapidly allocates and deallocates local register sets during context switches. The
processor needs to flush a register set to the stack only when it saves more than seven sets to its
local register cache.
A 32-bit multiplexed burst bus provides a high-speed interface to system memory and I/O. A full
complement of control signals simplifies the connection of the 80960Jx to external components.
The user programs physical and logical memory attributes through memory-mapped control
registers (MMRs) — an extension not found on the i960 Kx, Sx or Cx processors. Physical and
logical configuration registers enable the processor to operate with all combinations of bus width
and data object alignment. The processor supports a homogeneous byte ordering model.
This processor integrates two important peripherals: a timer unit, and an interrupt controller. Th ese
and other hardware resources are programmed through memory-mapped control registers, an
extension to the familiar 80960 architecture.
The timer unit (TU) offers two independent 32-bit timers for use as real-time system clocks and
general-purpose system timing. These operate in either single-shot or auto-reload mode and can
generate interrupts.
The interrupt controller unit (ICU) provides a flexible, low-latency means for requesting interrupts.
The ICU provides full programmability of up to 240 interrupt sources into 31 priority levels. The
ICU takes advantage of a cached priority table and optional routine caching to minimize interrupt
latency. Clock doubling reduces interrupt latency by 40% compared to the 80960JA/JF, and clock
tripling reduces interrupt latency by 20% compared to the 80960JD. Local registers may be
dedicated to high-priority interrupts to further reduce latency. Acting independently from the core,
the ICU compares the priorities of posted interrupts with the current process priority, off-loading
this task from the core. The ICU also supports the integrat ed tim er interrupts.
The 80960Jx features a Halt mode designed to support applicat ions wher e low power consumpt ion
is critical. The halt i nstruct ion shuts down inst ruct ion execution , r esu lting in a power s aving s of up
to 90 percent.
The 80960Jx’s testability features, including ONCE (On-Circuit Emulation) mode and Boundary
Scan (JTAG), provide a powerful environment for design debug and fault diagnosis.
The Solutions960
®
program features a wide variety of development tools which support the i960
processor family. Many of these tools are developed by partner compan ies; s ome are dev el oped by
Intel, such as profile-driven optimizing compilers. For more information on these products, contact
your local Intel representative.
8 Advance Information Datasheet
Figure 2. 80960Jx Block Diagram
80960JA/JF/JD/JT 3.3 V Microprocessor
CLKIN
TAP
Local Register Cache
PLL, Clocks,
Power Mgmt
Boundary Scan
5
8-Set
Global / Local
Register File
SRC2 DESTSRC1
Controller
128
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
Multiply
Divide
Unit
SRC1
SRC2
Instruction Cache
80960JA - 2K
80960JF/JD - 4K
80960JT - 16K
Two-Way Set Associative
Instruction Sequencer
Constants
Execution
and
Address
Generation
Unit
effective
address
DEST
SRC1
SRC2
DEST
Control
Memory
Interface
Unit
32-bit Address
32-bit Data
SRC1
32-bit buses
address / data
DEST
Physical Region
Configuration
Bus
Control Unit
Bus Request
Queues
Two 32-Bit
Timers
Programmable
Interrupt Controller
Memory-Mapped
Register Interface
1K Data RAM
Direct Mapped
Data Cache
80960JA - 1K
80960JF/JD - 2K
80960JT - 4K
Control
21
Address/
Data Bus
32
Interrupt
Port
9
2.1 80960 Processor Core
The 80960Jx family is a scalar implementation of the 80960 Core Architecture. Intel designed this
processor core as a very high performan ce d evice that is also cost-effective. Factors that contribute
to the core’s performance include:
• Core operates at the bus speed with the 80960JA/JF
• Core operates at two or three times the bus speed with the 80960JD and 80960JT respectively
• Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline break latency
• Register and resource scoreboarding allow overlapped instruction execution
• 128-bit register bus speeds local register caching
• Two-way set associative, integrated instruction cache
• Direct-mapped, integrated data cache
• 1 Kbyte integrated data RAM d e livers zero wait state program data
Advance Information Datasheet 9
80960JA/JF/JD/JT 3.3 V Microprocessor
2.2 Burst Bus
A 32-bit high-performance Bus Controller Unit (BCU) interfaces the 80960Jx to external memory
and peripherals. The BCU fetches instructions and transfers data at the rate of up to four 32-bit
words per six clock cycles. The external address/data bus is multiplexed.
Users may configure the 80960Jx’s bus controller to match an application’s fundamental memory
organization. Phy sical bus wi dt h is register-programmed fo r up to eight regions . B yt e o rdering and
data caching are programmed through a gr oup of logical mem ory templates and a def aults register.
The BCU’s features include:
• Multiplexed external bus to minimize pin count
• 32-, 16- and 8-bit bus widths to simplify I/O interfaces
• External ready control for address-to-data, data-to-data and data-t o-n ext-add ress wait s tate ty pes
• Support for big or little endian byte orderin g to faci litate the porting of existing program code
• Unaligned bus accesses performed transparently
• Three-deep load/store queue to decouple the bus from the core
Upon reset, the 80960Jx conducts an internal self-test. Then, before executing its first instruction, it
performs an external bus confidence test by performing a checksum on the first words of the
initialization boot record (IBR).
The user may examine the contents of the caches by executing special cache control instructions.
2.3 Timer Unit
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several
clock rates and generating interrupts. Each is programmed by use of the TU registers. These
memory-mapped registers are addressable on 32-bit boundaries. The timers have a single-shot
mode and auto-reload capabilities for continuous operation. Each timer has an independent
interrupt request to the 80960Jx’s interrupt controller. The TU can generate a fault when
unauthorized writes from user mode are detected. Clock prescaling is supported.
2.4 Priority Interrupt Controller
A programmable interrupt controller manages up to 240 external sources through an 8-bit external
interrupt port. Alternatively, the interrupt inputs may be configured for individual edge- or
level-triggered inputs. The interrupt unit (IU) also accepts interrupts from the two on-chip timer
channels and a single Non-Maskable Interrupt (NMI
priority levels relative to the current process priority.
Low interrupt latency is critical to many embedded applications. As part of its highly flexible
interrupt mechanism, the 80960Jx exploits several techniques to minimize latency:
• Interrupt vectors and interrupt handler routines can be reserved on-chip
• Register frames for high-priority interrupt handlers can be cached on-chip
) pin. Interrupts are serviced according to their
• The interrupt stack can be placed in cacheable memory space
• Interrupt microcode executes at two or three times the bus frequency for the 80960JD and
80960JT respectively
10 Advance Information Datasheet
2.5 Instruction Set Summary
The 80960Jx adds several new instructions to the i960 core architecture. The new instructions are:
• Conditional Move
• Conditional Add
• Conditional Subtract
• Byte Swap
• Halt
• Cache Control
• Interrupt Control
T able 1 identifies the instructions that the 80960Jx supports. Refer to the i960
Developer’s Manual (272483) for a detailed description of each instruction.
2.6 Faults and Debugging
The 80960Jx employs a comprehensive fault model. The processor responds to faults by making
implicit calls to a fault handling routine. Specific information collected for each fault allows the
fault handler to diagnose exceptions and recover appropriately.
80960JA/JF/JD/JT 3.3 V Microprocessor
®
Jx Microprocessor
The processor also has built-in debug capabilities. In software, the 80960J x may be configured to
detect as many as seven different trace event types. Alternatively, mark and fmark instructions
can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are
also available to trap on execution and data addresses.
2.7 Low Power Operation
Intel fabricates the 8096 0Jx using an advanced sub-micron manuf acturing process. The processor’ s
sub-micron topology provides the circuit density for optimal cache size and high operating speeds
while dissipating modest power. The processor also uses dynamic power management to turn off
clocks to unused circuits.
Users may program the 80960Jx to enter Halt mode for maximum power savings. In Halt mode,
the processor core stops completely while the integrated perip herals continue to function, reducing
overall power requirements up to 90 percent. Processor execution resumes from internally or
externally generated interrupts.
Advance Information Datasheet 11
80960JA/JF/JD/JT 3.3 V Microprocessor
2.8 Test Features
The 80960Jx incorporates numerous features which enhance the user’s ability to test both the
processor and the system to which it is attached. These features include ONCE (On-Circuit
Emulation) mode and Boundary Scan (JTAG).
The 80960Jx provides testability features compatible with IEEE Standard Test Access Port and
Boundary Scan Architecture (IEEE Std. 1149.1).
One of the boundary scan instructions, HIGHZ, forces the processor to float all i ts output pins (ONCE
mode). ONCE mode can also be initiated at reset without usi ng the bound ar y scan mechanism.
ONCE mode is useful for board-level testing. This feature allows a mounted 80960Jx to
electrically “remove” itself from a circuit board. This allows for system-level testing where a
remote tester — such as an in-circuit emulator — can exercise the processor system.
The provided test logic does not interfere with component or circuit board behavior and ensures
that components function correctly, connections between various components are correct, and
various components interact correctly on the printed circuit board.
The JT AG Boundary Scan featur e is an attractive alternative to conventional “bed-o f-nails” testing.
It can examine connections which might otherwise be inaccessible to a test system.
2.9 Memory-Mapped Control Registers
The 80960Jx, though compliant with i960 series processor core, has the added advantage of
memory-mapped, internal control registers not found on the i960 Kx, Sx or Cx processors. These
give software the interface to easily read and modify internal control registers.
Each of these registers is accessed as a memory-mapped, 32-bit register. Access is accomplished
through regular memory-format instructions. The processor ensures that these accesses do not
generate external bus cycles.
2.10 Data Types and Memory Addressing Modes
As with all i960 family processors, the 80960Jx instruction set supports several data types and formats:
• Bit
• Bit fields
• Integer (8-, 16-, 32-, 64-bit)
• Ordinal (8-, 16-, 32-, 64-bit unsigned integers)
• Triple word (96 bits)
• Quad word (128 bits)
The 80960Jx provides a full set of addressing modes for C and assembly programming:
• Two Absolute modes
• Five Register Indirect modes
• Index with displacement
• IP with displacement
12 Advance Information Datasheet
Table 1. 80960Jx Instruction Set
Data Movement Arithmetic Logical Bit, Bit Field and Byte
Add
Subtract
Multiply
Divide
Remainder
Load
Store
Move
*Conditional Select
Load Address
Comparison Branch Call/Return Fault
Modulo
Shift
Extended Shift
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
*Conditional Add
*Conditional Subtract
Rotate
80960JA/JF/JD/JT 3.3 V Microprocessor
And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Nor
Exclusive Nor
Not
Nand
Set Bit
Clear Bit
Not Bit
Alter Bit
Scan For Bit
Span Over Bit
Extract
Modify
Scan Byte for Equal
*Byte Swap
Compare
Conditional Compare
Compare and Increment
Compare and Decrement
Test Condition Code
Check Bit
Debug Processor Management Atomic
Modify Trace Controls
Mark
Force Mark
Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB implementations.
Unconditional Branch
Conditional Branch
Compare and Branch
Flush Local Registers
Modify Arithmetic
Controls
Modify Process Controls
*Halt
System Control
*Cache Control
*Interrupt Control
Call
Call Extended
Call System
Return
Branch and Link
Atomic Add
Atomic Modify
Conditional Fault
Synchronize Faults
Advance Information Datasheet 13
80960JA/JF/JD/JT 3.3 V Microprocessor
3.0 Package Information
The 80960Jx is offered with four speeds and three package types. The 132-pin Pin Grid Array
(PGA) device is specified for operation at V
0° to 100°C:
• A80960JT-100 (100 MHz core, 33 MHz bus)
• A80960JT-75 (75 MHz core, 25 MHz bus)
• A80960JD-66 (66 MHz core, 33 MHz bus)
• A80960JD-50 (50 MHz core, 25 MHz bus)
• A80960JD-40 (40 MHz core, 20 MHz bus)
• A80960JD-33 (33 MHz core, 16 MHz bus)
• A80960JA/JF-33 (33 MHz)
• A80960JA/JF-25 (25 MHz)
• A80960JA/JF-16 (16 MHz)
The 132-pin Plastic Quad Flatpack (PQFP) devices are specified for operation at
=3.3V ± 0.15 V over a case temperature range of 0° to 100°C:
V
CC
• NG80960JT-100 (100 MHz core, 33 MHz bus)
• NG80960JT-75 (75 MHz core, 25 MHz bus)
=3.3 V ± 0.15 V over a case temperature range of
CC
• NG80960JD-66 (66 MHz core, 33 MHz bus)
• NG80960JD-50 (50 MHz core, 25 MHz bus)
• NG80960JD-40 (40 MHz core, 20 MHz bus)
• NG80960JD-33 (33 MHz core, 16 MHz bus)
• NG80960JA/JF-33 (33 MHz)
• NG80960JA/JF-25 (25 MHz)
• NG80960JA/JF-16 (16 MHz)
An extended temperature 132-pin Plastic Quad Flatpack (PQFP) device is specified for operation
= 3.3 V ± 0.15 V over a case temperature range of -40° to 100°C:
at V
CC
• TG80960JA-25 (25 MHz)
14 Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
The 196-ball Mini Plastic Ball Grid Array (MPBGA) device is specified for operation at
= 3.3 V ± 0.15 V over a case temperature range of 0° to 100°C:
V
CC
• GD80960JT-100 (100 MHz core, 33 MHz bus)
• GD80960JT-75 (75 MHz core, 25 MHz bus)
• GD80960JD-50 (50 MHz core, 25 MHz bus)
• GD80960JD-40 (40 MHz core, 20 MHz bus)
• GD80960JD-33 (33 MHz core, 16 MHz bus)
• GD80960JA/JF-33 (33 MHz)
• GD80960JA/JF-25 (25 MHz)
• GD80960JA/JF-16 (16 MHz)
For package specifications and information, refer to Intel’s Packaging Handbook (240800).
Advance Information Datasheet 15
80960JA/JF/JD/JT 3.3 V Microprocessor
3.1 Pin Descriptions
This section describes the pins for the 80960Jx in the 132-pin ceramic Pin Grid Array (PGA)
package, 132-lead Plastic Quad Flatpack Package (PQFP) and 196-ball Mini Plastic Ball Grid
Array (MPBGA).
Section 3.1.1, “Functional Pin Definitions”, describes pin function; Section 3.1.2, “80960Jx
132-Lead PGA Pinout”, Section 3.1.3, “80960Jx 132-Lead PQFP Pinout” and Section 3.1.4,
“80960Jx 196-Ball MPBGA P i nou t”, define the signal and p in l o catio ns fo r t h e s upp orte d p ackage
types.
3.1.1 Functional Pin Definitions
T able 2 presents the legend for interpreting the pin descriptions which follow. Pins associated with
the bus interface are described in Table 3 . Pins associated with basic control and test functions are
described in Table 4. Pins associated with the Interrupt Unit are described in Table 5.
Table 2. Pin Description Nomenclature
Symbol Description
I Input pin only.
O Output pin only.
I/O Pin can be either an input or output.
– Pin must be connected as described.
Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation.
S
A (...)
R (...)
H (...)
P (...)
S(E) Edge sensitive input
S(L) Level sensitive input
Asynchronous. Inputs may be asynchronous relative to CLKIN.
A(E) Edge sensitive input
A(L) Level sensitive input
While the processor’s RESET
R(1) is driven to V
R(0) is driven to V
R(Q) is a valid output
R(X) is driven to unknown state
R(H) is pulled up to V
While the processor is in the hold state, the pin:
H(1) is driven to V
H(0) is driven to V
H(Q) Maintains previous state or continues to be a valid output
H(Z) Floats
While the processor is halted, the pin:
P(1) is driven to V
P(0) is driven to V
P(Q) Maintains previous state or continues to be a valid output
CC
SS
CC
SS
CC
SS
pin is asserted, the pin:
CC
16 Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 3. Pin Description — External Bus Signals (Sheet 1 of 3)
NAME TYPE DESCRIPTION
AD31:0
ALE
ALE
ADS
A3:2
I/O
S(L)
R(X)
H(Z)
P(Q)
O
R(0)
H(Z)
P(0)
O
R(1)
H(Z)
P(1)
O
R(1)
H(Z)
P(1)
O
R(X)
H(Z)
P(Q)
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data
T
to and from memory. During an address (
address (bits 0-1 indicate SIZE; see below). During a data (T
data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,
) cycle, bits 31:2 contain a physical word
a
) cycle, read or write
d
AD15:8 and AD7:0. During write operations, unused pins are driven to determinate
values.
T
SIZE, which comprises bits 0-1 of the AD lines during a
number of data transfers during the bus transaction.
cycle, specifies the
a
AD1 AD0 Bus Transfers
0 0 1 Transfer
0 1 2 Transfers
1 0 3 Transfers
1 1 4 Transfers
When the processor enters Halt mode, if the previous bus operation was a:
• write — AD31:2 are driven with the last data value on the AD bus.
• read — AD31:4 are driven with the last address value on the AD bus; AD3:2 are
driven with the value of A3:2 from the last data cycle.
Typically, AD1:0 reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
T
asserted during a
active HIGH and floats to a high impedance state during a hold cycle (T
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE
cycle and deasserted before the beginning of the Td state. It is
a
).
h
is the
inverted version of ALE. This signal gives the 80960Jx a high degree of compatibility
with existing 80960Kx systems.
ADDRESS STROBE indicates a valid address and the start of a new bus access.
The processor asserts ADS
samples ADS
at the end of the cycle.
for the entire Ta cycle. External bus control logic typically
ADDRESS3:2 comprise a partial demultiplexed address bus.
32-bit memory accesses:
partial word address increments with each assertion of RDYRCV
16-bit memory accesses:
driven on the
BE1 pin. The partial short word address increments with each
assertion of RDYRCV
8-bit memory accesses:
driven on BE1:0
RDYRCV
. The partial byte address increments with each assertion of
during a burst.
the processor asserts address bits A3:2 during Ta. The
during a burst.
the processor asserts address bits A3:1 during Ta with A1
during a burst.
the processor asserts address bits A3:0 during Ta, with A1:0
Advance Information Datasheet 17
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 3. Pin Description — External Bus Signals (Sheet 2 of 3)
NAME TYPE DESCRIPTION
BYTE ENABLES select which of up to four data bytes on the bus participate in the
current bus access. Byte enable encoding is dependent on the bus width of the
memory region accessed:
BE3:0
WIDTH/
HLTD1:0
D/C
W/R
DT/R
DEN
O
R(1)
H(Z)
P(1)
O
R(0)
H(Z)
P(1)
O
R(X)
H(Z)
P(Q)
O
R(0)
H(Z)
P(Q)
O
R(0)
H(Z)
P(Q)
O
R(1)
H(Z)
P(1)
32-bit bus:
16-bit bus:
8-bit bus:
The processor asserts byte enables, byte high enable and byte low enable during
Since unaligned bus requests are split into separate bus transactions, these signals
do not toggle during a burst. They remain active through the last T
For accesses to 8- and 16-bit memory, the processor asserts the address bits in
conjunction with A3:2 described above.
WIDTH/HALTED signals denote the physical memory attributes for a bus
transaction:
The processor floats the WIDTH/HLTD pins whenever it relinquishes the bus in
response to a HOLD request, regardless of prior operating state.
DATA/CODE indicates that a bus access is a data access (1) or an instruction
access (0). D/C
0 = instruction access
1 = data access
WRITE/READ specifies, during a
read (0). It is latched on-chip and remains valid during T
0 = read
1 = write
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and f rom the
address/data bus. It is low during T
and T
0 = receive
1 = transmit
DATA ENABLE indicates data transfer cycles during a bus access. DEN
at the start of the first data cycle in a bus access and deasserted at the end of the
last data cycle. DEN
connected to the data bus.
0 = data cycle
1 = not data cycle
enables data on AD31:24
BE3
enables data on AD23:16
BE2
enables data on AD15:8
BE1
enables data on AD7:0
BE0
BE3 becomes Byte High Enable (enables data on AD15:8)
is not used (state is high)
BE2
becomes Address Bit 1 (A1)
BE1
becomes Byte Low Enable (enables data on AD7:0)
BE0
BE3 is not used (state is high)
is not used (state is high)
BE2
becomes Address Bit 1 (A1)
BE1
becomes Address Bit 0 (A0)
BE0
WIDTH/HL TD1 WIDTH/HLTD0
0 0 8 Bits Wide
0 1 16 Bits Wide
1 0 32 Bits Wide
1 1 Processor Halted
has the same timing as W/R.
T
cycle, whether the operation is a write (1) or
a
and Tw/Td cycles for a read; it is high during Ta
cycles for a write. DT/R never changes state when DEN is asserted.
w/Td
a
is used with DT/R to provide control for data transceivers
cycles.
d
cycle.
d
T
is asserted
.
a
18 Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 3. Pin Description — External Bus Signals (Sheet 3 of 3)
NAME TYPE DESCRIPTION
BLAST
RDYRCV
LOCK
ONCE
HOLD
HOLDA
BSTAT
BURST LAST indicates the last transfer in a bus access. BLAST
last data transfer of burst and non-burst accesses. BLAST
O
R(1)
H(Z)
P(1)
S(L)
S(L)
/
R(H)
H(Z)
P(1)
S(L)
R(Q)
H(1)
P(Q)
R(0)
H(Q)
P(0)
wait states are inserted via the RDYRCV
data transfer in a bus cycle.
0 = last data transfer
1 = not last data transfer
READY/RECOVER indicates that data on AD lines can be sampled or removed. If
RDYRCV
by inserting a wait state (T
0 = sample data
1 = don’t sample data
I
The RDYRCV
continues to insert additional recovery states until it samples the pin HIGH. This
function gives slow external devices more time to float their buffers before the
processor begins to drive address again.
0 = insert wait states
1 = recovery complete
BUS LOCK indicates that an atomic read-modify-write operation is in progress. The
LOCK
the last data transfer of the sequence. The processor does not grant HOLDA while it
is asserting LOCK
in semaphore operations.
I/O
0 = Atomic read-modify-write in progress
1 = Atomic read-modify-write not in progress
ONCE MODE: The processor samples the ONCE
LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the
processor stops all clocks and floats all output pins. The pin has a weak internal
pullup which is active during reset to ensure normal operation when the pin is left
unconnected.
0 = ONCE mode enabled
1 = ONCE mode not enabled
HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it asserts
HOLDA, floats the address/data and control lines and enters the T
I
HOLD is deasserted, the processor deasserts HOLDA and enters either the T
state, resuming control of the address/data and control lines.
0 = no hold request
1 = hold request
HOLD ACKNOWLEDGE indicates to an external bus master that the processor has
O
relinquished control of the bus. The processor can grant HOLD requests and enter
the T
0 = hold not acknowledged
1 = hold acknowledged
BUS STATUS indicates that the processor may soon stall unless it has sufficient
access to the bus; see
O
Arbitration logic can examine this signal to determine when an external bus master
should acquire/relinquish the bus.
0 = no potential stall
1 = potential stall
is not asserted during a Td cycle, the Td cycle is extended to the next cycle
pin has another function during the recovery (Tr) state. The processor
output is asserted in the first clock of an atomic operation and deasserted in
. This prevents external agents from accessing memory involved
state during reset and while halted as well as during regular operation.
h
).
w
i960® Jx Microprocessor Developer’s Manual
pin. BLAST becomes inactive after the final
input during reset. If it is asserted
is asserted in the
remains active as long as
state. When
h
(272483).
or Ta
i
Advance Information Datasheet 19
80960JA/JF/JD/JT 3.3 V Microprocessor
T a b l e 4. Pin Description — Processor Control Signals, Test Signals and Power
NAME TYPE DESCRIPTION
CLKIN I
core and the external bus run at the CLKIN rate. All input and output timings are
specified relative to a rising CLKIN edge.
RESET initializes the processor and clears its internal logic. During reset, the
processor places the address/data bus and control output pins in their idle (inactive)
states.
CLOCK INPUT provides the processor’s fundamental time base; both the processor
During reset, the input pins are ignored with the exception of LOCK
I
RESET
A(L)
and HOLD.
The RESET
pin has an internal synchronizer. To ensure predictable processor
initialization during power up, RESET
cycles with V
a minimum of 15 cycles.
and CLKIN stable. On a warm reset, RESET should be asserted for
CC
must be asserted a minimum of 10,000 CLKIN
SELF TEST enables or disables the processor’s internal self-test feature at
initialization. STEST is examined at the end of reset. When STEST is asserted, the
processor performs its internal self-test and the external bus confidence test. When
STEST
I
S(L)
STEST is deasserted, the processor performs only the external bus confidence test.
0 = self test disabled
1 = self test enabled
FAIL indicates a failure of the processor ’s built-in self-test performed during
FAIL
O
R(0)
H(Q)
P(1)
initialization. FAIL
indicate the status of individual tests:
• When self-test passes, the processor deasserts FAIL
user code.
• When self-test fails, the processor asserts FAIL
is asserted immediately upon reset and toggles during self-test to
and begins operation from
and then stops executing.
0 = self test failed
1 = self test passed
TEST CLOCK is a CPU input which provides the clocking function for IEEE1149.1
TCK I
Boundary Scan T esting (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.
I
TDI
TDO
S(L)
R(Q)
HQ)
P(Q)
TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising
edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Por t.
O
TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling
edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At
other times, TDO floats. TDO does not float during ONCE mode.
TEST RESET asynchronously resets the Test Access Port (TA P) controller function
TRST
TMS
V
CC
A(L)
S(L)
VCCPLL –
feature, connect a pulldown resistor between this pin and V
this pin must be connected to V
“Connection Recommendations” on page 40.
I
TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of
; however, no resistor is required. See Section 4.3,
SS
the test logic for IEEE 1149.1 Boundary Scan testing.
– POWER pins intended for external connection to a VCC board plane.
PLL POWER is a separate V
is intended for external connection to the V
add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects
supply pin for the phase lock loop clock generator. It
CC
board plane. In noisy environments,
CC
. If TAP is not used,
SS
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
I
on timing relationships.
5 V REFERENCE VOLTAGE input is the reference voltage for the 5 V-tolerant I/O
VCC5 –
buffers. This signal should be connected to +5 V for use with inputs which exceed
3.3 V. If all inputs are from 3.3 V components, this pin should be connected to 3.3 V.
V
SS
– GROUND pins intended for external connection to a VSS board plane.
NC – NO CONNECT pins. Do not make any system connections to these pins.
/ONCE, STEST
20 Advance Information Datasheet
Table 5. Pin Description — Interrupt Unit Signals
NAME TYPE DESCRIPTION
80960JA/JF/JD/JT 3.3 V Microprocessor
XINT7:0
NMI
I
A(E/L)
I
A(E)
EXTERNAL INTERRUPT pins are used to request interrupt service. The XINT7:0
pins can be configured in three modes:
Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inputs
can be programmed to be level (low) or edge (falling) sensitive.
Expanded Mode: All eight pins act as a vectored interrupt source. The interrupt pins
are level sensitive in this mode.
Mixed Mode:
as the five most significant bits of a vectored source. The least significant bits of the
vectored source are set to 010
Unused external interrupt pins should be connected to V
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI
is the highest priority interrupt source and is falling edge-triggered. If NMI is
unused, it should be connected to V
The XINT7:5 pins act as dedicated sources and the XINT4:0 pins act
internally.
2
.
CC
CC
.
Advance Information Datasheet 21
80960JA/JF/JD/JT 3.3 V Microprocessor
3.1.2 80960Jx 132-Lead PGA Pinout
Figure 3. 132-Lead Pin Grid Array Bottom View - Pins Facing Up
1413121110987654321
P
AD25
AD18AD19AD22
CC
CC
CC
CC
CC
CC
V
V
V
V
V
V
AD13V
CC
AD6AD11
N
AD27
AD20AD24AD26
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
AD3AD7AD10V
M
AD29AD30 NC
AD21AD23
AD14AD15AD16AD17
L
BE3BE2
AD28
K
V
V
CC
AD31
SS
J
V
V
CC
H
G
F
E
D
C
B
V
CC
CC
V
CC
V
CC
V
CC
LOCK/
ONCE
A
V
V
V
HOLDA
WIDTH/ADS
HLTD1
BE1
SS
BE0V
SS
ALEV
SS
BSTAT
SS
DEN
SS
DT/RV
SS
A2
A3 XINT1
V
V
V
HLTD0
NCTDOWIDTH/D/CW/R XINT4
NCNCALE
SS
SS
V
V
CC
CC
SS
SS
V
V
CC
CC
AD9AD12
AD8
AD5
AD2
NC
VCCPLL
NC
RDYRCV
RESET
TDI
XINT0
XINT6V
XINT5XINT7NMI
AD4
AD1
V
V
V
V
V
V
TCKXINT3
AD0
V
CC
V
CC
SS
V
CC
SS
CLKINV
SS
V
CC
SS
V
CC
SS
V
CC
SS
V
CC
SS
NCSTESTTRSTHOLDNCFAIL VCC5BLAST
NC
TMSXINT2
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1413121110987654321
22 Advance Information Datasheet
80960JA/JF/JD/JT 3.3 V Microprocessor
Figure 4. 132-Lead Pin Grid Array Top View - Pins Facing Down
1413121110987654321
P
AD6 AD11
N
M
L
K
J
H
G
F
E
D
C
B
A
AD3 AD7 AD10 VSSVSSVSSVSSV
AD0
VCCAD1
VCCV
VCCV
CLKIN VSSVCCPLL
VCCVSSNC
V
CC
V
CC
VCCV
NC STEST TRST HOLD NC FAILVCC5 BLAST
NC
TMS XINT2
AD13 VCCVCCVCCVCCV
AD9 AD12
AD4
AD8
AD5
AD2
SS
NC
SS
AD14 AD15 AD16 AD17
A80960Jx
M
i
V
RDYRCV
SS
RESET
V
SS
TDI
SS
XINT0
TCK
XINT4
XINT3
XINT5 XINT7 NMI VCCVCCVCCV
XXXXXXXX SS
XINT6 VSSVSSVSSVSSNC TDO WIDTH/ D/C W/R
©19xx
CCVCCVCC
SSVSSVSS
CC
AD18 AD19 AD22
AD20 AD24 AD26
AD21 AD23
BSTAT
A2
A3XINT1
HLTD0
NC NC ALE
AD25
AD27
AD29 AD30NC
AD28 BE3 BE2
V
AD31
BE1 V
BE0
ALE V
DEN
DT/R VSSV
V
SS
SSVCC
V
V
SS
V
SS
V
SSVCC
V
V
SS
LOCK/
HOLDA
ONCE
WIDTH/ ADS
HLTD1
CC
CC
CC
CC
CC
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1413121110987654321
Advance Information Datasheet 23
80960JA/JF/JD/JT 3.3 V Microprocessor
Table 6. 132-Lead PGA Pinout — In Signal Order
Signal Pin Signal Pin Signal Pin Signal Pin
A2 C5 AD31 K3 TDO B4 V
A3 C4 ADS
AD0 M14 ALE G3 TRST
AD1 L13 ALE
AD2 K12 BE0
AD3 N14 BE1
AD4 M13 BE2
AD5 L12 BE3
AD6 P14 BLAST
AD7 N13 BSTAT F3 V
AD8 M12 CLKIN H14 V
AD9 M11 D/C
AD10 N12 DEN
AD11 P13 DT/R
AD12 M10 FAIL
AD13 P12 HOLD C9 V
AD14 M9 HOLDA C2 V
AD15 M8 LOCK
/ONCE C1 V
AD16 M7 NC A4 V
AD17 M6 NC A5 V
AD18 P4 NC B5 V
AD19 P3 NC B14 V
AD20 N4 NC C8 V
AD21 M5 NC C14 V
AD22 P2 NC G12 V
AD23 M4 NC J12 V
AD24 N3 NC M3 V
AD25 P1 NMI
AD26 N2 RDYRCV
AD27 N1 RESET
AD28 L3 STEST C13 V
AD29 M2 TCK B13 V
AD30 M1 TDI D12 V
A1 TMS A14 V
C12 V
A3 V
H3 V
J3 V
L1 V
L2 V
C3 V
B2 V
E3 V
D3 V
C6 V
A10 V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
A6 V
A7 V
A8 V
A9 V
D1 V
D14 V
E1 V
E14 V
F1 V
F14 V
G1 V
G14 V
H1 V
J1 V
J14 V
K1 V
K14 V
L14 V
P5 V
P6 W/R B1
P7 WIDTH/HLTD0 B3
P8 WIDTH/HLTD1 A2
P9 XINT0 C11
P10 XINT1 C10
P11 XINT2 A13
F12 VCCPLL H12 XINT3 B12
E12 VCC5 C7 XINT4 B11
SS
SS
SS
B6 XINT5 A12
B7 XINT6 B10
B8 XINT7 A11
NOTE: Do not connect any external logic to pins marked NC (no connect pins).
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
B9
D2
D13
E2
E13
F2
F13
G2
G13
H2
H13
J2
J13
K2
K13
N5
N6
N7
N8
N9
N10
N11
24 Advance Information Datasheet
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