Intel Corporation TE28F400BX-T80, TE28F400BX-B80 Datasheet

4-MBIT (256K X 16, 512K X 8)

BOOT BLOCK

FLASH MEMORY FAMILY

28F400BX-T/B, 28F004BX-T/B

Y

x8/x16 Input/Output Architecture
Ð 28F400BX-T, 28F400BX-B
Ð For High Performance and High

Integration 16-bit and 32-bit CPUs

Y

x8-only Input/Output Architecture
Ð 28F004BX-T, 28F004BX-B
Ð For Space Constrained 8-bit

Applications

Y

Upgradeable to Intel’s Smart Voltage
Products

Y

Optimized High-Density Blocked
Architecture
Ð One 16-KB Protected Boot Block
Ð Two 8-KB Parameter Blocks
Ð One 96-KB Main Block
Ð Three 128-KB Main Blocks
Ð Top or Bottom Boot Locations

Y

Extended Cycling Capability
Ð 100,000 Block Erase Cycles

Y

Automated Word/Byte Write and Block
Erase
Ð Command User Interface
Ð Status Registers
Ð Erase Suspend Capability

Y

SRAM-Compatible Write Interface

Y

Automatic Power Savings Feature
Ð 1 mA Typical I

Active Current in

CC

Static Operation

Y

Very High-Performance Read
Ð 60/80/120 ns Maximum Access Time
Ð 30/40/40 ns Maximum Output Enable

Time

Y

Low Power Consumption
Ð 20 mA Typical Active Read Current

Y

Reset/Deep Power-Down Input
Ð 0.2 mAI

CC

Typical

Ð Acts as Reset for Boot Operations

Y

Extended Temperature Operation

b

Ð

40§Ctoa85§C

Y

Write Protection for Boot Block

Y

Hardware Data Protection Feature
Ð Erase/Write Lockout During Power

Transitions

Y

Industry Standard Surface Mount
Packaging
Ð 28F400BX: JEDEC ROM Compatible

44-Lead PSOP
56-Lead TSOP

Ð 28F004BX: 40-Lead TSOP

Y

12V Word/Byte Write and Block Erase

e

ÐV
ÐV

Y

ETOXTMIII Flash Technology

12Vg5% Standard

PP

e

12Vg10% Option

PP

Ð 5V Read

*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

November 1995COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 290451-005

28F400BX-T/B, 28F004BX-T/B

Intel’s 4-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selec­tive erasure, automated write and erase operations and standard microprocessor interface. The 4-Mbit Flash
Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16 input/out­put control, very high speed, low power, an industry standard ROM compatible pinout and surface mount
packaging. The 4-Mbit flash family is an easy upgrade from Intel’s 2-Mbit Boot Block Flash Memory Family.

The Intel 28F400BX-T/B are 16-bit wide flash memory offerings. These high density flash memories provide
user selectable bus operation for either 8-bit or 16-bit applications. The 28F400BX-T and 28F400BX-B are
4,194,304-bit non-volatile memories organized as either 524,288 bytes or 262,144 words of information. They
are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industry
standard ROM/EPROM pinout.

The Intel 28F004BX-T/B are 8-bit wide flash memories with 4,194,304 bits organized as 524,288 bytes of
information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable
systems.

These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The 28F400BX-T/28F004BX-T provide block locations compatible with
Intel’s MCS-186 family, 80286, i386
28F004BX-B provide compatibility with Intel’s 80960KX and 80960SX families as well as other embedded
microprocessors.

The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 60 ns, these 4-Mbit flash devices are very high performance memories which
interface at zero-wait-state to a wide range of microprocessors and microcontrollers. A deep power-down
mode lowers the total V
For very low power applications using a 3.3V supply, refer to the Intel 28F400BL-T/B, 28F004BL-T/B 4-Mbit

power consumption to 1 mW. This is critical in handheld battery powered systems.

CC

Boot Block Flash Memory Family datasheet.

Manufactured on Intel’s 0.8 micron ETOX III process, the 4-Mbit flash memory family provides world class
quality, reliability and cost-effectiveness at the 4-Mbit density level.

TM

, i486TM, i860TMand 80960CA microprocessors. The 28F400BX-B/

2

28F400BX-T/B, 28F004BX-T/B

1.0 PRODUCT FAMILY OVERVIEW

Throughout this datasheet the 28F400BX refers to
both the 28F400BX-T and 28F400BX-B devices and
28F004BX refers to both the 28F004BX-T and
28F004BX-B devices. The 4-Mbit flash memory fam­ily refers to both the 28F400BX and 28F004BX prod­ucts. This datasheet comprises the specifications for
four separate products in the 4-Mbit flash memory
family. Section 1 provides an overview of the 4-Mbit
flash memory family including applications, pinouts
and pin descriptions. Sections 2 and 3 describe in
detail the specific memory organizations for the
28F400BX and 28F004BX products respectively.
Section 4 combines a description of the family’s
principles of operations. Finally Section 5 describes
the family’s operating specifications.

Product Family

X8/X16 Products X8-Only Products

28F400BX-T 28F004BX-T

28F400BX-B 28F004BX-B

1.1 Designing for Upgrade to
SmartVoltage Products

Today’s high volume boot block products are up­gradable to Intel’s SmartVoltage boot block prod­ucts that provide program and erase operation at 5V
or 12V V
Intel’s SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this data sheet:

1. DU pin is replaced by WP

to lock and unlock the boot block with logic sig­nals.

2. 5V Program/Erase operation uses proven pro-

gram and erase techniques with 5V
plied to V

3. Enhanced circuits optimize performance at 3.3V

V

CC

Refer to the 2, 4 or 8 Mbit SmartVoltage Boot Block
Flash Memory Data Sheets for complete specifica­tions.

When you design with 12V V
you should provide the capability in your board de­sign to upgrade to SmartVoltage products.

and read operation at 3V or 5V VCC.

PP

Ý

to provide a means

.

PP

.

boot block products

PP

g

10% ap-

Follow these guidelines to ensure compatibility:

Ý

1. Connect DU (WP
a control signal or to V

on SmartVoltage products) to

or GND.

CC

2. If adding a switch on VPPfor write protection,
switch to GND for complete write protection.

3. Allow for connecting 5V to V
12V from the V

line, if desired.

PP

and disconnect

PP

1.2 Main Features

The 28F400BX/28F004BX boot block flash memory
family is a very high performance 4-Mbit (4,194,304
bit) memory family organized as either 256 KWords
(262,144 words) of 16 bits each or 512 Kbytes
(524,288 bytes) of 8 bits each.

Seven Separately Erasable Blocks including a
Hardware-Lockable boot block (16,384 Bytes),
Two parameter blocks (8,192 Bytes each) and
Four main blocks (1 block of 98,304 Bytes and 3

blocks of 131,072 Bytes) are included on the 4-Mbit
family. An erase operation erases one of the main
blocks in typically 2.4 seconds and the boot or pa­rameter blocks in typically 1.0 seconds independent
of the remaining blocks. Each block can be indepen­dently erased and programmed 100,000 times.

The Boot Block is located at either the top
(28F400BX-T, 28F004BX-T) or the bottom
(28F400BX-B, 28F004BX-B) of the address map in
order to accommodate different microprocessor pro­tocols for boot code location. The hardware locka-
ble boot block provides the most secure code stor­age. The boot block is intended to store the kernel
code required for booting-up a system. When the

Ý

RP

pin is between 11.4V and 12.6V the boot block
is unlocked and program and erase operations can
be performed. When the RP
the boot block is locked and program and erase op­erations to the boot block are ignored.

The 28F400BX products are available in the ROM/
EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package and
the 56-Lead TSOP (Thin Small Outline, 1.2mm thick)
package as shown in Figures 3 and 4. The
28F004BX products are available in the 40-Lead
TSOP (1.2mm thick) package as shown in Figure 5.

The Command User Interface (CUI) serves as the
interface between the microprocessor or microcon­troller and the internal operation of the 28F400BX
and 28F004BX flash memory products.

Ý

pin is at or below 6.5V

3

28F400BX-T/B, 28F004BX-T/B

Program and Erase Automation allows program

and erase operations to be executed using a two­write command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, there­by unburdening the microprocessor or microcontrol­ler. Writing of memory data is performed in word or
byte increments for the 28F400BX family and in byte
increments for the 28F004BX family typically within
9 ms which is a 100% improvement over current
flash memory products.

The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.

Maximum Access Time of 60 ns (t
over the commercial temperature range (0

C), 5% VCCsupply voltage range (4.75V to

70

§

) is achieved

ACC

Cto

§

5.25V) and 30 pF output load. Maximum Access
Time of 70 ns (t
cial temperature range, 10% V
to 5.5V) and 100 pF output load.

I

maximum Program current is 40 mA for x16

PP

operation and 30 mA for x8 operation. I
current is 30 mA maximum. V
gramming voltage is 11.4V to 12.6V (V

g

5%) under all operating conditions. As an op-

tion, V

e

can also vary between 10.8V to 13.2V (V

PP

12Vg10%) with a guaranteed number of 100

) is achieved over the commer-

ACC

supply range (4.5V

CC

erase and pro-

PP

PP

PP

Erase

e

12V

PP

block erase cycles.

Typical I
for the X16 products (28F400BX). Typical I
tive Current of 20 mA is achieved for the X8 prod-

ucts (28F400BX, 28F004BX). Refer to the I
current derating curves in this datasheet.

Active Current of 25 mA is achieved

CC

CC

CC

active

Ac-

Ý

When the CE

Ý

BYTE

and RPÝpins are at VCCand the

pin (28F400BX-only) is at either VCCor

GND the CMOS Standby mode is enabled where

is typically 50 mA.

I

CC

A Deep Power-Down Mode is enabled when the

Ý

RP

pin is at ground minimizing power consumption
and providing write protection during power-up con­ditions. I
is 0.20 mA typical. An initial maximum access time

current during deep power-down mode

CC

or Reset Time of 300 ns is required from RP
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 215 ns until
writes to the Command User Interface are recog­nized. When RP

Ý

is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature pre­vents data corruption and protects the code stored
in the device during system reset. The system Reset

Ý

pin can be tied to RP

to reset the memory to nor­mal read mode upon activation of the Reset pin.
With on-chip program/erase automation in the
4-Mbit family and the RP

Ý

functionality for data pro­tection, when the CPU is reset and even if a program
or erase command is issued, the device will not rec­ognize any operation until RP

Ý

returns to its normal

state.

For the 28F400BX, Byte-wide or Word-wide In­put/Output Control is possible by controlling the

Ý

BYTE

pin. When the BYTEÝpin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through DQ[0:7]. During the byte­wide mode, DQ[8:14]are tri-stated and DQ15/A-1
becomes the lowest order address pin. When the

Ý

BYTE

pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DQ[0:15].

Ý

The 4-Mbit boot block flash memory family is also
designed with an Automatic Power Savings (APS)
feature to minimize system battery current drain and
allows for very low power designs. Once the device
is accessed to read array data, APS mode will imme­diately put the memory in static mode of operation
where I
next read is initiated.

active current is typically 1 mA until the

CC

4

28F400BX-T/B, 28F004BX-T/B

1.3 Applications

The 4-Mbit boot block flash memory family com­bines high density, high performance, cost-effective
flash memories with blocking and hardware protec­tion capabilities. Its flexibility and versatility will re­duce costs throughout the product life cycle. Flash
memory is ideal for Just-In-Time production flow, re­ducing system inventory and costs, and eliminating
component handling during the production phase.

During the product life cycle, when code updates or
feature enhancements become necessary, flash
memory will reduce the update costs by allowing ei­ther a user-performed code change via floppy disk
or a remote code change via a serial link. The 4-Mbit
boot block flash memory family provides full func­tion, blocked flash memories suitable for a wide
range of applications. These applications include
Extended PC BIOS and ROM-able applications
storage, Digital Cellular Phone program and data
storage, Telecommunication boot/firmware, Print-
er firmware/font storage and various other embed­ded applications where both program and data stor­age are required.

Reprogrammable systems such as personal com­puters, are ideal applications for the 4-Mbit flash
memory products. Portable and handheld personal
computer applications are becoming more complex
with the addition of power management software to
take advantage of the latest microprocessor tech­nology, the availability of ROM-based application
software, pen tablet code for electronic hand writing,
and diagnostic code. Figure 1 shows an example of
a 28F400BX-T application.

This increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped. The 4-Mbit flash memory
products provide an inexpensive update solution for
the notebook and handheld personal computers
while extending their product lifetime. Furthermore,
the 4-Mbit flash memory products’ power-down
mode provides added flexibility for these battery­operated portable designs which require operation
at very low power levels.

The 4-Mbit flash memory products also provide ex­cellent design solutions for Digital Cellular Phone
and Telecommunication switching applications re­quiring high performance, high density storage capa­bility coupled with modular software designs, and a
small form factor package (X8-only bus). The
4-Mbit’s blocking scheme allows for an easy seg­mentation of the embedded code with; 16 Kbytes of
Hardware-Protected Boot code, 4 Main Blocks of
program code and 2 Parameter Blocks of 8 Kbytes
each for frequently updatable data storage and diag­nostic messages (e.g., phone numbers, authoriza­tion codes). Figure 2 is an example of such an appli­cation with the 28F004BX-T.

These are a few actual examples of the wide range
of applications for the 4-Mbit Boot Block flash mem­ory family which enable system designers achieve
the best possible product design. Only your imagina­tion limits the applicability of such a versatile product
family.

5

28F400BX-T/B, 28F004BX-T/B

Figure 1. 28F400BX Interface to Intel386TMEX Embedded Processor

290451– 4

290451– 24

Figure 2. 28F004BX Interface to INTEL 80C188EB 8-Bit Embedded Processor

6

28F400BX-T/B, 28F004BX-T/B

1.4 Pinouts

The 28F400BX 44-Lead PSOP pinout follows the in­dustry standard ROM/EPROM pinout as shown in
Figure 3. Furthermore, the 28F400BX 56-Lead
TSOP pinout shown in Figure 4 provides density up­grades to future higher density boot block memories.

The 28F004BX 40-Lead TSOP pinout shown in Fig­ure 5 is 100% compatible and provides a density
upgrade for the 2-Mbit Boot Block flash memory or
the 28F002BX.

Figure 3. PSOP Lead Configuration for x8/x16 28F400BX

290451– 25

7

28F400BX-T/B, 28F004BX-T/B

Figure 4. TSOP Lead Configuration for x8/x16 28F400BX

290451– 3

290451– 20

Figure 5. TSOP Lead Configuration for x8 28F004BX

8

28F400BX-T/B, 28F004BX-T/B

1.5 28F400BX Pin Descriptions

Symbol Type Name and Function

A0–A

17

A

9

DQ0–DQ7I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle during a

DQ8–DQ15I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle during a

Ý

CE

Ý

RP

Ý

OE

Ý

WE

Ý

BYTE

V

PP

V

CC

GND GROUND: For all internal circuitry.

NC NO CONNECT: Pin may be driven or left floating.

DU DON’T USE PIN: Pin should not be connected to anything.

I ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write

cycle.

I ADDRESS INPUT: When A9is at 12V the signature mode is accessed. During this mode A

decodes between the manufacturer and device ID’s. When BYTEÝis at a logic low only the
lower byte of the signatures are read. DQ

Ý

is low.

BYTE

program command. Inputs commands to the command user interface when CE

/A

is a don’t care in the signature mode when

b

15

1

Ý

and WE
are active. Data is internally latched during the write and program cycles. Outputs array,
Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled.

program command. Data is internally latched during the write and program cycles. Outputs
array data. The data pins float to tri-state when the chip is deselected or the outputs are
disabled as in the byte-wide mode (BYTE
becomes the lowest order address for data output on DQ0-DQ7.

e

Ý

‘‘0’’). In the byte-wide mode DQ15/A

b

1

I CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense

amplifiers. CE
consumption to standby levels. If CE
standby current will increase due to current flow through the CE

Ý

is active low; CEÝhigh deselects the memory device and reduces power

Ý

and RPÝare high, but not at a CMOS high level, the

Ý

and RPÝinput stages.

I RESET/DEEP POWER-DOWN: Provides three-state control. Puts the device in deep power-

down mode. Locks the boot block from program/erase.

Ý

When RP

is at logic high level and equals 6.5V maximum the boot block is locked and

cannot be programmed or erased.

e

Ý

When RP

11.4V minimum the boot block is unlocked and can be programmed or

erased.

Ý

When RP

is at a logic low level the boot block is locked, the deep power-down mode is
enabled and the WSM is reset preventing any blocks from being programmed or erased,
therefore providing data protection during power transitions.

Ý

When RP

transitions from logic low to logic high the flash memory enters the read-array
mode.

I OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a read cycle.

Ý

is active low.

OE

I WRITE ENABLE: Controls writes to the Command Register and array blocks. WEÝis active

low. Addresses and data are latched on the rising edge of the WEÝpulse.

I BYTEÝENABLE: Controls whether the device operates in the byte-wide mode (x8) or the

Ý

word-wide mode (x16). BYTE
current in the standby mode. BYTE
and programmed on DQ
decodes between the upper and lower byte. DQ
mode. BYTE

e

Ý

‘‘1’’ enables the word-wide mode where data is read and programmed on

pin must be controlled at CMOS levels to meet 100A CMOS

e

Ý

–DQ7and DQ15/A

0

‘‘0’’ enables the byte-wide mode, where data is read

becomes the lowest order address that

b

1

–DQ14are tri-stated during the byte-wide

8

DQ0–DQ15.

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming
data in each block.

Note: V

k

V

PP

memory contents cannot be altered.

PPLMAX

DEVICE POWER SUPPLY (5Vg10%, 5Vg5%)

0

Ý

9

28F400BX-T/B, 28F004BX-T/B

1.6 28F004BX Pin Descriptions

Symbol Type Name and Function

A0–A

18

A

9

DQ0–DQ7I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle

Ý

CE

Ý

RP

Ý

OE

Ý

WE

V

PP

V

CC

GND GROUND: For all internal circuitry.

NC NO CONNECT: Pin may be driven or left floating.

DU DON’T USE PIN: Pin should not be connected to anything.

I ADDRESS INPUTS for memory addresses. Addresses are internally latched during

a write cycle.

I ADDRESS INPUT: When A9is at 12V the signature mode is accessed. During this

mode A

decodes between the manufacturer and device ID’s.

0

during a program command. Inputs commands to the command user interface when

Ý

and WEÝare active. Data is internally latched during the write and program

CE
cycles. Outputs array, Intelligent Identifier and status register data. The data pins
float to tri-state when the chip is deselected or the outputs are disabled.

I CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

Ý

sense amplifiers. CE
reduces power consumption to standby levels. If CE

is active low; CEÝhigh deselects the memory device and

Ý

and RPÝare high, but not at

a CMOS high level, the standby current will increase due to current flow through the

Ý

and RPÝinput stages.

CE

I RESET/DEEP POWERDOWN: Provides Three-State control. Puts the device in

deep power-down mode. Locks the Boot Block from program/erase.

When RP

Ý

is at logic high level and equals 6.5V maximum the Boot Block is locked

and cannot be programmed or erased.

e

Ý

When RP

11.4V minimum the Boot Block is unlocked and can be programmed

or erased.

When RP

Ý

is at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power transitions.
When RP

Ý

transitions from logic low to logic high, the flash memory enters the
read-array mode.

I OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

read cycle. OEÝis active low.

I WRITE ENABLE: Controls writes to the Command Register and array blocks. WE

is active low. Addresses and data are latched on the rising edge of the WEÝpulse.

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.

NOTE: V

k

V

PP

memory contents cannot be altered.

PPLMAX

DEVICE POWER SUPPLY (5Vg10%, 5Vg5%)

Ý

10

28F400BX-T/B, 28F004BX-T/B

2.0 28F400BX WORD/BYTE-WIDE PRODUCTS DESCRIPTION

290451– 1

Figure 6. 28F400BX Word/Byte Block Diagram

11

28F400BX-T/B, 28F004BX-T/B

2.1 28F400BX Memory Organization

2.1.1 BLOCKING

The 28F400BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block ad­dress range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F400BX is
a random read/write memory, only erasure is per­formed by block.

2.1.1.1 Boot Block Operation and Data
Protection

The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow­er failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RP
be erased and written when RP
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address lo­cations of the boot block for the 28F400BX-T and
28F400BX-B.

2.1.1.2 Parameter Block Operation

The 28F400BX has 2 parameter blocks (8-Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The pa­rameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. The parameter blocks pro­vide for more efficient memory utilization when deal­ing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for ad­dress locations of the parameter blocks for the
28F400BX-T and 28F400BX-B.

2.1.1.3 Main Block Operation

Four main blocks of memory exist on the 28F400BX
(3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks). See
the following section on Block Memory Map for the
address location of these blocks for the 28F400BX-T
and 28F400BX-B products.

Ý

is not at 12V. The boot block can

Ý

is held at 12V for

2.1.2 BLOCK MEMORY MAP

Two versions of the 28F400BX product exist to sup­port two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F400BX-T
memory map is inverted from the 28F400BX-B
memory map.

2.1.2.1. 28F400BX-B Memory Map

The 28F400BX-B device has the 16-Kbyte boot
block located from 00000H to 01FFFH to accommo­date those microprocessors that boot from the bot­tom of the address map at 00000H. In the
28F400BX-B the first 8-Kbyte parameter block re­sides in memory space from 02000H to 02FFFH.
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96-Kbyte main block resides in memory space from
04000H to 0FFFFH. The three 128-Kbyte main
block resides in memory space from 10000H to
1FFFFH, 20000H to 2FFFFH and 30000H to
3FFFFH (word locations). See Figure 7.

(Word Addresses)

3FFFFH

128-Kbyte MAIN BLOCK

30000H

2FFFFH

128-Kbyte MAIN BLOCK

20000H

1FFFFH

128-Kbyte MAIN BLOCK

10000H

0FFFFH

96-Kbyte MAIN BLOCK

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

00000H

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

Figure 7. 28F400BX-B Memory Map

12

2.1.2.2 28F400BX-T Memory Map

The 28F400BX-T device has the 16-Kbyte boot
block located from 3E000H to 3FFFFH to accom­modate those microprocessors that boot from the
top of the address map. In the 28F400BX-T the first
8-Kbyte parameter block resides in memory space
from 3D000H to 3DFFFH. The second 8-Kbyte pa­rameter block resides in memory space from
3C000H to 3CFFFH. The 96-Kbyte main block re­sides in memory space from 30000H to 3BFFFH.
The three 128-Kbyte main blocks reside in memory
space from 20000H to 2FFFFH, 10000H to 1FFFFH
and 00000H to 0FFFFH as shown below in Figure 8.

28F400BX-T/B, 28F004BX-T/B

(Word Addresses)

3FFFFH

3E000H

3DFFFH

3D000H

3CFFFH

3C000H

3BFFFH

30000H

2FFFFH

20000H

1FFFFH

10000H

0FFFFH

00000H

Figure 8. 28F400BX-T Memory Map

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

13

28F400BX-T/B, 28F004BX-T/B

3.0 28F004BX PRODUCT DESCRIPTION

290451– 19

14

Figure 9. 28F004BX Byte-Wide Block Diagram

28F400BX-T/B, 28F004BX-T/B

3.1 28F004BX Memory Organization

3.1.1 BLOCKING

The 28F004BX uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block ad­dress range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F004BX is
a random read/write memory, only erasure is per­formed by block.

3.1.1.1 Boot Block Operation and Data
Protection

The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow­er failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being programmed
or erased when RP
can be erased and programmed when RP
at 12V for the duration of the erase or program oper­ation. This allows customers to change the boot
code when necessary while still providing security
when needed. See the Block Memory Map section
for address locations of the boot block for the
28F004BX-T and 28F004BX-B.

3.1.1.2 Parameter Block Operation

The 28F004BX has 2 parameter blocks (8-Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The pa­rameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. Parameter blocks provide
for more efficient memory utilization when dealing
with small parameter changes versus regularly
blocked devices. See the Block Memory Map sec­tion for address locations of the parameter blocks
for the 28F004BX-T and 28F004BX-B.

3.1.1.3 Main Block Operation

Four main blocks of memory exist on the 28F004BX

c

(3

128-Kbyte blocks and 1c96-Kbyte blocks).
See the following section on Block Memory Map for
the address location of these blocks for the
28F004BX-T and 28F004BX-B.

Ý

is not at 12V. The boot block

Ý

is held

3.1.2 BLOCK MEMORY MAP

Two versions of the 28F004BX product exist to sup­port two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F004BX-T
memory map is inverted from the 28F004BX-B
memory map.

3.1.2.1 28F004BX-B Memory Map

The 28F004BX-B device has the 16-Kbyte boot
block located from 00000H to 03FFFH to accommo­date those microprocessors that boot from the bot­tom of the address map at 00000H. In the
28F004BX-B the first 8-Kbyte parameter block re­sides in memory from 04000H to 05FFFH. The sec­ond 8-Kbyte parameter block resides in memory
space from 06000H to 07FFFH. The 96-Kbyte main
block resides in memory space from 08000H to
1FFFFH. The three 128-Kbyte main block reside in
memory space from 20000H to 3FFFFH, 40000H to
5FFFFH and 60000H to 7FFFFH. See Figure 10.

7FFFFH

128-Kbyte MAIN BLOCK

60000H

5FFFFH

128-Kbyte MAIN BLOCK

40000H

3FFFFH

128-Kbyte MAIN BLOCK

20000H

1FFFFH

96-Kbyte MAIN BLOCK

08000H

07FFFH

06000H

05FFFH

04000H

03FFFH

00000H

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

Figure 10. 28F004BX-B Memory Map

15