Intel Corporation TN28F020-150, TN28F020-120, TE28F020-150, TE28F020-120 Datasheet

December 1997

28F020 2048K (256K X 8) CMOS

FLASH MEMORY

Flash Electrical Chip-Erase

 2 Second Typical Chip-Erase

Quick-Pulse Programming Algorithm

 10 µS Typical Byte-Program  4 second Chip-Program

100,000 Erase/Program Cycles

12.0 V ±5% V

High-Performance Read

 90 ns Maximum Access Time

CMOS Low Power Consumption

 10 mA Typical Active Current  50 µA Typical Standby Current  0 Watts Data Retention Power

Integrated Program/Erase Stop Timer

Intel’s 28F020 CMOS flash memory offers the most cost-effective and reliable alternative for read/write random access nonvolatile memory. The 28F020 adds electrical chip-erasure and reprogramming to familiar EPROM technology. Memory contents can be rewritten: in a t est soc ket ; i n a PROM-program mer s ock et; onboard during subassembly tes t; in-system during final test; and in-system after sale. The 28F020 increases memory flexibility, while contributing to time and cost savings.

Command Register Architecture for Microprocessor/Microcontroller Compatible Write Interface

Noise Immunity Features

 ±10% V  Maximum Latch-Up Immunity

through EPI Processing

ETOX™ Nonvolatile Flash Technology

 EPROM-Compatible Process Base  High-Volume Manufacturing

Experience

JEDEC-Standard Pinouts

 32-Pin Plastic Dip  32-Lead PLCC  32-Lead TSOP

(See Packaging Spec., Order #231369)

Extended Temperature Options

Tolerance

The 28F020 is a 2048-kilobit nonvolat ile memory organiz ed as 262,144 bytes of eight bits. Intel’s 28F020 is offered in 32-pin plastic DIP, 32-lead PLCC, and 32-lead TSOP packages. Pin assignments conform to JEDEC standards for byte-wide EPROMs.

Extended erase and program cycling capability is designed into Intel’s ETOX™ (EPROM Tunnel Oxide) process technology. A dvanced oxide processing, an optimized t unneling structure, and lower electric fiel d combine to extend reliabl e cycling beyond that of traditional EEPROMs. With the 12.0 V V 28F020 performs 100,000 erase and program cycles—well within the time limits of the quick-pulse programming and quick-erase algorithms.

Intel’s 28F020 employs adv anced CMOS circuitry for systems requiring high-performance access speeds , low power consumption, and immunity to noise. Its 90 ns access t ime provides zero wait -state performanc e for a wide range of microprocessors and microcontrollers. M aximum standby current of 100 µA translat es into power savings when the device is deselected. Finally, the highest degree of latch-up protection is achieved through Intel’s uni que EP I proc ess ing. P revent ion of latc h-up is provided f or st ress es up t o 100 mA on address and data pins, from –1 V to V

With Intel’s ETOX proc ess technology bas e, the 28F020 builds on years of E PROM experience to yield the highest levels of quality, reliability, and cost-effectiveness.

+ 1 V.

Order Number: 290245-009

supply, the

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditi ons of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. The 28F020 may contain design defects or errors known as errata. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be

obtained from: Intel Corporation

P.O. Box 5937 Denver, CO 80217-9808

or call 1-800-548-4725

* Third-party brands and names are the property of their respective owners.

E 28F020

PAGE PAGE

1.0 APPLICATIONS..............................................5

2.0 PRINCIPLES OF OPERATION .......................8

2.1 Integrated Stop Timer ..................................8

2.2 Write Protection ...........................................9

2.2.1 Bus Operations......................................9

2.2.1.1 Read...............................................9

2.2.1.2 Output Disable..............................10

2.2.1.3 Standby ........................................10

2.2.1.4 Intelligent Identifier Operation.......10

2.2.1.5 Write.............................................10

2.2.2 Command Definitions..........................10

2.2.2.1 Read Command............................11

2.2.2.2 Intelligent Identifier Command ......11

2.2.2.3 Set-Up Erase/Erase Commands...12

2.2.2.4 Erase Verify Command.................12

2.2.2.5 Set-Up Program/Program

Commands ..................................12

2.2.2.6 Program Verify Command ............12

2.2.2.7 Reset Command...........................13

2.2.3 Extended Erase/Program Cycling........13

2.2.4 Quick-Pulse Programming Algorithm...13

2.2.5 Quick-Erase Algorithm.........................13

3.0 DESIGN CONSIDERATIONS........................16

3.1 Two-Line Output Control............................16

3.2 Power Supply Decoupling..........................16

Trace on Printed Circuit Boards...........16

3.3 V

3.4 Power-Up/Down Protection........................16

3.5 28F020 Power Dissipation .........................16

4.0 ELECTRICAL SPECIFICATIONS..................18

4.1 Absolute Maximum Ratings........................18

4.2 Operating Conditions..................................18

4.3 Capacitance...............................................18

4.4 DC Characteristics—TTL/NMOS

Compatible—Commercial Products...........19

4.5 DC Characteristics—CMOS Compatible—

Commercial Products................................20

4.6 DC Characteristics—TTL/NMOS Compatible—Extended Temperature

Products....................................................22

4.7 DC Characteristics—CMOS Compatible—

Extended Temperature Products...............24

4.8 AC Characteristics—Read Only Operations—Commercial and Extended

Temperature Products...............................28

4.9 AC Characteristics—Write/Erase/Program Only Operations—Commercial and

Extended Temperature Products...............30

4.10 Erase and Programming Performance.....31

4.11 AC Characteristics—Alternate CE# Controlled Writes—Commercial and

Extended Temperature Products...............35

5.0 ORDERING INFORMATION.........................38

6.0 ADDITIONAL INFORMATION......................38

28F020 E

—

REVISION HISTORY

Number Description

-004 Removed Preliminary Classification. Clarified AC and DC test conditions. Added “dimple”

-005 Added –80V05, –90 ns speed grades. Added extended temperature devices. Corrected

-006 Added –70 ns speed. Deleted –80 V05 speed. Revised symbols, i.e., CE, OE, etc. to CE#,

-007 Updated Command Def. Table. Updated 28F020 Quick-Erase Algorithm. Updated AC

-008 Minor changes throughout document.

-009 Deleted –70 ns speed and F TSOP package. Added –120 ns speed and extended

to F TSOP package. Corrected serpentine layout.

AC Waveforms.

———

————

OE#, etc.

Characteristics. Removed serpentine layout diagram.

temperature devices. Updated Ordering Information chart. Updated AC Characteristics. Replaced references to –70 ns with –90 ns on first page. Removed F TSOP package pin configuration diagram.

E 28F020

1.0 APPLICATIONS

The 28F020 flash memory provides nonvolatility along with the capability to perform over 100,000 electrical chip-erasure/reprogram cycles. These features make the 28F020 an innovat i ve alternative to disk, EEPROM, and battery-backed st atic RAM. Where periodic updates of code and data tables

are required, the 28F020’s reprogrammability and nonvolatility make it the obvious and ideal replacement for EPROM.

Primary applications and operat ing systems stored in flash eliminate the s low disk -to-DRAM downl oad process. This result s in dramatic enhancement of performance and substantial reduction of power consumption—a consideration particularly important in portable equipment. Flash memory increases flexibility with electrical chip-erasure and in-system update capability of operating systems and application code. With updatable c ode, system manufacturers can easily accommodate lastminute changes as revisions are made.

In diskless workstations and terminals, network traffic reduces to a minimum and systems are instant-on. Reliability exceeds that of electromechanical media. Often in these environments, power interruptions force ext ended re-boot periods for all networked terminals. This mishap is no longer an issue if boot code, operating systems, communication protocol s and primary applications are flash resident in each terminal.

For embedded systems that rely on dynamic RAM/disk for main system memory or nonvolatile backup storage, the 28F020 flash memory offers a solid state alternati ve in a minimal form fact or. The 28F020 provides higher performance, lower power consumption, instant-on capability, and allows an “eXecute in place” (XIP) memory hierarchy for code and data table reading. Additi onally, t he flas h memory is more rugged and reliable in harsh environments where extreme temperatures and shock can cause disk-based systems to fail.

The need for code updates pervades al l phases of a system’s life—from prototyping to system manufacture to after sale service. The electrical chip-erasure and reprogramming ability of the 28F020 allows in-circuit alterability; this eliminat es unnecessary handling and less reliable socketed

connections, while adding greater test, manufacture, and update flexibility.

Material and labor costs associated with code changes increases at higher levels of system integration—the most costly being code updates after sale. Code “bugs,” or the desire to augment system functionality, prompt after sale code updates. Field revisions to EPROM-based code requires the removal of EPROM components or entire boards. With the 28F020, code updates are implemented locally via an edge connector, or remotely over a communications link.

For systems currently using a high-density static RAM/battery configuration for data accumulation, flash memory’s inherent nonvolatility eliminat es the need for battery backup. The concern for battery failure no longer exists, an important consideration for portable equipment and medical instruments, both requiring continuous performance. In addition, flash memory offers a cons iderable c ost adv antage over static RAM.

Flash memory’s electrical chip-erasure, byte programmability and complete nonvolatility f it well with data accumulation and recording needs. Electrical chip-eras ure gives the designer a “blank slate” in which to log or record dat a. Data can be periodically off-loaded for analysis and the flash memory erased producing a new “blank slate.”

A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 3 depicts two 28F020s tied to the 80C186 system bus. The 28F020’s architect ure m inim izes interf ace circuitry needed for compl ete in-circuit updates of memory contents.

The outstanding feature of the TSOP (Thin Small Outline Package) is the 1.2 mm thicknes s. TSOP is particularly suited for portable equipment and applications requiring large amounts of flash memory.

With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility, the 28F020 offers advantages to the alternatives: EPROMs, EEPROMs, battery backed static RAM, or disk. EPROM-compatible read specifications, straightforward interfacing, and in-circ uit alterability offers designers unlimited flexibility to meet the high standards of today’s designs.

28F020 E

DQ0 - DQ

V V

WE#

CE# OE#

SS PP

State

Control

Command

Integrated Stop

Timer

Erase Voltage

Switch

PGM Voltage

Switch

To Array Source

Chip Enable

Output Enable

Logic

STB

Input/Output

Buffers

Data Latch

A0 - A

Address Latch

Y-Decoder

X-Decoder

STB

Y-Gating

2,097,152 Bit

Cell Matrix

Figure 1. 28F020 Block Diagram

Table 1. Pin Description

Symbol Type Name and Function

A0–A

DQ0–DQ

INPUT ADDRESS INPUTS for memory addresses. Addresses are

internally latched during a write cycle.

INPUT/OUTPUT DATA INPUT/OUTPUT: Inputs data during memory write cycles;

outputs data during memory read cycles. The data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. Data is internally latched during a write cycle.

CE# INPUT CHIP ENABLE: Activates the device’s control logic, input buffers,

decoders and sense amplifiers. CE# is active low; CE# high deselects the memory device and reduces power consumption to standby levels.

OE# INPUT OUTPUT ENABLE: Gates the devices output through the data

buffers during a read cycle. OE# is active low.

WE# INPUT WRITE ENABLE: Controls writes to the control register and the

array. Write enable is active low. Addresses are latched on the falling edge and data is latched on the rising edge of the WE# pulse. Note: With V

ERASE/PROGRAM POWER SUPPLY for writing the command

≤ 6.5 V, memory contents cannot be altered.

DEVICE POWER SUPPLY (5 V ±10%) GROUND

0245_01

E 28F020

Figure 2. 28F020 Pin Configurations

28F020 E

80C186

System Bus

1-A18

DQ8 -DQ

DQ0 -DQ

Address Decoded

Chip Select

BHE

Figure 3. 28F020 in an 80C186 System

2.0 PRINCIPLES OF OPERATION

Flash memory augments EP ROM funct ionality with in-circuit electrical erasure and reprogramming. The 28F020 introduces a command register to manage this new functionality. The command register allows for 100% TTL-level control inputs, fixed power supplies during erasure and programming, and maximum EPROM compatibility.

In the absence of high v oltage on the V 28F020 is a read-only memory. Manipulat ion of the external memory control pins yields the standard EPROM read, standby, output disable, and intelligent identifier operations.

The same EPROM read, standby, and output disable operations are available when high voltage is applied to the V on V

enables erasure and programming of the

pin. In addition, high volt age

device. All functions associated with altering memory contents—intelligent identifier, erase,

erase verify, program, and program verify—are accessed via the command register.

pin, the

A0-A

-DQ

DQ0-DQ

28F020 28F020

A0-A

WE OE

Commands are written to the register using standard microprocessor write timings. Register contents serve as input to an internal state machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for programming or erase operations. With the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or output data for erase and program verification.

2.1 Integrated Stop Timer

Successive command write cycles define the durations of program and erase operations; specifically, the program or erase time durations are normally terminated by associated P rogram or Erase Verify commands . An integrated stop timer provides simplified timing control over these operations; thus eliminati ng the need for maximum program/erase timing speci fications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or eras e operation, the device enters an inactive state and remains inactive until receiving the appropriate Verify or Reset command.

0245_03

E 28F020

Table 2. 28F020 Bus Operations

Mode V

Read V

Output Disable V READ- Standby V ONLY Intelligent Identifier

(2)

(Mfr)

Intelligent Identifier

(2)

(Device)

Read V READ/ Output Disable V WRITE Standby

(5)

Write V

NOTES:

1. Refer to

2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other

3. V

4. Read operations with V

5. With V

6. Refer to Table 3 for valid data-in during a write operation.

7. X can be V

DC Characteristics

addresses low.

is the intelligent identifier high voltage. Refer to

at high voltage, the standby current equals ICC + IPP (standby).

or VIH.

. When VPP = V

= V

may access array data or the intelligent identifier codes.

PPH

(1)

PPL

PPH

memory contents can be read but not written or erased.

PPL

DC Characteristics

XXVILV

CE# OE# WE# DQ0–DQ

XXVIHX X Tri-State

(3)

XXVILV

(3)

XXVIHX X Tri-State

Data Out Tri-State

Data = 89H

Data = BDH

Data Out

(4)

Tri-State

(6)

Data In

2.2 Write Protection

The command register is only active when VPP is at high voltage. Depending upon the application, the system designer may choose to make the V power supply switchable—available only when

memory updates are desired. When V the contents of the register default to the Read command, making the 28F020 a read only memory. In this mode, the memory contents cannot be altered.

Or, the system designer may choose to “hardwire” V

, making the high voltage supply constantly

available. In this case, all command register functions are inhibited whenev er V write lockout voltage V

Protection

). The 28F020 is designed to

LKO

(see

accommodate either design practice, and to encourage optimization of the processor memory interface.

= V

PPL

is below the

Power-Up/Down

The two step program/erase write sequence to t he command register provides additional software write protection.

2.2.1 BUS OPERATIONS

2.2.1.1 Read

The 28F020 has two control functions, both of which must be logically act iv e, t o obtain dat a at t he outputs. Chip Enable (CE#) is the power control and should be used for device selection. Output Enable (OE#) is the output control and should be used to gate data from the output pins, independent of device selection. Refer t o AC read timing waveforms.

When V

is high (V

), the read operation can

PPH

be used to access array data, to output the intelligent identifier c odes, and to access data for program/erase verificati on. When V the read operation can only access the array data.

is low (V

PPL

28F020 E

2.2.1.2 Output Disable

With OE# at a logic-high level (V

), output from

the device is disabled. Out put pins are placed in a high-impedance state.

2.2.1.3 Standby

With CE# at a logic-high level, the standby

operation disables most of the 28F020’s circuitry and substantially reduces device power consumption. The outputs are placed in a highimpedance state, independent of the OE# signal . If the 28F020 is deselected during erasure, programming, or program/erase verification, the device draws active current until the operation is terminated.

2.2.1.4 Intelligent Identifier Operation

The intelligent identifier operation outputs the manufacturer code (89H) and device code (BDH). Programming equipment automatically matches the device with its proper erase and program ming algorithms.

With CE# and OE# at a logic low level, rais ing A to high voltage VID (see

DC Characteristics

activates the operation. Data read from locations 0000H and 0001H represent the manufacturer’s code and the device code, respectively.

The manufacturer and device codes can also be read via the command register, for instances where the 28F020 is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location 0000H outputs the manufacturer code (89H). A read from address 0001H outputs the device code (BDH).

2.2.1.5 Write

Device erasure and programming are accomplished via the command register, when high voltage is applied to the V

pin. The contents of

the register serve as input to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy an addressable memory location. The register is a latch used to store the command, along with address and data information needed to execute the command.

The command register is written by bringi ng WE# to a logic-low level (V

), while CE# is low.

Addresses are latched on the falling edge of WE# while data is latched on the risi ng edge of the WE# pulse. Standard microprocessor write timings are used.

Refer to

Only Operations

AC Characteristic s—Write/Erase/Program

and the erase/programming

waveforms for specific timing parameters.

2.2.2 COMMAND DEFINITIONS

)

When low voltage is applied to the V contents of the command register default to 00H, enabling read only operations.

Placing high voltage on the V

read/write operations. Device operations are selected by writing spec ific data patterns into the command register. Table 3 defines t hese 28F020 register commands.

pin, the

pin enables

E 28F020

Table 3. Command Definitions

Bus

Cycles

Command

Read Memory 1 Write X 00H Read Intelligent

Identifier Codes Set-Up

Erase/Erase Erase Verify Set-Up Program/

Program Program Verify Reset

NOTES:

1. Bus operations are defined in Table 2.

2. IA = Identifier address: 00H for manufacturer code, 01H for device code. EA = Erase Address: Address of memory location to be read during erase verify. PA = Program Address: Address of memory location to be programmed. Addresses are latched on the falling edge of the Write-Enable pulse.

3. ID = Identifier Address: Data read from location IA during device identification (Mfr = 89H, Device = BDH). EVD = Erase Verify Data: Data read from location EA during erase verify. PD = Program Data: Data to be programmed at location PA. Data is latched on the rising edge of Write-Enable. PVD = Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.

4. Following the Read Intelligent ID command, two read operations access manufacturer and device codes.

5. Figure 5 illustrates the

6. Figure 4 illustrates the

7. The second bus cycle must be followed by the desired command register write.

(5)

(6)

(7)

Req’d First Bus Cycle Second Bus Cycle

Operation

(4)

(6)

3 Write IA 90H Read IA ID

2 Write X 20H Write X 20H

2 Write EA A0H Read X EVD 2 Write X 40H Write PA PD

2 Write X C0H Read X PVD 2 Write X FFH Write X FFH

28F020 Quick-Erase Algorithm 28F020 Quick-Pulse Programming Algorithm

(1)

Address

flowchart.

(2)

(3)

Data

flowchart.

Operation

(1)

Address

(2)

Data

(3)

2.2.2.1 Read Command

While V memory contents can be accessed via the Read command. The read operation is init iat ed by wri ti ng 00H into the command register. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered.

The default contents of the register upon V power-up is 00H. This default value ensures that no spurious alteration of memory c ontents occurs during the V supply is hardwired to the 28F020, the device powers-up and remains enabled for reads until the

is high, for erasure and programming,

power transition. Where the V

command register content s are changed. Refer to the

AC Characteristics—Read-Only Operations

and waveforms for specific timing parameters.

2.2.2.2 Intelligent Identifier Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As s uc h, manufacturer and device codes must be accessible while t he device resides in t he

target system. PROM programmers typically access signature codes by raising A voltage. However, multiplexing high voltage onto

address lines is not a desired system design practice.

to a high

28F020 E

The 28F020 contains an intelligent identifier operation to supplement traditional PROMprogramming methodology. The operation is initiated by writing 90H into the command regi ster. Following the command Write, a read cycle from address 0000H retrieves the manufacturer code of 89H. A read cycle from address 0001H returns the device code of BDH. To terminate the operat ion, it is necessary to write another valid command into the register.

2.2.2.3 Set-Up Erase/Erase Commands

Set-Up Erase is a command-only operation that stages the device for el ectrical erasure of all by tes in the array. The set-up erase operation is performed by writing 20H to the command register.

To commence chip-erasure, the Erase command (20H) must again be written to the register. The erase operation begins with the rising edge of t he WE# pulse and terminates wit h the rising edge of the next WE# pulse (i.e., Erase Verify command).

This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when high voltage is appli ed to the V In the absence of this high voltage, memory contents are protected against erasure. Refer to

pin.

AC Characteristics—Write/Erase/Program Only

Operations

parameters.

2.2.2.4 Erase Verify Command

The Erase command erases all by tes of the array in parallel. After each erase operation, all bytes must be verified. The erase verify operation is initiated by writing A0H i nto the command register. The address for the byte to be verified must be supplied as it is latched on the falling edge of the WE# pulse. The register write t erminates the erase operation with the rising edge of its WE# pulse.

and waveforms for specific timing

In the case where the data read is not FFH, another erase operation is performed. (Refer to Section 2.2.2.3, Verification then resum es from the address of t he last verified byte. Once all bytes in the array have been verified, the erase step is complete. The device can be programmed. At this point , the veri fy operation is terminated by wri ting a v alid c ommand (e.g., Program Set-Up) to the command register. Figure 5, the flowchart, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F020. Refer to

Set-Up Erase/Erase Com mands

28F020 Quick-Erase Algorithm

AC Characteristics—Write/Erase/Program Only Operations

parameters.

2.2.2.5 Set-Up Program/Program

Set-Up program is a command-only operation that stages the device for byte programming. Writing 40H into the command register perf orms t he s et-up operation.

Once the program set-up operation is performed, the next WE# pulse causes a transition to an active programming operation. Addresses are internally latched on the falling edge of the WE# pulse. Data is internally latched on the risi ng edge of the WE# pulse. The rising edge of WE# also begins the programming operation. The programming operation terminates with the next rising edge of WE# used to write the Program Veri fy command. Refer to

Only Operations

parameters.

2.2.2.6 Program Verify Command

The 28F020 is programmed on a byte-by-byte basis. Byte programmi ng may occur sequent i al l y or at random. Following each programm ing operati on, the byte just programmed must be verified.

and waveforms for specific timing

Commands

AC Characteristics —Write/Erase/Program

and waveforms for specif ic timing

The 28F020 applies an internally-generated margin voltage to the addressed byt e. Reading FFH from the addressed byte indicat es that all bits in the byte are erased.

The Erase Verify command m ust be written to the command register prior to each by te verificat ion to latch its address. The process continues for each byte in the array until a byt e does not return FFH data, or the last address is accessed.

The program verify operation is initiated by wri ting C0H into the command register. The register write terminates the programming operation with the rising edge of its WE# pulse. The program verify operation stages the device for verification of the byte last programmed. No new addres s inf ormat ion is latched.

The 28F020 applies an internally-generated margin voltage to the byte. A microprocessor read cycle outputs the data. A successful comparison

+ 26 hidden pages

Intel Corporation TN28F020-150, TN28F020-120, TE28F020-150, TE28F020-120 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

CONTENTS

REVISION HISTORY

1.0 APPLICATIONS

Figure 1. 28F020 Block Diagram

Table 1. Pin Description

Figure 2. 28F020 Pin Configurations

Figure 3. 28F020 in an 80C186 System

2.0 PRINCIPLES OF OPERATION

2.1 Integrated Stop Timer

Table 2. 28F020 Bus Operations

2.2 Write Protection

2.2.1 BUS OPERATIONS

2.2.1.1 Read

2.2.1.2 Output Disable

2.2.1.3 Standby

2.2.1.4 Intelligent Identifier Operation

2.2.1.5 Write

2.2.2 COMMAND DEFINITIONS

Table 3. Command Definitions

2.2.2.1 Read Command

2.2.2.2 Intelligent Identifier Command

2.2.2.3 Set-Up Erase/Erase Commands

2.2.2.4 Erase Verify Command

2.2.2.6 Program Verify Command