Intel Corporation TE28F008BV-T90, TE28F008BV-B90, TE28F008BE-T120, TE28F008BE-B120 Datasheet
E
PRODUCT PREVIEW
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION 1995 September 1995 Order Number: 290539-002
Intel SmartVoltage Technology
5V or 12V Program/Erase
2.7V, 3.3V or 5V Read Operation
Program Time Reduced 60% at
12V V
PP
Very High Performance Read
5V: 70/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time
3V: 120/150 ns Max Access
65 ns Max. Output Enable Time
2.7V: 120 ns Max Access
65 ns Max. Output Enable Time
Low Power Consumption
Max 60 mA Read Current at 5V
Max 30 mA Read Current at 2.7–3.6V
x8/x16-Selectable Input/Output Bus
28F800 for High Performance 16- or
32-bit CPUs
x8-Only Input/Output Architecture
28F008B for Space-Constrained
8-bit Applications
Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Seven 128-KB Main Blocks
Top or Bottom Boot Locations
Absolute Hardware-Protection for Boot
Block
Software EEPROM Emulation with
Parameter Blocks
Extended Temperature Operation
–40°C to +85°C
Extended Cycling Capability
100,000 Block Erase Cycles
(Commercial Temperature)
10,000 Block Erase Cycles
(Extended Temperature)
Automated Word/Byte Write and Block
Erase
Industry-Standard Command User
Interface
Status Registers
Erase Suspend Capability
SRAM-Compatible Write Interface
Automatic Power Savings Feature
1 mA Typical I
CC
Active Current in
Static Operation
Reset/Deep Power-Down Input
0.2 µA I
CC
Typical
Provides Reset for Boot Operations
Hardware Data Protection Feature
Erase/Write Lockout during Power
Transitions
Industry-Standard Surface Mount
Packaging
40-Lead TSOP
44-Lead PSOP: JEDEC ROM
Compatible
48-Lead TSOP
Footprint Upgradeable from 2-Mbit and
4-Mbit Boot Block Flash Memories
ETOX™ IV Flash Technology
8-MBIT (512K X 16, 1024K X 8)
SmartVoltage BOOT BLOCK
FLASH MEMORY FAMILY
28F800BV-T/B, 28F800CV-T/B, 28F008BV-T/B
28F800CE-T/B, 28F008BE-T/B
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY E
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PRODUCT PREVIEW
CONTENTS
PAGE PAGE
1.0 PRODUCT FAMILY OVERVIEW .3
1.1 New Features in the
SmartVoltage Products.....................3
1.2 Main Features...................................4
1.3 Applications.....................................7
1.4 Pinouts..............................................8
1.5 Pin Descriptions.............................10
2.0 PRODUCT DESCRIPTION ...........13
2.1 Memory Organization....................13
2.1.1 Blocking...................................13
3.0 PRODUCT FAMILY PRINCIPLES
OF OPERATION............................. 12
3.1 Bus Operations...............................16
3.2 Read Operations.............................16
3.2.1 Read Array...............................16
3.2.2 Intelligent Identifiers................14
3.3 Write Operations............................19
3.3.1 Command User Interface..........19
3.3.2 Status Register..........................17
3.3.3 Program Mode..........................18
3.3.4 Erase Mode..............................27
3.4 Boot Block Locking.......................19
3.4.1 VPP = VIL for Complete
Protection..................................28
3.4.2 WP# = VIL for Boot Block
Locking.....................................28
3.4.3 RP# = VHH or WP# = VIH for
Boot Block Unlocking..............29
3.5 Power Consumption.......................33
3.5.1 Active Power............................33
3.5.2 Automatic Power Savings........ 33
3.5.3 Standby Power.........................33
3.5.4 Deep Power-Down Mode.........33
3.6 Power-Up/Down Operation............34
3.6.1 RP# Connected to System Reset34
3.6.2 VCC, VPP and RP# Transtions... 34
3.7 Power Supply Decoupling..............34
3.7.1 VPP Trace on Printed Circuit
Boards......................................35
4.0 ABSOLUTE MAXIMUM RATINGS36
5.0 COMMERCIAL OPERATING
CONDITIONS ................................. 37
5.1 Applying VCC Voltages..................37
5.2 DC Characteristics..........................38
5.3 AC Characteristics..........................32
6.0 EXTENDED OPERATING
CONDITIONS ................................. 57
6.1 Applying VCC Voltages..................57
6.2 DC Characteristics..........................58
6.3 AC Characteristics..........................67
7.0 ADDITIONAL INFORMATION ... 75
7.1 Ordering Information..................... 75
7.2 References...................................... 77
7.3 Revision History............................77
E 8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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PRODUCT PREVIEW
1.0 PRODUCT FAMILY
OVERVIEW
This datasheet contains the specifications
for the two branches of products in the
SmartVoltage 8-Mbit boot block flash
memory family: the -BE/CE suffix
products feature a low VCC operating range
of 2.7–3.6V; the -BV/CV suffix products
offer
3.0–3.6V operation. Both BE/CE and
BV/CV products also operate at 5V for
high-speed access times. Throughout this
datasheet, the 28F800 refers to all x8/x16
8-Mbit products, while 28F008B refers to
all x8 8-Mbit boot block products (but not
to the 28F008SA FlashFile™ Memory).
Also, the term “2.7V” generally means the
full voltage range 2.7–3.6V. Section 1
provides an overview of the flash memory
family including applications, pinouts and
pin descriptions. Sections 2 and 3 describe
the memory organization and operation for
these products. Finally, Sections 4, 5 and 6
contain the family’s operating
specifications.
1.1 New Features in the
SmartVoltage Products
The new 8-Mbit SmartVoltage boot block
flash memory family provides a
convenient density upgrade path from the
2-Mbit and 4-Mbit boot block products.
The 8-Mbit boot block functions similarly
to lower density boot block products in
both command sets and operation,
providing similar pinouts to ease density
upgrades.
To upgrade from lower density -BX/BLsuffix 12V program products, please note
the following differences and guidelines:
• WP# pin has replaced DU (Don’t Use)
pin #12 in the 40-lead TSOP package.
In the 44-lead PSOP, DU pin #2 is
replaced with A18 (see Figure 1 and
Section 3.4 for details). Connect the
WP# pin to control signal or to VCC or
GND (in this case, a logic-level signal
can be placed on DU pin #12 for 40lead TSOP). See Tables 2 and 9 to see
how the WP# pin works.
• 5V program/erase operation has been
added. If switching VPP for write
protection, switch to GND (not 5V) for
complete write protection. To take
advantage of 5V write-capability, allow
for connecting 5V to VPP and
disconnecting 12V from VPP line.
• Enhanced circuits optimize low V
CC
performance, allowing operation down
to VCC = 2.7V (using the BE/CE
products).
To upgrade from lower density
SmartVoltage boot block products, the
similar pinouts in the 40-lead and 48-lead
TSOP packages provide easy upgrades by
adding extra address lines (see Figures 1
and 3). In the 44-lead TSOP, the WP# pin
on the 2-Mbit and 4-Mbit BV parts
becomes A18, removing the capability to
unlock the boot block with a logic-level
signal in this package only. The boot block
can still be unlocked with 12V on RP# (see
Figure 2 and Section 3.4 for details).
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY E
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PRODUCT PREVIEW
Table 1. SmartVoltage Provides Total Voltage Flexibility
Product Bus V
CC
V
PP
Name Width 2.7–3.6V 3.3 ±± 0.3V 5V ±± 5%
5V ±± 10%
5 ±± 10%V 12 ±± 5%V
28F008BV-
T/B
x8
√√ √√ √√ √√
28F800BV-
T/B
x8 or x16
√√ √√ √√ √√
28F800CV-
T/B
x8 or x16
√√ √√ √√ √√
28F008BE-
T/B
x8
√√ √√ √√ √√
28F800CE-
T/B
x8 or x16
√√ √√ √√ √√
E 8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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PRODUCT PREVIEW
1.2 Main Features
Intel’s SmartVoltage technology is the most
flexible voltage solution in the flash
industry, providing two discrete voltage
supply pins: VCC for read operation, and V
PP
for program and erase operation. Discrete
supply pins allow system designers to use
the optimal voltage levels for their design.
All products (28F800BV/CV, 28F008BV,
28F800CE and 28F008BE) provide
program/erase capability at 5V or 12V. The
28F800BV/CV and 28F008BV allows reads
with VCC at 3.3 ± 0.3V or 5V, while the
28F800CE and 28F008BE allows reads
with VCC at 2.7–3.6V or 5V. Since many
designs read from the flash memory a large
percentage of the time, 2.7V VCC operation
can provide great power savings. If read
performance is an issue, however, 5V V
CC
provides faster read access times. For
program and erase operations, 5V V
PP
operation eliminates the need for in system
voltage converters, while 12V VPP operation
provides faster program and erase for
situations where 12V is available, such as
manufacturing or designs where 12V is insystem. For design simplicity, however, just
hook up VCC and VPP to the same 5V ± 10%
source.
The 28F800/28F008B boot block flash
memory family is a high-performance,
8-Mbit (8,388,608 bit) flash memory family
organized as either
512 Kwords of 16 bits each (28F800 only)
or
1024 Kbytes of 8 bits each (28F800 and
28F008B).
Separately erasable blocks, including a
hardware-lockable boot block (16,384
bytes), two parameter blocks (8,192 bytes
each) and main blocks (one block of 98,304
bytes and seven blocks of 131,072 bytes)
define the boot block flash family
architecture. See Figures 4 and 5 for
memory maps. Each block can be
independently erased and programmed
100,000 times at commercial temperature or
10,000 times at extended temperature.
The boot block is located at either the top
(denoted by -T suffix) or the bottom (-B
suffix) of the address map in order to
accommodate different microprocessor
protocols for boot code location. The
hardware-lockable boot block provides
complete code security for the kernel code
required for system initialization. Locking
and unlocking of the boot block is
controlled by WP# and/or RP# (see Section
3.4 for details).
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY E
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PRODUCT PREVIEW
The Command User Interface (CUI) serves
as the interface between the microprocessor
or microcontroller and the internal
operation of the boot block flash memory
products. The internal Write State Machine
(WSM) automatically executes the
algorithms and timings necessary for
program and erase operations, including
verifications, thereby unburdening the
microprocessor or microcontroller of these
tasks. The Status Register (SR) indicates the
status of the WSM and whether it
successfully completed the desired program
or erase operation.
Program and erase automation allows
program and erase operations to be
executed using an industry-standard twowrite command sequence to the CUI. Data
writes are performed in word (28F800
family) or byte (28F800 or 28F008B
families) increments. Each byte or word in
the flash memory can be programmed
independently of other memory locations,
unlike erases, which erase all locations
within a block simultaneously.
The 8-Mbit SmartVoltage boot block flash
memory family is also designed with an
Automatic Power Savings (APS) feature
which minimizes system battery current
drain, allowing for very low power designs.
To provide even greater power savings, the
boot block family includes a deep powerdown mode which minimizes power
consumption by turning most of the flash
memory’s circuitry off. This mode is
controlled by the RP# pin and its usage is
discussed in Section 3.5, along with other
power consumption issues.
Additionally, the RP# pin provides
protection against unwanted command
writes due to invalid system bus conditions
that may occur during system reset and
power-up/down sequences. For example,
when the flash memory powers-up, it
automatically defaults to the read array
mode, but during a warm system reset,
where power continues uninterrupted to the
system components, the flash memory
could remain in a non-read mode, such as
erase. Consequently, the system Reset
signal should be tied to RP# to reset the
memory to normal read mode upon
activation of the Reset signal (see Section
3.6).
The 28F800 provides both byte-wide or
word-wide input/output, which is
controlled by the BYTE# pin. Please see
Table 2 and Figure 13 for a detailed
description of BYTE# operations,
especially the usage of the DQ15/A–1 pin.
E 8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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PRODUCT PREVIEW
The 28F800 products are available in the
44-lead PSOP (Plastic Small Outline)
package (a ROM/EPROM-compatible
pinout) and the 48-lead TSOP (Thin Small
Outline, 1.2 mm thick) package as shown in
Figures 2, and 3, respectively. The 28F800
is not available in 56-lead TSOP. The
28F008B products are available in the 40lead TSOP package as shown in Figure 1.
Refer to the DC Characteristics Table,
Section 5.2 (commercial temperature)
and Section 6.2 (extended temperature),
for complete current and voltage
specifications. Refer to the AC
Characteristics Table, Section 5.3
(commercial temperature) and Section
6.3 (extended temperature), for read,
write and erase performance
specifications.
1.3 Applications
The 8-Mbit boot block flash memory family
combines high-density, low-power, highperformance, cost-effective flash memories
with blocking and hardware protection
capabilities. Their flexibility and versatility
reduce costs throughout the product life
cycle. Flash memory is ideal for just-intime production flow, reducing system
inventory and costs, and eliminating
component handling during the production
phase.
When your product is in the end-user’s
hands, and updates or feature enhancements
become necessary, flash memory reduces
the update costs by allowing userperformed code changes instead of costly
product returns or technician calls.
The 8-Mbit boot block flash memory family
provides full-function, blocked flash
memories suitable for a wide range of
applications. These applications include
ROM-able applications storage, digital
cellular phone program and data storage,
telecommunication boot/firmware, printer
firmware/font storage and various other
embedded applications where program and
data storage are required.
The 8-Mbit flash memory products are also
excellent design solutions for digital
cellular phone and telecommunication
switching applications requiring very low
power consumption, high-performance,
high-density storage capability, modular
software designs, and a small form factor
package. The 8-Mbit’s blocking scheme
allows for easy segmentation of the
embedded code with
16 Kbytes of hardware-protected boot code,
eight main blocks of program code and two
parameter blocks of 8 Kbytes each for
frequently updated data storage and
diagnostic messages (e.g., phone numbers,
authorization codes).
Intel’s boot block architecture provides a
flexible solution for the different design
needs of various applications. The
asymmetrically-blocked memory map
allows the integration of several memory
components into a single flash device. The
boot block provides a secure boot PROM;
the parameter blocks can emulate EEPROM
functionality for parameter store with
proper software techniques; and the main
blocks provide code and data storage with
access times fast enough to execute code in
place, decreasing RAM requirements.
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY E
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PRODUCT PREVIEW
1.4 Pinouts
Intel’s SmartVoltage Boot Block
architecture provides pinout upgrade paths
to the 8-Mbit density. 8-Mbit pinouts are
given on the chip illustration in the center,
with 2-Mbit and 4-Mbit pinouts going
outward from the center for reference.
The 28F008B 40-lead TSOP pinout for
space-constrained designs is shown in
Figure 1. For designs that require x16
operation but have space concerns, refer to
the 48-lead pinout in Figure 3. The 28F800
44-lead PSOP pinout follows the industrystandard ROM/EPROM pinout, as shown in
Figure 2.
28F008B
40-LEAD TSOP
Boot Block
10 mm x 20 mm
TOP VIEW
32
31
30
29
28
27
26
25
24
23
22
21
33
34
35
36
37
38
39
40
20
19
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
A
1
A
2
A
3
RP#
WE#
V
PP
A
16
A
15
A
7
A
6
A
5
A
4
A
14
A
13
A
8
A
9
A
11
A
12
WP#
NC
28F004B 28F004B
A
1
A
2
A
3
RP#
WE#
V
PP
A
16
A
15
A
7
A
6
A
5
A
4
A
14
A
13
A
8
A
9
A
11
A
12
WP#
A
18
DQ
7
CE#
OE#
GND
A
0
DQ
6
DQ
5
DQ
4
DQ
2
DQ
1
DQ
0
V
CC
DQ
3
A
17
GND
NC
A
10
NC
NC
V
CC
DQ
7
CE#
OE#
GND
A
0
DQ
6
DQ
5
DQ
4
DQ
2
DQ
1
DQ
0
V
CC
DQ
3
A
17
GND
NC
A
10
NC
NC
V
CC
28F002B28F002B
A
1
A
2
A
3
RP#
WE#
V
PP
A
16
A
15
A
7
A
6
A
5
A
4
A
14
A
13
A
8
A
9
A
11
A
12
WP#
A
18
DQ
7
CE#
OE#
GND
A
0
DQ
6
DQ
5
DQ
4
DQ
2
DQ
1
DQ
0
V
CC
DQ
3
A
17
GND
NC
A
10
NC
V
CC
A
19
0539_01
NOTE:
1. Pin 12 is DU for -BX/BL 12V V
PP
Versions.
2. The 28F008B pinout is for the 8-Mbit boot block and not for the 28F008SA FlashFile™ Memory.
Figure 1. The 40-Lead TSOP Offers the Smallest Form Factor for Space-Constrained
Applications
E 8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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PRODUCT PREVIEW
CE#
GND
OE#
A
7
A
5
A
6
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
PP
A
17
A
18
CE#
WP#
GND
OE#
A
7
A
5
A
6
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
PP
A
17
PA28F800
Boot Block
44-LEAD PSOP
0.525" x 1.110"
TOP VIEW
GND
WE#
RP#
BYTE#
A
8
A
9
A
11
A
12
A
13
A
14
A
16
DQ
7
DQ
14
DQ
6
DQ
13
DQ
12
DQ
4
V
CC
DQ
5
A
10
A
15
32
31
30
29
28
27
26
25
24
23
33
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
NC
CE#
WP#
GND
OE#
A
7
A
5
A
6
A
4
A
3
A
2
A
1
A
0
DQ
0
DQ
8
DQ
1
DQ
9
DQ
2
DQ
10
DQ
3
DQ
11
V
PP
GND
WE#
RP#
BYTE#
A
8
A
9
A
11
A
12
A
13
A
14
A
16
DQ
7
DQ
14
DQ
6
DQ
13
DQ
12
DQ
4
V
CC
DQ
5
A
10
A
15
28F200 28F200
DQ
15 -1
/A
DQ
15 -1
/A
28F400
GND
WE#
RP#
BYTE#
A
8
A
9
A
11
A
12
A
13
A
14
A
16
DQ
7
DQ
14
DQ
6
DQ
13
DQ
12
DQ
4
V
CC
DQ
5
A
10
A
15
28F400
DQ
15 -1
/A
0539_02
NOTE:
Pin 2 is DU for BX/BL 12V V
PP
Versions, but for the 8-Mbit device, pin 2 has been changed to A18 (WP# on 2/4 Mbit). Designs
planning on upgrading to the 8-Mbit density from the 2/4-Mbit density in this package should design pin 2 to control WP# functionality
at the 2/4-Mbit level and allow for pin 2 to control A18 after upgrading to the 8-Mbit density.
Figure 2. The 44-Lead PSOP Offers a Convenient Upgrade from JEDEC ROM
Standards
28F800C
Boot Block
48-LEAD TSOP
12 mm x 20 mm
TOP VIEW
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
25
26
27
28
29
30
31
32
A
1
A
2
A
3
RP#
WE#
A
15
A
7
A
6
A
5
A
4
A
14
A
13
A
8
A
9
A
11
A
12
V
PP
NC
NC
NC
A
10
WP#
NC
CE#
OE#
GND
A
0
V
CC
GND
BYTE#
A
16
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
DQ
11
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
DQ
3
A
1
A
2
A
3
RP#
WE#
A
15
A
7
A
6
A
5
A
4
A
14
A
13
A
8
A
9
A
11
A
12
V
PP
NC
NC
NC
A
17
A
10
WP#
CE#
OE#
GND
A
0
V
CC
GND
BYTE#
A
16
DQ
15
/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
DQ
11
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
DQ
3
CE#
OE#
GND
A
0
V
CC
GND
BYTE#
A
16
DQ15/A
-1
DQ
7
DQ
14
DQ
6
DQ
13
DQ
5
DQ
12
DQ
4
DQ
11
DQ
10
DQ
2
DQ
9
DQ
1
DQ
8
DQ
0
DQ
3
28F200
28 F400
28F20 0
28F4 00
NC
A
18
A
1
A
2
A
3
RP#
WE#
A
15
A
7
A
6
A
5
A
4
A
14
A
13
A
8
A
9
A
11
A
12
V
PP
NC
NC
NC
A
10
WP#
NC
A
17
0539_03
Figure 3. The 48-Lead TSOP Offers the Smallest Form Factor for x16 Operation
8-MBIT SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY E
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PRODUCT PREVIEW
1.5 Pin Descriptions
Table 2. 28F800/008B Pin Descriptions
Symbol Type Name and Function
A0–A
19
INPUT
ADDRESS INPUTS for memory addresses. Addresses are
internally latched during a write cycle. The 28F800 only has
A0–A
18
pins, while
the 28F008B has A0–A19.
A
9
INPUT
ADDRESS INPUT: When A9 is at VHH the signature mode is
accessed. During this mode, A0 decodes between the
manufacturer and device IDs. When BYTE# is at a logic low,
only the lower byte of the signatures are read. DQ15/A–1 is a
don’t care in the signature mode when BYTE# is low.
DQ0–
DQ
7
INPUT/OUT
PUT
DATA INPUTS/OUTPUTS: Inputs array data on the second
CE# and WE# cycle during a Program command. Inputs
commands to the Command User Interface when CE# and
WE# are active. Data is internally latched during the Write
cycle. Outputs array, Intelligent Identifier and Status Register
data. The data pins float to tri-state when the chip is deselected or the outputs are disabled.
DQ8–
DQ
15
INPUT/OUT
PUT
DATA INPUTS/OUTPUTS: Inputs array data on the second
CE# and WE# cycle during a Program command. Data is
internally latched during the Write cycle. Outputs array data.
The data pins float to tri-state when the chip is de-selected or
the outputs are disabled as in the byte-wide mode (BYTE# =
“0”). In the byte-wide mode DQ15/A–1 becomes the lowest
order address for data output on DQ0–DQ7. The 28F008B
does not include these DQ8–DQ
15
pins.
CE# INPUT
CHIP ENABLE: Activates the device’s control logic, input
buffers, decoders and sense amplifiers. CE# is active low.
CE# high de-selects the memory device and reduces power
consumption to standby levels. If CE# and RP# are high, but
not at a CMOS high level, the standby current will increase
due to current flow through the CE# and RP# input stages.
OE# INPUT
OUTPUT ENABLE: Enables the device’s outputs through
the data buffers during a read cycle. OE# is active low.
WE# INPUT
WRITE ENABLE: Controls writes to the Command Register
and array blocks. WE# is active low. Addresses and data are
latched on the rising edge of the WE# pulse.
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PRODUCT PREVIEW
RP# INPUT
RESET/DEEP POWER-DOWN: Uses three voltage levels
(VIL, VIH, and VHH) to control two different functions:
reset/deep power-down mode and boot block unlocking. It is
backwards-compatible with the BX/BL/BV products.
When RP# is at logic low, the device is in reset/deep
power-down mode, which puts the outputs at High-Z, resets
the Write State Machine, and draws minimum current.
When RP# is at logic high, the device is in standard
operation. When RP# transitions from logic-low to logic-
high, the device defaults to the read array mode.
When RP# is at VHH, the boot block is unlocked and can be
programmed or erased. This overrides any control from the
WP# input.
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PRODUCT PREVIEW
Table 2. 28F800/008B Pin Descriptions (Continued)
Symbol Type Name and Function
WP# INPUT
WRITE PROTECT: Provides a method for unlocking the
boot block in a system without a 12V supply.
When WP# is at logic low, the boot block is locked ,
preventing program and erase operations to the boot block. If
a program or erase operation is attempted on the boot block
when WP# is low, the corresponding status bit (bit 4 for
program, bit 5 for erase) will be set in the Status Register to
indicate the operation failed.
When WP# is at logic high, the boot block is unlocked and
can be programmed or erased.
NOTE: This feature is overridden and the boot block
unlocked when RP# is at VHH. This pin is not available on the
44-lead PSOP package. See Section 3.4 for details on write
protection.
BYTE# INPUT
BYTE# ENABLE: Not available on 28F008B. Controls
whether the device operates in the byte-wide mode (x8) or
the word-wide mode (x16). BYTE# pin must be controlled at
CMOS levels to meet the CMOS current specification in the
standby mode.
When BYTE# is at logic low, the byte-wide mode is
enabled, where data is read and programmed on DQ0–DQ
7
and DQ15/A–1 becomes the lowest order address that decodes
between the upper and lower byte. DQ8–DQ14 are tri-stated
during the byte-wide mode.
When BYTE# is at logic high, the word-wide mode is
enabled, where data is read and programmed on DQ0–DQ15.
V
CC
DEVICE POWER SUPPLY: 5.0V ± 10%, 3.3V ± 0.3V,
2.7V–3.6V
V
PP
PROGRAM/ERASE POWER SUPPLY: For erasing
memory array blocks or programming data in each block, a
voltage either of 5V ± 10% or 12V ± 5% must be applied to
this pin. When VPP < V
PPLK
all blocks are locked and
protected against Program and Erase commands.
GND
GROUND: For all internal circuitry.
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PRODUCT PREVIEW
NC
NO CONNECT: Pin may be driven or left floating.
2.0 PRODUCT DESCRIPTION
2.1 Memory Organization
2.1.1 BLOCKING
This product family features an
asymmetrically- blocked architecture
providing system memory integration. Each
erase block can be erased independently of
the others up to 100,000 times for
commercial temperature or up to 10,000
times for extended temperature. The block
sizes have been chosen to optimize their
functionality for common applications of
nonvolatile storage. The combination of
block sizes in the boot block architecture
allow the integration of several memories
into a single chip. For the address locations
of the blocks, see the memory maps in
Figures 4 and 5.
2.1.1.1 Boot Block - 1 x 16 KB
The boot block is intended to replace a
dedicated boot PROM in a microprocessor
or microcontroller-based system. The 16Kbyte (16,384 bytes) boot block is located
at either the top (denoted by -T suffix) or
the bottom (-B suffix) of the address map to
accommodate different microprocessor
protocols for boot code location. This boot
block features hardware controllable writeprotection to protect the crucial
microprocessor boot code from accidental
modification. The protection of the boot
block is controlled using a combination of
the VPP, RP#, and WP# pins, as is detailed
in Section 3.4.
2.1.1.2 Parameter Blocks - 2 x 8 KB
The boot block architecture includes
parameter blocks to facilitate storage of
frequently updated small parameters that
would normally require an EEPROM. By
using software techniques, the byte-rewrite
functionality of EEPROMs can be
emulated. These techniques are detailed in
Intel’s AP-604,
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PRODUCT PREVIEW
“Using Intel’s Boot Block Flash Memory
Parameter Blocks to Replace EEPROM.”
Each boot block component contains two
parameter blocks of
8 Kbytes (8,192 bytes) each. The parameter
blocks are not write-protectable.
2.1.1.3 Main Blocks - 1 x 96 KB + 7 x
128 KB
After the allocation of address space to the
boot and parameter blocks, the remainder is
divided into main blocks for data or code
storage. Each 8-Mbit device contains one
96-Kbyte (98,304 byte) block and seven
128-Kbyte (131,072 byte) blocks. See the
memory maps for each device for more
information.
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
7FFFFH
70000H
6FFFFH
60000H
5FFFFH
50000H
4FFFFH
40000H
3FFFFH
30000H
2FFFFH
20000H
1FFFFH
10000H
0FFFFH
04000H
03FFFH
03000H
02FFFH
02000H
01FFFH
00000H
28F800-B
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
00000H
0FFFFH
10000H
1FFFFH
20000H
2FFFFH
30000H
3FFFFH
40000H
4FFFFH
50000H
5FFFFH
60000H
6FFFFH
70000H
7BFFFH
7C000H
7CFFFH
7D000H
7DFFFH
7E000H
7FFFFH
28F800-T
0539_04
NOTE:
In x8 operation, the least significant system address should be connected to A–1. Memory maps are shown for x16 operation.
Figure 4. Word-Wide x16-Mode Memory Maps
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PRODUCT PREVIEW
28F800-T 28F800-B
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
00000H
1FFFFH
20000H
3FFFFH
40000H
5FFFFH
60000H
7FFFFH
80000H
9FFFFH
A0000H
BFFFFH
C0000H
DFFFFH
E0000H
F7FFFH
F8000H
F9FFFH
FA000H
FBFFFH
FC000H
FFFFFH
128-Kbyte MAIN BLOCK
8-Kbyte PARAMETER BLOCK
16-Kbyte BOOT BLOCK
8-Kbyte PARAMETER BLOCK
96-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
128-Kbyte MAIN BLOCK
FFFFFH
E0000H
DFFFFH
C0000H
BFFFFH
A0000H
9FFFFH
80000H
7FFFFH
60000H
5FFFFH
40000H
3FFFFH
20000H
1FFFFH
08000H
07FFFH
06000H
05FFFH
04000H
03FFFH
00000H
0539_05
NOTE:
These memory maps apply to the 28F008B or the 28F800 (in x8 mode).
Figure 5. Byte-Wide x8-Mode Memory Maps
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PRODUCT PREVIEW
3.0 PRODUCT FAMILY
PRINCIPLES OF OPERATION
Flash memory combines EPROM
functionality with in-circuit electrical write
and erase. The boot block flash family
utilizes a Command User Interface (CUI)
and automated algorithms to simplify write
and erase operations. The CUI allows for
100% TTL-level control inputs, fixed power
supplies during erasure and programming,
and maximum EPROM compatibility.
When VPP < V
PPLK
, the device will only
successfully execute the following
commands: Read Array, Read Status
Register, Clear Status Register and
intelligent identifier mode. The device
provides standard EPROM read, standby
and output disable operations. Manufacturer
identification and device identification data
can be accessed through the CUI or through
the standard EPROM A9 high voltage
access (VID) for PROM programming
equipment.
The same EPROM read, standby and output
disable functions are available when 5V or
12V is applied to the VPP pin. In addition,
5V or 12V on VPP allows write and erase of
the device. All functions associated with
altering memory contents: Program and
Erase, Intelligent Identifier Read, and Read
Status are accessed via the CUI.
The internal Write State Machine (WSM)
completely automates program and erase,
beginning operation signaled by the CUI
and reporting status through the Status
Register. The CUI handles the WE#
interface to the data and address latches, as
well as system status requests during WSM
operation.
3.1 Bus Operations
Flash memory reads, erases and writes insystem via the local CPU. All bus cycles to
or from the flash memory conform to
standard microprocessor bus cycles. These
bus operations are summarized in Tables 3
and 4.
3.2 Read Operations
3.2.1 READ ARRAY
When RP# transitions from VIL (reset) to
VIH, the device will be in the read array
mode and will respond to the read control
inputs (CE#, address inputs, and OE#)
without any commands being written to the
CUI.
When the device is in the read array mode,
five control signals must be controlled to
obtain data at the outputs.
• WE# must be logic high (V
IH
)
• CE# must be logic low (V
IL
)
• OE must be logic low (V
IL
)
• RP# must be logic high (V
IH
)
• BYTE# must be logic high or logic low.
In addition, the address of the desired
location must be applied to the address
pins. Refer to Figures 12 and 13 for the
exact sequence and timing of these signals.
If the device is not in read array mode, as
would be the case after a program or erase
operation, the Read Mode command (FFH)
must be written to the CUI before reads can
take place.
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PRODUCT PREVIEW
Table 3. Bus Operations for Word-Wide Mode (BYTE# = VIH)
Mode NotesRP# CE# OE# WE# A
9
A
0
V
PP
DQ
0–15
Read 1,2,3 V
IH
V
IL
V
IL
V
IH
X X X D
OUT
Output Disable V
IH
V
IL
V
IH
V
IH
X X X High Z
Standby V
IH
V
IH
X X X X X High Z
Deep PowerDown
9 V
IL
X X X X X X High Z
Intelligent
Identifier (Mfr.)
4 V
IH
V
IL
V
IL
V
IH
V
ID
V
IL
X 0089 H
Intelligent
Identifier
(Device)
4,5 V
IH
V
IL
V
IL
V
IH
V
ID
V
IH
X See
Table 5
Write 6,7,8 V
IH
V
IL
V
IH
V
IL
X X X D
IN
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PRODUCT PREVIEW
Table 4. Bus Operations for Byte-Wide Mode (BYTE# = VIL)
Mode NotesRP# CE# OE#WE#A
9
A0A–1VPPDQ
0–7
DQ
8–
14
Read 1,2,3 V
IH
V
IL
VILV
IH
X X X X D
OUT
High
Z
Output
Disable
VIHV
IL
VIHV
IH
X X X X HighZHigh
Z
Standby V
IH
V
IH
X X X X X X HighZHigh
Z
Deep
PowerDown
9 V
IL
X X X X X X X HighZHigh
Z
Intelligent
Identifier
(Mfr.)
4 V
IH
V
IL
VILVIHV
ID
V
IL
X X 89H High
Z
Intelligent
Identifier
(Device)
4,5 V
IH
V
IL
VILVIHV
ID
V
IH
X X See
Table
6
High
Z
Write 6,7,8 V
IH
V
IL
VIHV
IL
X X X X D
IN
High
Z
NOTES:
1. Refer to DC Characteristics.
2. X can be VIL, VIH for control pins and addresses, V
PPLK
or V
PPH
for VPP.
3. See DC Characteristics for V
PPLK
, V
PPH
1, V
PPH
2, VHH, V
ID
voltages
4. Manufacturer and device codes may also be accessed via a CUI write sequence, A1–A18 = X, A1–A19 = X.
5. See Table 5 for device IDs.
6. Refer to Table 7 for valid D
IN
during a write operation.
7. Command writes for Block Erase or Word/Byte Write are only executed when VPP = V
PPH
1 or V
PPH
2.
8. To write or erase the boot block, hold RP# at VHH or WP# at VIH. See Section 3.4.
9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
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PRODUCT PREVIEW
3.2.2 INTELLIGENT IDENTIFIERS
To read the manufacturer and device codes,
the device must be in intelligent identifier
read mode, which can be reached using two
methods: by writing the intelligent identifier
command (90H) or by taking the A9 pin to
VID. Once in intelligent identifier read
mode, A0 = 0 outputs the manufacturer’s
identification code and A0 = 1 outputs the
device code. In byte-wide mode, only the
lower byte of the above signatures is read
(DQ15/A–1 is a “don’t care” in this mode).
See Table 5 for product signatures. To
return to read array mode, write a Read
Array command (FFH).
Table 5. Intelligent Identifier Table
ProductMfr.
ID
Device ID
-T
(Top
Boot)
-B
(Bottom
Boot)
28F800 0089H889C H 889D H
28F008B89 H 9C H 9D H
3.3 Write Operations
3.3.1 COMMAND USER
INTERFACE (CUI)
The Command User Interface (CUI) is the
interface between the microprocessor and
the internal chip controller. Commands are
written to the CUI using standard
microprocessor write timings. The available
commands are Read Array, Read Intelligent
Identifier, Read Status Register, Clear
Status Register, Erase and Program
(summarized in Tables 6 and 7). The three
read modes are read array, intelligent
identifier read, and Status Register read. For
Program or Erase commands, the CUI
informs the Write State Machine (WSM)
that a write or erase has been requested.
During the execution of a Program
command, the WSM will control the
programming sequences and the CUI will
only respond to status reads. During an
erase cycle, the CUI will respond to status
reads and erase suspend. After the WSM
has completed its task, it will set the WSM
Status bit to a “1” (ready), which indicates
that the CUI can respond to its full
command set. Note that after the WSM has
returned control to the CUI, the CUI will
stay in the current command state until it
receives another command.
3.3.1.1 Command Function
Description
Device operations are selected by writing
specific commands into the CUI. Tables 6
and 7 define the available commands.
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PRODUCT PREVIEW
Table 6. Command Codes and Descriptions
Code Device Mode Description
00 Invalid/
Reserved
Unassigned commands that should not be used. Intel reserves the
right to redefine these codes for future functions.
FF Read Array/
Program or
Erase Abort
Places the device in read array mode, so that array data will be
output on the data pins. This command can also be used to cancel
erase and program sequences after their set-up commands have been
issued. To cancel after issuing an Erase Set-Up command, issue this
command, which will reset to read array mode. To cancel a program
operation after issuing a Program Set-Up command, issue two Read
Array commands in sequence to reset to read array mode. If a
program or erase operation has already been initiated to the WSM
this command can not cancel that operation in progress.
40 Program
Set-Up
Sets the CUI into a state such that the next write will load the
Address and Data registers. After this command is executed, the
outputs default to the Status Register. A two Read Array command
sequence (FFH) is required to reset to Read Array after the Program
Set-Up command.
The second write after the Program Set-Up command will latch
addresses and data, initiating the WSM to begin execution of the
program algorithm. The device outputs Status Register data when
OE# is enabled. A Read Array command is required after
programming, to read array data. See Section 3.3.3.
10 Alternate
Program Set-
Up
(See 40H/Program Set-Up)
20 Erase
Set-Up
Prepares the CUI for the Erase Confirm command. If the next
command is not an Erase Confirm command, then the CUI will set
both the Program Status and Erase Status bits of the Status Register
to a “1,” place the device into the read Status Register state, and
wait for another command. See Section 3.3.4.
D0 Erase
Resume/
Erase
Confirm
If the previous command was an Erase Set-Up command, then the
CUI will close the address and data latches, and begin erasing the
block indicated on the address pins. During erase, the device will
respond only to the Read Status Register and Erase Suspend
commands and will output Status Register data when OE# is
toggled low. Status Register data can be updated by toggling either
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PRODUCT PREVIEW
Table 6. Command Codes and Descriptions
Code Device Mode Description
OE# or CE# low.
B0 Erase
Suspend
Valid only while an erase operation is in progress and will be
ignored in any other circumstance. Issuing this command will begin
to suspend erase operation. The Status Register will indicate when
the device reaches erase suspend mode. In this mode, the CUI will
respond only to the Read Array, Read Status Register, and Erase
Resume commands and the WSM will also set the WSM Status bit
to a “1” (ready). The WSM will continue to idle in the SUSPEND
state, regardless of the state of all input control pins except RP#,
which will immediately shut down the WSM and the remainder of
the chip, if it is made active. During a suspend operation, the data
and address latches will remain closed, but the address pads are able
to drive the address into the read path. See Section 3.3.4.1.
70 Read Status
Register
Puts the device into the read Status Register mode, so that reading
the device will output the contents of the Status Register, regardless
of the address presented to the device. The device automatically
enters this mode after program or erase has completed. This is one
of the two commands that is executable while the WSM is
operating. See Section 3.3.2.
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PRODUCT PREVIEW
Table 6. Command Codes and Descriptions (Continued)
Code Device Mode Description
50 Clear Status
Register
The WSM can only set the Program Status and Erase Status bits in
the Status Register to “1,” it cannot clear them to “0.”
The Status Register operates in this fashion for two reasons. The
first is to give the host CPU the flexibility to read the status bits at
any time. Second, when programming a string of bytes, a single
Status Register query after programming the string may be more
efficient, since it will return the accumulated error status of the
entire string. See Section 3.3.2.1.
90 Intelligent
Identifier
Puts the device into the intelligent identifier read mode, so that
reading the device will output the manufacturer and device codes.
(A0 = 0 for manufacturer,
A0 = 1 for device, all other address inputs are ignored). See Section
3.2.2.
Table 7. Command Bus Definitions
First Bus Cycle Second Bus Cycle
Command Note Oper Addr Data Oper Addr Data
Read Array 8 Write X FFH
Intelligent Identifier 1 Write X 90H Read IA IID
Read Status Register 2,4 Write X 70H Read X SRD
Clear Status Register 3 Write X 50H
Word/Byte Write Write WA 40H Write WA WD
Alternate Word/Byte
Write
6,7 Write WA 10H Write WA WD
Block Erase/Confirm 6,7 Write BA 20H Write BA D0H
Erase Suspend/Resume 5 Write X B0H Write X D0H
ADDRESS DATA
BA= Block Address SRD= Status Register Data
IA= Identifier Address IID= Identifier Data
WA= Write Address WD= Write Data
X= Don’t Care
NOTES:
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1. Bus operations are defined in Tables 3 and 4.
2. IA = Identifier Address: A0 = 0 for manufacturer code, A0 = 1 for device code.
3. SRD - Data read from Status Register.
4. IID = Intelligent Identifier Data. Following the Intelligent Identifier command, two read operations access manufacturer and device
codes.
5. BA = Address within the block being erased.
6. WA = Address to be written. WD = Data to be written at location WD.
7. Either 40H or 10H commands is valid.
8. When writing commands to the device, the upper data bus [DQ8–DQ15] = X (28F800 only) which is either VIL or VIH, to minimize
current draw.
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PRODUCT PREVIEW
Table 8. Status Register Bit Definition
WSMS ESS ES DWS VPPS R R R
7 6 5 4 3 2 1 0
NOTES:
SR.7 WRITE STATE MACHINE
STATUS
1 = Ready (WSMS)
0 = Busy
Check Write State Machine bit first to
determine Word/Byte program or Block
Erase completion, before checking
Program or Erase Status bits.
SR.6 = ERASE-SUSPEND STATUS
(ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM
halts execution and sets both WSMS and
ESS bits to “1.” ESS bit remains set to “1”
until an Erase Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” WSM has
applied the max number of erase pulses to
the block and is still unable to verify
successful block erasure.
SR.4 = PROGRAM STATUS (DWS)
1 = Error in Byte/Word Program
0 = Successful Byte/Word Program
When this bit is set to “1,” WSM has
attempted but failed to program a byte or
word.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation
Abort
0 = V
PP
OK
The V
PP
Status bit does not provide
continuous indication of V
PP
level. The
WSM interrogates VPP level only after the
Byte Write or Erase command sequences
have been entered, and informs the system
if VPP has not been switched on. The V
PP
Status bit is not guaranteed to report
accurate feedback between V
PPLK
and
V
PPH
.
SR.2-SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS (R)
These bits are reserved for future use and
should be masked out when polling the
Status Register.
3.3.2 STATUS REGISTER
The device Status Register indicates when a
program or erase operation is complete, and
the success or failure of that operation. To
read the Status Register write the Read
Status (70H) command to the CUI. This
causes all subsequent read operations to
output data from the Status Register until
another command is written to the CUI. To
return to reading from the array, issue a
Read Array (FFH) command.
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