Intel Corporation TE28F016B3-T150, TE28F016B3-T120, TE28F016B3-B150, TE28F016B3-B120, TE28F008B3-T150 Datasheet
...
E
PRELIMINARY
May 1997 Order Number: 290605-001
n
Flexible SmartVoltage Technology
2.7V–3.6V Program/Erase
2.7V–3.6V Read Operation
12V VPP Fast Production
Programming
n
2.7V or 1.8V I/O Option
Reduces Overall System Power
n
Optimized Block Sizes
Eight 8-Kbyte Blocks for Data,
Top or Bottom Locations
Up to Thirty-One 64-Kbyte Blocks
for Code
n
High Performance
2.7V–3.6V: 120 ns Max Access Time
n
Block Locking
VCC-Level Control through WP#
n
Low Power Consumption
20 mA Maximum Read Current
n
Absolute Hardware-Protection
VPP = GND Option
VCC Lockout Voltage
n
Extended Temperature Operation
–40°C to +85°C
n
Supports Code plus Data Storage
Optimized for FDI, Flash Data
Integrator Software
Fast Program Suspend Capability
Fast Erase Suspend Capability
n
Extended Cycling Capability
10,000 Block Erase Cycles
n
Automated Byte Program and Block
Erase
Command User Interface
Status Registers
n
SRAM-Compatible Write Interface
n
Automatic Power Savings Feature
n
Reset/Deep Power-Down
1 µA ICCTypical
Spurious Write Lockout
n
Standard Surface Mount Packaging
48-Ball µBGA* Package
40-Lead TSOP Package
n
Footprint Upgradeable
Upgradeable from 2-, 4- and 8-Mbit
Boot Block
n
ETOX™ V (0.4 µ) Flash Technology
n
x8-Only Input/Output Architecture
For Space-Constrained 8-bit
Applications
The new Smart 3 Advanced Boot Bl ock , m anufac tured on I ntel’ s lat est 0.4µ t echnol ogy, represent s a featurerich solution at overall lower system cost. Smart 3 flash memory devices incorporate low voltage capability
(2.7V read, program and erase) with high-speed, low-power operation. Several new features have been
added, including the ability to drive the I /O at 1.8V, which significantly reduces system active power and
interfaces to 1.8V control lers. A new bloc king schem e enables code and data s torage within a si ngle device.
Add to this the Intel-dev eloped Flash Data Integrator (FDI) software and you hav e the most cost-effect ive,
monolithic code plus data storage solution on t he market today. Smart 3 Advanced Boot B lock Byte-Wide
products will be available in 40-lead TSOP and 48-ball µBGA* packages. Additional information on this
product family can be obtained by accessing Intel’s WWW page: http://www.intel.com/design/flcomp
SMART 3 ADVANCED BOOT BLOCK
BYTE-WIDE
8-MBIT (1024K x 8), 16-MBIT (2056K x 8)
FLASH MEMORY FAMILY
28F008B3, 28F016B3
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or
otherwise, to any intellectual property rights is granted by this document. Except as provi ded in Intel ’s Terms and Condi tions of
Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to
sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life
saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The 28F008B3 and 28F016B3 may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
*Third-party brands and names are the property of their respective owners.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be
obtained from:
Intel Corporation
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
or visit Intel’s website at http:\\www.intel.com
COPYRIGHT © INTEL CORPORATION 1996, 1997 CG-041493
*Third-party brands and names are the property of their respective owners.
E SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
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PRELIMINARY
CONTENTS
PAGE PAGE
1.0 INTRODUCTION .............................................5
1.1 Smart 3 Advanced Boot Block Flash
Memory Enhancements ..............................5
1.2 Product Overview.........................................6
2.0 PRODUCT DESCRIPTION..............................6
2.1 Package Pinouts..........................................7
2.2 Block Organization.....................................11
2.2.1 Parameter Blocks................................11
2.2.2 Main Blocks.........................................11
3.0 PRINCIPLES OF OPERATION .....................14
3.1 Bus Operation............................................14
3.1.1 Read....................................................15
3.1.2 Output Disable.....................................15
3.1.3 Standby...............................................15
3.1.4 Deep Power-Down/Reset....................15
3.1.5 Write....................................................15
3.2 Modes of Operation....................................15
3.2.1 Read Array..........................................16
3.2.2 Read Intelligent Identifier.....................17
3.2.3 Read Status Register ..........................17
3.2.4 Program Mode.....................................18
3.2.5 Erase Mode.........................................19
3.3 Block Locking.............................................26
3.3.1 V
PP
= VIL for Complete Protection .......26
3.3.2 WP# = V
IL
for Block Locking................26
3.3.3 WP# = V
IH
for Block Unlocking............26
3.4 V
PP
Program and Erase Voltages ..............26
3.5 Power Consumption...................................26
3.5.1 Active Power .......................................26
3.5.2 Automatic Power Savings (APS) .........27
3.5.3 Standby Power....................................27
3.5.4 Deep Power-Down Mode.....................27
3.6 Power-Up/Down Operation.........................27
3.6.1 RP# Connected to System Reset ........27
3.6.2 V
CC
, VPP and RP# Transitions.............27
3.7 Power Supply Decoupling ..........................28
3.7.1 V
PP
Trace on Printed Circuit Boards....28
4.0 ABSOLUTE MAXIMUM RATINGS................29
5.0 OPERATING CONDITIONS
(V
CCQ
= 2.7V–3.6V).......................................29
5.1 DC Characteristics: V
CCQ
= 2.7V–3.6V.......30
6.0 OPERATING CONDITIONS
(V
CCQ
= 1.8V–2.2V).......................................34
6.1 DC Characteristics: V
CCQ
= 1.8V–2.2V.......34
7.0 AC CHARACTERISTICS...............................39
7.1 Reset Operations .......................................43
APPENDIX A: Ordering Information .................45
APPENDIX B: Write State Machine Current/
Next States ..................................................46
APPENDIX C: Access Time vs.
Capacitive Load...........................................47
APPENDIX D: Architecture Block Diagram ......48
APPENDIX E: Additional Information ...............49
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
4
PRELIMINARY
REVISION HISTORY
Number Description
-001 Original version
E SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
5
PRELIMINARY
1.0 INTRODUCTION
This preliminary datasheet contains the
specifications for the Advanced Boot Block flash
memory family, which is optimized for low power,
portable systems. This family of products features
1.8V–2.2V or 2.V–3.6V I/Os and a low V
CC/VPP
operating range of 2.7V–3.6V for read and
program/erase operations. In addit ion this fami ly i s
capable of fast programming at 12V. Throughout
this document, the term “2.7V” refers to the full
voltage range 2.7V–3.6V (except where noted
otherwise) and “V
PP
= 12V” refers to 12V ±5%.
Section 1 and 2 provides an overv iew of the flash
memory family incl uding applications, pinouts and
pin descriptions. Section 3 descri bes the memory
organization and operation for these products.
Finally, Sections 4, 5, 6 and 7 contain the
operating specifications.
1.1 Smart 3 Advanced Boot Block
Flash Memory Enhancements
The new 8-Mbit and 16-Mbit Smart 3 Advanced
Boot Block flash memory provides a convenient
upgrade from and/or compatibility to previous 4Mbit and 8-Mbit Boot Block product s. The Smart 3
product functions are similar to lower density
products in both command sets and operation,
providing similar pinouts to ease density upgrades.
The Smart 3 Advanced Boot Block flash memory
features
• Enhanced blocking for easy segmentation of
code and data or additional design flexibility
• Program Suspend command which permits
program suspend to read
• WP# pin to lock and unlock t he upper two (or
lower two, depending on location) 8-Kbyte
blocks
• V
CCQ
input for 1.8V–2.2V on all I/Os. See
Figures 1–3 for pinout diagrams and V
CCQ
location
• Maximum program time specification for
improved data storage.
Table 1. Smart 3 Advanced Boot Block Feature Summary
Feature 28F016B3/28F008B3/28F004B3 Reference
VCC Read Voltage 2.7V– 3.6V Table 9, Table 12
V
CCQ
I/O Voltage 1.8V–2.2V or 2.7V– 3.6V Table 9, Table 12
VPP Program/Erase Voltage 2.7V– 3.6V or 11.4V– 12.6V Table 9, Table 12
Bus Width 8 bits Table 2
Speed 120 ns Table 15
Memory Arrangement 1 Mbit x 8 (8 Mbit), 2 Mbit x 8 (16 Mbit)
Blocking (top or bottom) Eight 8-Kbyte parameter blocks (8/16 Mbit) &
Fifteen 64-Kbyte blocks (8 Mbit)
Thirty-one 64-Kbyte main blocks (16 Mbit)
Section 2.2
Figures 4 and 5
Locking WP# locks/unlocks parameter blocks
All other blocks protected using V
PP
switch
Section 3.3
Table 8
Operating Temperature Extended: –40°C to +85°C Table 9, Table 12
Program/Erase Cycling 10,000 cycles Table 9, Table 12
Packages 40-Lead TSOP, 48-Ball µBGA* CSP Figures 1, 2, and 3
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
6
PRELIMINARY
1.2 Product Overview
Intel provides the most flexible voltage solution in
the flash industry, prov iding three discrete voltage
supply pins: V
CC
for read operation, V
CCQ
for output
swing, and V
PP
for program and erase operation.
Discrete supply pins allow system designers to use
the optimal voltage level s for thei r design. A ll Smart
3 Advanced Boot Block flash memory products
provide program/erase capability at 2.7V or 12V
and read with V
CC
at 2.7V. Since many designs
read from the flash memory a large perc entage of
the time, 2.7V V
CC
operation can provide
substantial power savings. The 12V V
PP
option
maximizes program and erase performanc e during
production programming.
The Smart 3 Advanced Boot Block flash memory
products are high-performance devices with low
power operation. The available densities for the
byte-wide devices (x8) are
a. 8-Mbit (8,388,608-bit) flash memory
organized as 1 Mbyte of 8 bits each
b. 16-Mbit (16,777,216-bit) flash memory
organized as 2 Mbytes of 8 bits each.
For word-wide devices (x16) see the
Smart 3
Advanced Boot Block Word-Wide Flash Memory
Family
datasheet.
The parameter blocks are located at either the top
(denoted by -T suffix) or the bot tom (-B suffix) of the
address map in order to accommodate different
microprocessor protocols for kernel code location.
The upper two (or lower two) parameter blocks can
be locked to provide complete code security for
system initialization code. Locking and unlocking is
controlled by WP# (see Section 3.3 for details).
The Command User Interface (CUI) s erves as the
interface between the microprocessor or
microcontroller and the internal operation of the
flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and
timings necessary for program and erase
operations, including verification, thereby unburdening the microprocessor or microcontroller.
The status register indicates t he status of the WSM
by signifying block erase or byte program
completion and status.
Program and erase automation allows program and
erase operations to be executed using an indust rystandard two-write command sequence t o the CUI.
Data writes are performed in byte i ncrements . E ach
byte in the flash memory can be programmed
independently of other memory locations; every
erase operation erases all locations within a bl ock
simultaneously. Program suspend allows system
software to suspend the program comm and in order
to read from any other block. E rase s uspend allows
system software to suspend the block erase
command in order to read from or program data to
any other block.
The Smart 3 Advanced Boot Bl ock flas h memory is
also designed with an Automatic Power Savings
(APS) feature which minimizes system current
drain, allowing for very low power designs. This
mode is entered immediately following the
completion of a read cycle.
When the CE# and RP# pins are at V
CC
, the I
CC
CMOS standby mode is enabled. A deep powerdown mode is enabled when the RP# pin is at
GND, minimizing power consum ption and providing
write protection. I
CC
current in deep power-down is
1 µA typical (2.7V V
CC
). A minimum reset time of
t
PHQV
is required from RP# switching high until
outputs are valid to read attempts. With RP# at
GND, the WSM is reset and Status Register is
cleared. Section 3.5 cont ains additional inf ormation
on using the deep power-down feature, along wit h
other power consumption issues.
The RP# pin provides additional protection agains t
unwanted command writes that may occur during
system reset and power-up/down sequences due to
invalid system bus conditions (see Section 3.6).
Refer to the DC Characteristic s Table, Sec tions 5.1
and 6.1, for complete current and voltage
specifications. Refer to the AC Characteristics
Table, Section 7.0, for read, program and erase
performance specifications.
2.0 PRODUCT DESCRIPTION
This section explains device pin description and
package pinouts.
E SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
7
PRELIMINARY
2.1 Package Pinouts
The Smart 3 Advanced Boot Bl ock flas h memory is
available in 40-lead TSOP (see Figure 1) and 48ball µBGA packages (see Figures 2 and 3). In
Figure 1, pin changes from one density to the next
are circled. Both packages , 40-lead TSOP and 48ball µBGA
package, are 8-bits wide and fully
upgradeable across product densities (f rom 8 Mb to
16 Mb).
Advanced Boot Bloc k
40-Lead TSOP
10 mm x 20 mm
TOP VIEW
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
20
19
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
21
22
23
24
28F00828F016
A
16
A
15
A
14
A
13
A
12
A
11
A
9
A
8
WE#
RP#
WP#
A
7
A
6
A
5
A
4
A
3
A
2
A
1
V
PP
A
18
A
16
A
15
A
14
A
13
A
12
A
11
A
9
A
8
WE#
RP#
WP#
A
7
A
6
A
5
A
4
A
3
A
2
A
1
V
PP
A
18
28F008 28F016
A
17
GND
A
10
DQ
7
DQ
6
DQ
5
DQ
4
V
CCQ
V
CC
NC
DQ
3
DQ
2
DQ
1
OE#
GND
CE#
A
0
NC
A
17
GND
A
10
DQ
7
DQ
6
DQ
5
DQ
4
V
CCQ
V
CC
NC
DQ
3
DQ
2
DQ
1
OE#
GND
CE#
A
0
A
19
A
19
A
20
DQ0DQ
0
0605-01
Figure 1. 40-Lead TSOP Package
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
8
PRELIMINARY
A
14
A
12
A
8
V
PP
WP# NC A
7
A
4
A
15
A
10
WE# RP# A
19
A
18
A
5
A
2
A
16
A
13
A
9
A
6
A
3
A
1
A
17
NC D
5
NC D
2
NC CE# A
0
V
CCQ
A
11
D
6
NC D
3
NC D
0
GND
GND D
7
NC D
4
V
CC
NC D
1
OE#
A
B
C
D
E
F
1234 567 8
0605-03
NOTE:
Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.
Routing is not recommended in this area.
Figure 2. 8-Mbit 48-Ball µBGA* Chip Size Package
E SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
9
PRELIMINARY
A
14
A
12
A
8
V
PP
WP# A
20
A
7
A
4
A
15
A
10
WE# RP# A
19
A
18
A
5
A
2
A
16
A
13
A
9
A
6
A
3
A
1
A
17
NC D
5
NC D
2
NC CE# A
0
V
CCQ
A
11
D
6
NC D
3
NC D
0
GND
GND D
7
NC D
4
V
CC
NC D
1
OE#
A
B
C
D
E
F
1234 567 8
0605-02
NOTE:
Dotted connections indicate placeholders where there is no solder ball. These connections are reserved for future upgrades.
Routing is not recommended in this area.
Figure 3. 16-Mbit 48-Ball µBGA* Chip Size Package
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
10
PRELIMINARY
The pin descriptions table details the usage of each device pin.
Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions
Symbol Type Name and Function
A0–A
20
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a program or erase cycle.
28F008B3: A[0-19], 28F016B3: A[0-20]
DQ0–DQ7INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and
WE# cycle during a Program command. Inputs commands to the
Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, Intelligent Identifier and Status Register
data. The data pins float to tri-state when the chip is de-selected or the
outputs are disabled.
CE# INPUT CHIP ENABLE: Activates the internal control logic, input buffers,
decoders and sense amplifiers. CE# is active low. CE# high de-selects
the memory device and reduces power consumption to standby levels. If
CE# and RP# are high, but not at a CMOS high level, the standby
current will increase due to current flow through the CE# and RP# inputs.
OE# INPUT OUTPUT ENABLE: Enables the device’s outputs through the data
buffers during an array or status register read. OE# is active low.
WE# INPUT WRITE ENABLE: Controls writes to the Command Register and memory
array. WE# is active low. Addresses and data are latched on the rising
edge of the second WE# pulse.
RP# INPUT RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to
control reset/deep power-down mode.
When RP# is at logic low, the device is in reset/deep power-down
mode, which drives the outputs to High-Z, resets the Write State
Machine, and draws minimum current.
When RP# is at logic high, the device is in standard operation.
When RP# transitions from logic-low to logic-high, the device defaults to
the read array mode.
WP# INPUT WRITE PROTECT: Provides a method for locking and unlocking the two
lockable parameter blocks.
When WP# is at logic low, the lockable blocks are locked,
preventing program and erase operations to those blocks. If a program
or erase operation is attempted on a locked block, SR.1 and either SR.4
[program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and
can be programmed or erased.
See Section 3.3 for details on write protection.
E SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
11
PRELIMINARY
Table 2. 16-Mbit Smart 3 Advanced Boot Block Pin Descriptions (Continued)
Symbol Type Name and Function
VCCQ INPUT OUTPUT VCC: Enables all outputs to be driven to 2.0V ±10% while the
V
CC
is at 2.7V. When this mode is used, the VCC should be regulated to
2.7V–2.85V to achieve lowest power operation (see Section 6.1: DC
Characteristics: V
CCQ
= 1.8V–2.2V).
This input may be tied directly to V
CC
(2.7V–3.6V).
See the DC Characteristics for further details.
V
CC
DEVICE POWER SUPPLY: 2.7V–3.6V
V
PP
PROGRAM/ERASE POWER SUPPLY: For erasing memory array
blocks or programming data in each block, a voltage of either 2.7V–3.6V
or 12V ± 5% must be applied to this pin. When V
PP
< V
PPL
K
all blocks
are locked and protected against Program and Erase commands.
Applying 11.4V–12.6V to V
PP
can only be done for a maximum of 1000
cycles on the main blocks and 2500 cycles on the parameter blocks.
V
PP
may be connected to 12V for a total of 80 hours maximum (see
Section 3.4 for details).
GND GROUND: For all internal circuitry. All ground inputs must be
connected.
NC NO CONNECT: Pin may be driven or left floating.
2.2 Block Organization
The Smart 3 Advanced Boot Block is an
asymmetrically-blocked architecture that enables
system integration of code and data within a single
flash device. Each block can be erased
independently of the others up to 10, 000 times . For
the address locations of each block, see the
memory maps in Figure 4 (top boot blocking) and
Figure 5 (bottom boot blocking).
2.2.1 PARAMETER BLOCKS
The Smart 3 Advanced Boot Block flash memory
architecture includes parameter bl ocks to facilitate
storage of frequently updated small parameters
(e.g., data that would normally be stored in an
EEPROM. By using software techniques, the by terewrite functionality of EEPROMs can be emulated.
Each 8-/16-Mbit device contains eight parameter
blocks of 8 Kbytes (8,192-bytes) each.
2.2.2 MAIN BLOCKS
After the parameter blocks, the remainder of the
array is divided into equal size main blocks for data
or code storage. Each 16-Mbit device contains
thirty-one 64-Kbyte (65,536-byte) blocks. Each
8-Mbit device contains fifteen 64-Kbyte blocks.
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
12
PRELIMINARY
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
FFFFF
FE000
FDFFF
FC000
FBFFF
F9FFF
FA000
F7FFF
70000
6FFFF
F8000
F6000
F5FFF
F4000
F2000
F1FFF
F0000
EFFFF
64-Kbyte Block
64-Kbyte Block
3FFFF
30000
2FFFF
20000
3
0
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
20
21
22
18
19
17
16
15
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
10
8
9
7
6
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
14
13
12
11
8-Mbit Advanced Boot
Block
64-Kbyte Block
64-Kbyte Block
50000
4FFFF
40000
64-Kbyte Block
64-Kbyte Block
1FFFF
10000
0FFFF
00000
0
1
2
4
5
F3FFF
5FFFF
60000
1E0000
1BFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
080000
07FFFF
1FFFFF
1FE000
1FDFFF
1FC000
1FBFFF
1F9FFF
1FA000
1F7FFF
070000
06FFFF
1F8000
1F6000
1F5FFF
1F4000
1F2000
1F1FFF
1F0000
1EFFFF
64-Kbyte Block
64-Kbyte Block
03FFFF
030000
02FFFF
020000
3
0
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
8-Kbyte Block
36
37
38
34
35
33
32
31
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
10
8
9
7
6
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
30
29
12
11
16-Mbit Advanced Boot
Block
64-Kbyte Block
64-Kbyte Block
050000
04FFFF
040000
64-Kbyte Block
64-Kbyte Block
01FFFF
010000
00FFFF
000000
0
1
2
4
5
1F3FFF
05FFFF
060000
15FFFF
150000
14FFFF
140000
13FFFF
130000
12FFFF
120000
11FFFF
110000
10FFFF
100000
0FFFFF
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
19
17
18
16
15
64-Kbyte Block
64-Kbyte Block
21
20
64-Kbyte Block
64-Kbyte Block
0E0000
0DFFFF
13
14
0EFFFF
0F0000
1B0000
1A0000
19FFFF
1AFFFF
64-Kbyte Block
64-Kbyte Block
28
27
190000
180000
17FFFF
18FFFF
64-Kbyte Block
64-Kbyte Block
26
25
170000
64-Kbyte Block
160000
16FFFF
64-Kbyte Block
64-Kbyte Block
22
23
24
1DFFFF
1D0000
1CFFFF
1C0000
0605-05
Figure 4. 8-/16-Mbit Advanced Boot Block Byte-Wide Top Boot Memory Maps
E SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
13
PRELIMINARY
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
FFFFF
F0000
EFFFF
E0000
DFFFF
CFFFF
D0000
BFFFF
0E000
0DFFF
C0000
B0000
AFFFF
A0000
90000
8FFFF
80000
7FFFF
8-Kbyte Block
8-Kbyte Block
07FFF
06000
05FFF
04000
3
0
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
20
21
22
18
19
17
16
15
64-Kbyte Block
8-Kbyte Block
64-Kbyte Block
8-Kbyte Block
64-Kbyte Block
10
8
9
7
6
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
14
13
12
11
8-Mbit Advanced Boot
Block
8-Kbyte Block
8-Kbyte Block
0A000
09FFF
08000
8-Kbyte Block
8-Kbyte Block
03FFF
02000
01FFF
00000
0
1
2
4
5
9FFFF
0BFFF
0C000
170000
14FFFF
060000
05FFFF
050000
04FFFF
040000
03FFFF
030000
02FFFF
020000
01FFFF
010000
00FFFF
1FFFFF
1F0000
1EFFFF
1E0000
1DFFFF
1CFFFF
1D0000
1BFFFF
00E000
00DFFF
1C0000
1B0000
1AFFFF
1A0000
190000
18FFFF
180000
17FFFF
8-Kbyte Block
8-Kbyte Block
007FFF
006000
005FFF
004000
3
0
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
36
37
38
34
35
33
32
31
64-Kbyte Block
8-Kbyte Block
64-Kbyte Block
8-Kbyte Block
64-Kbyte Block
10
8
9
7
6
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
30
29
12
11
16-Mbit Advanced Boot
Block
8-Kbyte Block
8-Kbyte Block
00A000
009FFF
008000
8-Kbyte Block
8-Kbyte Block
003FFF
002000
001FFF
000000
0
1
2
4
5
19FFFF
00BFFF
00C000
0EFFFF
0E0000
0DFFFF
0D0000
0CFFFF
0C0000
0BFFFF
0B0000
0AFFFF
0A0000
09FFFF
090000
08FFFF
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
19
17
18
16
15
64-Kbyte Block
64-Kbyte Block
21
20
64-Kbyte Block
64-Kbyte Block
070000
06FFFF
13
14
07FFFF
080000
140000
130000
12FFFF
13FFFF
64-Kbyte Block
64-Kbyte Block
28
27
120000
110000
10FFFF
11FFFF
64-Kbyte Block
64-Kbyte Block
26
25
100000
64-Kbyte Block
0F0000
0FFFFF
64-Kbyte Block
64-Kbyte Block
22
23
24
16FFFF
160000
15FFFF
150000
0605-06
Figure 5. 8-/16-Mbit Advanced Boot Block Byte-Wide Bottom Boot Memory Maps
SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E
14
PRELIMINARY
3.0 PRINCIPLES OF OPERATION
Flash memory combines EEPROM functionality
with in-circuit electrical program and erase
capability. The Smart 3 Advanc ed Boot Block flash
memory family utilizes a Command User Interface
(CUI) and automated algorithms to si mpli fy program
and erase operations. The CUI allows for 100%
CMOS-level control inputs, fixed power supplies
during erasure and programming, and maximum
EEPROM compatibility.
When V
PP
< V
PPLK
, the device will only execute the
following commands successfully: Read Array,
Read Status Register, Clear Status Register and
Read Intelligent Identifier. The device provides
standard EEPROM read, standby and output
disable operations. Manufac turer identification and
device identification data can be ac cessed through
the CUI. In addition, 2.7V or 12V on V
PP
allows
program and erase of the device. All functions
associated with altering memory contents, namely
program and erase, are accessible via the CUI.
The internal Write State Machi ne (WSM) completely
automates program and erase operati ons while the
CUI signals the start of an operation and the stat us
register reports status . The CUI handles the WE#
interface to the data and address latches, as well
as system status requests during WSM operation.
3.1 Bus Operation
Smart 3 Advanced Boot Block flash memory
devices read, program and erase in-system via the
local CPU or microcontroller. All bus cycles to or
from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate
the data flow in and out of the flash component:
CE#, OE#, WE# and RP#. These bus operations
are summarized in Table 3.
Table 3. Bus Operations for Byte-Wide Mode
Mode Notes RP# CE# OE# WE# WP# A0V
PP
DQ
0–7
Read 1,2,3 V
IH
V
IL
V
IL
V
IH
XXXD
OUT
Output Disable 2 V
IH
V
IL
V
IH
V
IH
X X X High Z
Standby 2 V
IH
V
IH
X X X X X High Z
Deep Power-Down 2,9 V
IL
X X X X X X High Z
Intelligent Identifier (Mfr.) 2,4 V
IH
V
IL
V
IL
V
IH
XVILX 89 H
Intelligent Identifier (Dvc.) 2,4,5 V
IH
V
IL
V
IL
V
IH
XVIHX See Table 5
Write 2,6,7,8V
IH
V
IL
V
IH
V
IL
XXV
PPH
D
IN
NOTES:
1. Refer to DC Characteristics.
2. X must be V
IL
, VIH for control pins and addresses, V
PPLK
, V
PPH1
or V
PPH2
for VPP.
3. See DC Characteristics for V
PPLK
, V
PPH1
, V
PPH2
voltages.
4. Manufacturer and device codes may also be accessed via a CUI write sequence, A
1–A20
= X
5. See Table 5 for device IDs.
6. Refer to Table 6 for valid D
IN
during a write operation.
7. Command writes for block erase or byte program are only executed when V
PP
= V
PPH1
or V
PPH2
.
8. To program or erase the lockable blocks, hold WP# at V
IH
. See Section 3.3.
9. RP# must be at GND ± 0.2V to meet the maximum deep power-down current specified.
E SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE
15
PRELIMINARY
3.1.1 READ
The flash memory has three read modes av ailable:
read array, read identifier, and read s tatus. These
modes are accessible independent of the V
PP
voltage. The appropriate read mode c om m and must
be issued to the CUI to enter the corresponding
mode. Upon initial device power-up or after exit
from deep power-down mode, the device
automatically defaults to read array mode.
CE# and OE# must be driven active to obtain dat a
at the outputs. CE# is the device s election control;
when active it enables the flash memory device.
OE# is the data output (DQ
0
–DQ7) control and it
drives the selected mem ory data onto the I/O bus.
For all read modes, WE# and RP# must be at V
IH
.
Figure 14 illustrates a read cycle.
3.1.2 OUTPUT DISABLE
With OE# at a logic-high level (V
IH
), the device
outputs are disabled. Output pins DQ
0
–DQ7 are
placed in a high-impedance state.
3.1.3 STANDBY
Deselecting the device by bringi ng CE# to a logichigh level (V
IH
) places the device in standby mode,
which substantially reduces device power
consumption. In standby, outputs DQ
0
–DQ7 are
placed in a high-impedance state independent of
OE#. If deselected during program or erase
operation, the device conti nues to consume active
power until the program or erase operation is
complete.
3.1.4 DEEP POWER-DOWN/RESET
RP# at V
IL
initiates the deep power-down mode,
sometimes referred to as reset mode.
From read mode, RP# going low for time t
PLPH
accomplishes the following:
1. deselects the memory
2. places output drivers in a high-impedance
state
After return from power-down, a time t
PHQV
is
required until the initial mem ory access out puts are
valid. A delay (t
PHWL
or t
PHEL
) is required after
return from power-down before a write sequence
can be initiated. After this wak e-up interval, normal
operation is restored. The CUI resets t o read array
mode, and the status register is set to 80H (ready).
If RP# is taken low for time t
PLPH
during a program
or erase operation, the operation will be aborted
and the memory contents at the aborted location
are no longer valid. After returning f rom an aborted
operation, time t
PHQV
or t
PHWL/tPHEL
must be met
before a read or write operation is initiated
respectively.
3.1.5 WRITE
A write is any command t hat alters the content s of
the memory array. There are two write c ommands:
Program (40H) and Erase (20H). Writing either of
these commands to the internal Command User
Interface (CUI) initiates a sequence of internallytimed functions that culminate in the c ompletion of
the requested task (unless that operat ion is aborted
by either RP# being driven to V
IL
for of t
PLRH
or an
appropriate suspend command).
The Command User Interface does not occupy an
addressable memory locati on. Instead, commands
are written into the CUI using standard
microprocessor write timings when WE# and CE#
are low, OE# = V
IH
, and the proper address and
data (command) are presented. The command is
latched on the rising edge of the f irst WE# or CE#
pulse, whichever occurs first. Figure 15 illustrates a
write operation.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines the
available commands. Appendi x B provides detai led
information on moving between the different modes
of operation.
3.2 Modes of Operation
The flash memory has three read modes and two
write modes. The read modes are read array, read
identifier, and read status. The write modes are
program and block erase. Three additional mode
(erase suspend to program, erase sus pend to read
and program suspend to read) are available only
during suspended operations. These modes are
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