Intel Corporation TA80960CF-30, TA80960CF-25, TA80960CF-16 Datasheet
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
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changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
January 1995COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 271328-001
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
32-BIT HIGH-PERFORMANCE SUPERSCALAR
PROCESSOR
#
Socket and Object Code Compatible with 80960CA
#
Two Instructions/Clock Sustained Execution
#
Four 59 Mbytes/s DMA Channels with Data Chaining
#
Demultiplexed 32-bit Burst Bus with Pipelining
Y
32-bit Parallel Architecture
Ð Two Instructions/clock Execution
Ð Load/Store Architecture
Ð Sixteen 32-bit Global Registers
Ð Sixteen 32-bit Local Registers
Ð Manipulate 64-bit Bit Fields
Ð 11 Addressing Modes
Ð Full Parallel Fault Model
Ð Supervisor Protection Model
Y
Fast Procedure Call/Return Model
Ð Full Procedure Call in 4 clocks
Y
On-Chip Register Cache
Ð Caches Registers on Call/Ret
Ð Minimum of 6 Frames provided
Ð Up to 15 Programmable Frames
Y
On-Chip Instruction Cache
Ð 4 Kbyte Two-Way Set Associative
Ð 128-bit Path to Instruction Sequencer
Ð Cache-Lock Modes
Ð Cache-Off Mode
Y
On-Chip Data Cache
Ð 1 Kbyte Direct-Mapped,
Write Through
Ð 128 bits per Clock Access on
Cache Hit
Y
Product Grades Available
Ð SE3:
b
40§Ctoa110§C
Y
High Bandwidth On-Chip Data RAM
Ð 1 Kbytes On-Chip RAM for Data
Ð Sustain 128 bits per clock access
Y
Four On-Chip DMA Channels
Ð 59 Mbytes/s Fly-by Transfers
Ð 32 Mbytes/s Two-Cycle Transfers
Ð Data Chaining
Ð Data Packing/Unpacking
Ð Programmable Priority Method
Y
32-Bit Demultiplexed Burst Bus
Ð 128-bit Internal Data Paths to
and
from Registers
Ð Burst Bus for DRAM Interfacing
Ð Address Pipelining Option
Ð Fully Programmable Wait States
Ð Supports 8, 16 or 32-bit Bus Widths
Ð Supports Unaligned Accesses
Ð Supervisor Protection Pin
Y
Selectable Big or Little Endian Byte
Ordering
Y
High-Speed Interrupt Controller
Ð Up to 248 External Interrupts
Ð 32 Fully Programmable Priorities
Ð Multi-mode 8-bit Interrupt Port
Ð Four Internal DMA Interrupts
Ð Separate, Non-maskable Interrupt Pin
Ð Context Switch in 750 ns Typical
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328– 1
Figure 1. 80960CF Die Photo
2
Special Environment 80960CF-30, -25, -16
32-Bit High Performance Superscalar Processor
CONTENTS PAGE
1.0 PURPOSE ААААААААААААААААААААААААААААА 5
2.0 i960 CF PROCESSOR
OVERVIEW
ААААААААААААААААААААААААААААА 5
2.1 The C-Series Core ААААААААААААААААААА 6
2.2 Pipelined, Burst Bus ААААААААААААААААА 6
2.3 Flexible DMA Controller ААААААААААААА 6
2.4 Priority Interrupt Controller ААААААААААА 6
2.5 Instruction Set Summary ААААААААААААА 7
3.0 PACKAGE INFORMATION АААААААААААА 8
3.1 Package Introduction АААААААААААААААА 8
3.2 Pin Descriptions ААААААААААААААААААААА 8
3.3 80960CF Pinout АААААААААААААААААААА 14
3.4 Mechanical Data ААААААААААААААААААА 18
3.5 Package Thermal Specifications ÀÀÀÀ 20
3.6 Stepping Register Information АААААА 21
3.7 Suggested Sources for 80960CF
Accessories
ААААААААААААААААААААААААА 21
4.0 ELECTRICAL SPECIFICATIONS ААААА 22
4.1 Absolute Maximum Ratings ААААААААА 22
4.2 Operating Conditions ААААААААААААААА 22
4.3 Recommended Connections АААААААА 22
4.4 DC Specifications АААААААААААААААААА 23
4.5 AC Specifications АААААААААААААААААА 24
5.0 RESET, BACKOFF AND HOLD
ACKNOWLEDGE
ААААААААААААААААААААААА 35
6.0 BUS WAVEFORMS ААААААААААААААААААА 36
CONTENTS PAGE
FIGURES
Figure 1 80960CF Die Photo
АААААААААААА 2
Figure 2 80960CF Block Diagram ААААААА 5
Figure 3 Example Pin Description
Entry АААААААААААААААААААААААААА 8
Figure 4a 80960CF PGA Pinout (View
from Top Side) АААААААААААААААА 16
Figure 4b 80960CF PGA Pinout (View
from Bottom Side)
АААААААААААА 17
Figure 5 168-Lead Ceramic PGA
Package Dimensions
ААААААААА 18
Figure 6 80960CF PGA Package
Thermal Characteristics ААААААА 20
Figure 7 Measuring 80960CF PGA
Case Temperature АААААААААААА 21
Figure 8 Register G0 АААААААААААААААААА 21
Figure 9 AC Test Load ААААААААААААААААА 30
Figure 10a Input and Output Clocks
Waveform
АААААААААААААААААААА 30
Figure 10b CLKIN Waveform ААААААААААААА 30
Figure 11 Output Delay and Float
Waveform АААААААААААААААААААА 31
Figure 12a Input Setup and Hold
Waveform
АААААААААААААААААААА 31
Figure 12b NMI, XINT7:0 Input Setup
and Hold Waveform
АААААААААА 31
Figure 13 Hold Acknowledge
Timings ААААААААААААААААААААААА 32
Figure 14 Bus Back-Off (BOFF)
Timings ААААААААААААААААААААААА 32
3
CONTENTS PAGE
Figure 15 Relative Timings
Waveforms
АААААААААААААААААААА 33
Figure 16 Output Delay or Hold vs Load
Capacitance
АААААААААААААААААА 33
Figure 17 Rise and Fall Time Derating at
Highest Operating
Temperature and Minimum
V
CC
ААААААААААААААААААААААААААА 34
Figure 18 ICCvs Frequency and
Temperature АААААААААААААААААА 34
Figure 19 Cold Reset Waveform ААААААААА 36
Figure 20 Warm Reset Waveform АААААААА 37
Figure 21 Entering the ONCE State АААААА 38
Figure 22a Clock Synchronization in the
2x Clock Mode АААААААААААААААА 39
Figure 22b Clock Synchronization in the
1x Clock Mode АААААААААААААААА 39
Figure 23 Non-Burst, Non-Pipelined
Requests without Wait
States
АААААААААААААААААААААААА 40
Figure 24 Non-Burst, Non-Pipelined
Read Request with Wait
States АААААААААААААААААААААААА 41
Figure 25 Non-Burst, Non-Pipelined
Write Request with Wait
States
АААААААААААААААААААААААА 42
Figure 26 Burst, Non-Pipelined Read
Request without Wait States,
32-Bit Bus
ААААААААААААААААААААА 43
Figure 27 Burst, Non-Pipelined Read
Request with Wait States,
32-Bit Bus
ААААААААААААААААААААА 44
Figure 28 Burst, Non-Pipelined Write
Request without Wait States,
32-Bit Bus
ААААААААААААААААААААА 45
Figure 29 Burst, Non-Pipelined Write
Request with Wait States,
32-Bit Bus ААААААААААААААААААААА 46
Figure 30 Burst, Non-Pipelined Read
Request with Wait States,
16-Bit Bus ААААААААААААААААААААА 47
CONTENTS PAGE
Figure 31 Burst, Non-Pipelined Read
Request with Wait States,
8-Bit Bus
ААААААААААААААААААААА 48
Figure 32 Non-Burst, Pipelined Read
Request without Wait States,
32-Bit Bus АААААААААААААААААААА 49
Figure 33 Non-Burst, Pipelined Read
Request with Wait States,
32-Bit Bus
АААААААААААААААААААА 50
Figure 34 Burst, Pipelined Read
Request without Wait States,
32-Bit Bus
АААААААААААААААААААА 51
Figure 35 Burst, Pipelined Read
Requests with Wait States,
32-Bit Bus
АААААААААААААААААААА 52
Figure 36 Burst, Pipelined Read
Requests with Wait States,
16-Bit Bus
АААААААААААААААААААА 53
Figure 37 Burst, Pipelined Read
Requests with Wait States,
8-Bit Bus ААААААААААААААААААААА 54
Figure 38 Using External READY АААААААА 55
Figure 39 Terminating a Burst with
BTERM
АААААААААААААААААААААА 56
Figure 40 BOFF Functional Timing АААААА 57
Figure 41 HOLD Functional Timing АААААА 57
Figure 42 DREQ and DACK Functional
Timing АААААААААААААААААААААААА 58
Figure 43 EOP Functional Timing ААААААА 58
Figure 44 Terminal Count Functional
Timing
АААААААААААААААААААААААА 59
Figure 45 FAIL Functional Timing ААААААА 59
Figure 46 A Summary of Aligned and
Unaligned Transfers for Little
Endian Regions
ААААААААААААААА 60
Figure 47 A Summary of Aligned and
Unaligned Transfers for Little
Endian Regions
(Continued)
ААААААААААААААААААА 61
Figure 48 Idle Bus Operation АААААААААААА 62
4
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
1.0 PURPOSE
This document previews electrical characterizations
of Intel’s i960 CF embedded microprocessor (available in 33, 25 and 16 MHz). For a detailed description of any i960 CF processor functional topicÐother than parametric performanceÐrefer to the latest
i960 CA Microprocessor Reference Manual (Order
No. 270710) and the
i960 CF Reference Manual Ad-
dendum
(Order No. 272188).
2.0 i960 CF PROCESSOR OVERVIEW
Intel’s i960 CF microprocessor is the performance
follow-on product to the i960 CA processor. The
i960 CF product is socket- and object code-compatible with the CA; this makes CA-to-CF design upgrades straightforward. The i960 CF processor’s instruction cache is 4 Kbytes (CA device has 1 Kbyte);
CF data cache is 1 Kbyte (CA device has no data
cache). This extra cache on the CF product adds a
significant performance boost over the CA. The
80960CF is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip peripherals, and instruction set extensions to shift 64bit operands and configure on-chip hardware. Multiple 128-bit internal busses, on-chip instruction caching and a sophisticated instruction scheduler allow
the processor to sustain execution of two instruc-
tions every clock, and peak at execution of three
instructions per clock.
A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte/s bandwidth to a system’s highspeed external memory sub-system. In addition, the
80960CF’s on-chip caching of instructions, procedure context and critical program data substantially
decouples system performance from the wait states
associated with accesses to the system’s slower,
cost sensitive, main memory sub-system.
The 80960CF bus controller also integrates full wait
state and bus width control for highest system performance with minimal system design complexity.
Unaligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CF.
The processor also integrates four complete datachaining DMA channels and a high-speed interrupt
controller on-chip. The DMA channels perform: single-cycle or two-cycle transfers, data packing and
unpacking, and data chaining. Block transfers, in addition to source or destination synchronized transfers, are provided.
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (‘‘latency’’) time of
750 ns.
271328– 2
Figure 2. 80960CF Block Diagram
5
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
2.1. The C-Series Core
The C-Series core is a very high performance microarchitectural implementation of the 80960 Core Architecture. The C-Series core can sustain execution
of two instructions per clock (66 MIPs at 33 MHz).
To achieve this level of performance, Intel has incorporated state-of-the-art silicon technology and innovative microarchitectural constructs into the implementation of the C-Series core. Factors that contribute to the core’s performance include:
Ð Parallel instruction decoding allows issue of up
to three instructions per clock.
Ð Most instructions execute in a single clock.
Ð Parallel instruction decode allows sustained,
simultaneous execution of two single-clock instructions every clock cycle.
Ð Efficient instruction pipeline minimizes pipeline
break losses.
Ð Register and resource scoreboarding allow
simultaneous multi-clock instruction execution.
Ð Branch look-ahead and prediction allows many
branches to execute with no pipeline break.
Ð Local Register Cache integrated on-chip caches
Call/Return context.
Ð Two-way set associative, 4 Kbyte integrated in-
struction cache.
Ð Direct mapped, 1 Kbyte data cache, write
through, write allocate.
Ð 1 Kbyte integrated Data RAM sustains a four-
word (128-bit) access every clock cycle.
2.2. Pipelined, Burst Bus
A 32-bit high performance bus controller interfaces
the 80960CF to external memory and peripherals.
The Bus Control Unit features a maximum transfer
rate of 132 Mbytes per second (at 33 MHz). Internally programmable wait states and 16 separately configurable memory regions allow the processor to interface with a variety of memory subsystems with a
minimum of system complexity and a maximum of
performance. The Bus Controller’s main features include:
Ð Demultiplexed, Burst Bus to exploit most efficient
DRAM access modes.
Ð Address Pipelining to reduce memory cost while
maintaining performance.
Ð 32-, 16- and 8-bit modes for I/O interfacing ease.
Ð Full internal wait state generation to reduce sys-
tem cost.
Ð Little and Big Endian support to ease application
development.
Ð Unaligned access support for code portability.
Ð Three-deep request queue to decouple the bus
from the core.
2.3. Flexible DMA Controller
A four channel DMA controller provides high speed
DMA control for data transfers involving peripherals
and memory. The DMA provides advanced features
such as data chaining, byte assembly and disassembly, and a high performance fly-by mode capable of
transfer speed of up to 59 Mbytes per second at
33 MHz. The DMA controller features a performance
and flexibility which is only possible by integrating
the DMA controller and the 80960CF core.
2.4. Priority Interrupt Controller
A programmable-priority interrupt controller manages up to 248 external sources through the 8-bit
external interrupt port. The Interrupt Unit also handles the four internal sources from the DMA controller, and a single non-maskable interrupt input. The
8-bit interrupt port can also be configured to provide
individual interrupt sources that are level or edge
triggered.
Interrupts in the 80960CF are prioritized and signaled within 270 ns of the request. If the interrupt is
of higher priority than the processor priority, the context switch to the interrupt routine typically is complete in another 480 ns. The interrupt unit provides
the mechanism for the low latency and high throughput interrupt service which is essential for embedded
applications.
6
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
2.5. Instruction Set Summary
The following table summarizes the 80960CF instruction set by logical groupings. See the
i960 CA Microproc-
essor Reference Manual
for a complete description of the instruction set.
Data Arithmetic Logical Bit, Bit Field
Movement and Byte
Load Add And Set Bit
Store Subtract Not And Clear Bit
Move Multiply And Not Not Bit
Load Address Divide Or Alter Bit
Remainder Exclusive Or Scan for Bit
Modulo Not Or Span over Bit
Shift Or Not Extract
*Extended Nor Modify
Shift Exclusive Nor Scan Byte for Equal
Extended Not
Multiply Nand
Extended
Divide
Add with
Carry
Subtract with
Carry
Rotate
Comparison Branch Call and Return Fault
Compare Unconditional Call Conditional
Conditional Branch Call Extended Fault
Compare Conditional Call System Synchronize
Compare and Branch Return Faults
Increment Compare and Branch and Link
Compare and Branch
Decrement
Test Condition Code
Check Bit
Debug Processor Atomic
Management
Modify Trace Modify Atomic Add
Controls Process Atomic Modify
Mark Controls
Force Mark Modify
Arithmetic
Controls
*System Control
*DMA Control
Flush Local
Registers
NOTE:
Instructions marked by (*) are 80960CF extensions to the 80960 instruction set.
7
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
3.0 PACKAGE INFORMATION
3.1. Package Introduction
This section describes the pins, pinouts and thermal
characteristics for the 80960CF in the 168-pin Ceramic Pin Grid Array (PGA) package. For complete
package specifications and information, see the Intel
Packaging Outlines and Dimensions Guide
(Order
No. 231369).
3.2. Pin Descriptions
The 80960CF pins are described in this section. Table 1 presents the legend for interpreting the pin descriptions in the following tables.
Pins associated with the 32-bit demultiplexed processor bus are described in Table 2. Pins associated
with basic processor configuration and control are
described in Table 3. Pins associated with the
80960CF DMA Controller and Interrupt Unit are described in Table 4.
Figure 3 provides an example pin description table
entry. ‘‘I/O’’ signifies that data pins are input-output.
‘‘S’’ indicates pins are synchronous to PCLK2:1.
‘‘H(Z)’’ indicates that these pins float while the processor bus is in a Hold Acknowledge state. ‘‘R(Z)’’
indicates that the pins also float while RESET
is low.
All pins float while the processor is in the ONCE
mode.
Table 1. Pin Description Nomenclature
Symbol Description
I Input only pin
O Output only pin
I/O Pin can be either an input or output
- Pins ‘‘must be’’ connected as
described
S(...) Synchronous. Inputs must meet setup
and hold times relative to PCLK2:1 for
proper operation. All outputs are
synchronous to PCLK2:1.
S(E) Edge sensitive input
S(L) Level sensitive input
A(...) Asynchronous. Inputs may be
asynchronous to PCLK2:1.
A(E) Edge sensitive input
A(L) Level sensitive input
H(...) While the processor’s bus is in the
Hold Acknowledge or Bus Backoff
state, the pin:
H(1) is driven to V
CC
H(0) is driven to V
SS
H(Z) floats
H(Q) continues to be a valid output
R(...) While the processor’s RESET pin is
low, the pin
R(1) is driven to V
CC
R(0) is driven to V
SS
R(Z) floats
R(Q) continues to be a valid output
Name Type Description
D31:0 I/O DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configuration.
The least significant bit of the data is carried on D0 and the most significant on D31. When
S(L)
the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-bit bus
H(Z)
widths, D15:0 are used. For 32-bit bus widths the full data bus is used.
R(Z)
Figure 3. Example Pin Description Entry
8
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 2. 80960CF Pin DescriptionÐExternal Bus Signals
Name Type Description
A31:2 O ADDRESS BUS carries the physical address upper 30 bits. A31 is the most
significant address bit and A2 is the least significant. During a bus access, A31:2
S
identify all external addresses to word (4-byte) boundaries. The byte enable
H(Z)
signals indicate the selected byte in each word. During burst accesses, A3 and A2
R(Z)
increment to indicate successive data cycles.
D31:0 I / O DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width
configuration. The least significant bit of the data is carried on D0 and the most
S(L)
significant on D31. When the bus is configured for 8-bit data, the lower 8 data
H(Z)
lines, D7:0 are used. For 16-bit bus widths, D15:0 are used. For 32-bit bus widths
R(Z)
the full data bus is used.
BE3 O BYTE ENABLES select which of the four bytes addressed by A31:2 are active
during an access to a memory region configured for a 32-bit data-bus width. BE3
BE2 S
applies to D31:24; BE2 applies to D23:16; BE1 applies to D15:8; and BE0 applies
BE1 H(Z)
to D7:0.
BE0
R(1)
32-bit bus: BE3
–Byte Enable 3 –enable D31:24
BE2
–Byte Enable 2 –enable D23:16
BE1
–Byte Enable 1 –enable D15:8
BE0
–Byte Enable 0 –enable D7:0
For accesses to a memory region configured for a 16-bit data-bus width, the
processor directly encodes BE3, BE1 and BE0 to provided BHE, A1 and BLE
respectively.
16-bit bus: BE3 –Byte High Enable (BHE) –enable D15:8
BE2
–Not used (is driven high or low)
BE1
–Address Bit 1 (A1)
BE0
–Byte Low Enable (BLE) –enable D7:0
For accesses to a memory region configured for an 8-bit data bus width, the
processor directly encodes BE1
and BE0 to provide A1 and A0 respectively.
8-bit bus: BE3 –Not used (is driven high or low)
BE2
–Not used (is driven high or low)
BE1
–Address Bit 1 (A1)
BE0 –Address Bit 0 (A0)
W/R O WRITE/READ is asserted for read requests and deasserted for write requests.
The W/R
signal changes in the same clock cycle as ADS. It remains valid for the
S
entire access in non-pipelined regions. In pipelined regions, W/R
is not
H(Z)
guaranteed valid in the last cycle of a read access.
R(0)
ADS O ADDRESS STROBE indicates valid address and the start of a new bus access.
ADS
is asserted for the first clock of a bus access.
S
H(Z)
R(1)
READY I READY is an input which signals the termination of a data transfer. READY is
used to indicate that read data on the bus is valid, or that a write-data transfer has
S(L)
completed. The READY
signal works in conjunction with the internally
H(Z)
programmed wait-state generator. If READY
is enabled in a region, the pin is
R(Z)
sampled after the programmed number of wait-states has expired. If the READY
pin is deasserted, wait states continue to be inserted until READY becomes
asserted. This is true for the N
RAD,NRDD,NWAD
, and N
WDD
wait states. The
N
XDA
wait states cannot be extended.
9
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 2. 80960CF Pin DescriptionÐExternal Bus Signals (Continued)
Name Type Description
BTERM I BURST TERMINATEÐThe burst terminate signal breaks up a burst access and
causes another address cycle to occur. The BTERM
signal works in conjunction
S(L)
with the internally programmed wait-state generator. If READY
and BTERM are
H(Z)
enabled in a region, the BTERM
pin is sampled after the programmed number of
R(Z)
wait states has expired. When BTERM
is asserted, a new ADS signal is generated
and the access is completed. The READY
input is ignored when BTERM
is
asserted. BTERM must be externally synchronized to satisfy the BTERM setup
and hold times.
WAIT O WAIT indicates internal wait state generator status. WAIT is asserted when wait
states are being caused by the internal wait state generator and not by the
S
READY
or BTERM inputs. WAIT can be used to derive a write-data strobe. WAIT
H(Z)
can also be thought of as a READY output that the processor provides when it is
R(1)
inserting wait states.
BLAST O BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the
last data transfer of burst and non-burst accesses after the wait state counter
S
reaches zero. BLAST
remains asserted until the clock following the last cycle of
H(Z)
the last data transfer of a bus access. If the READY
or BTERM input is used to
R(0)
extend wait states, the BLAST
signal remains asserted until READY or BTERM
terminates the access.
DT/R O DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is
used in conjunction with DEN to provide control for data transceivers attached to
S
the external bus. When DT/R
is asserted, the signal indicates that the processor
H(Z)
receives data. Conversely, when deasserted, the processor sends data. DT/R
R(0)
changes only while DEN
is high.
DEN O DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the
start of the bus request first data cycle and is deasserted at the end of the last
S
data cycle. DEN
is used in conjunction with DT/R to provide control for data
H(Z)
transceivers attached to the external bus. DEN
remains asserted for sequential
R(1)
reads from pipelined memory regions. DEN is deasserted when DT/R changes.
LOCK O BUS LOCK indicates that an atomic read-modify-write operation is in progress.
LOCK
may be used to prevent external agents from accessing memory which is
S
currently involved in an atomic operation. LOCK
is asserted in the first clock of an
H(Z)
atomic operation, and deasserted in the clock cycle following the last bus access
R(1)
for the atomic operation. To allow the most flexibility for a memory system
enforcement of locked accesses, the processor acknowledges a bus hold request
when LOCK is asserted. The processor performs DMA transfers while LOCK is
active.
HOLD I HOLD REQUEST signals that an external agent requests access to the external
bus. The processor asserts HOLDA after completing the current bus request.
S(L)
HOLD, HOLDA and BREQ are used together to arbitrate access to the
H(Z)
processor’s external bus by external bus agents.
R(Z)
BOFF I BUS BACKOFF ÐThe backoff pin, when asserted, suspends the current access
and causes the bus pins to float. When deasserted, the ADS signal is asserted on
S(L)
the next clock cycle and the access is resumed.
H(Z)
R(Z)
10
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 2. 80960CF Pin DescriptionÐExternal Bus Signals (Continued)
Name Type Description
HOLDA O HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has
relinquished control of the external bus. When HOLDA is asserted, the external
S
address bus, data bus and bus control signals are floated. HOLD, BOFF
, HOLDA
H(1)
and BREQ are used together to arbitrate access to the processor’s external bus
R(Q)
by external bus agents. Since the processor grants HOLD requests and enters the
Hold Acknowledge state even while RESET
is asserted, HOLDA pin state is
independent of the RESET pin.
BREQ O BUS REQUEST is asserted when the bus controller has a request pending. BREQ
can be used by external bus arbitration logic in conjunction with HOLD and
S
HOLDA to determine when to return mastership of the external bus to the
H(Q)
processor.
R(0)
D/C O DATA OR CODE is asserted for a data request and deasserted for instruction
requests. D/C has the same timing as W/R.
S
H(Z)
R(Z)
DMA O DMA ACCESS indicates whether the bus request was initiated by the DMA
controller. DMA
is asserted for any DMA request. DMA
is deasserted for all other
S
requests.
H(Z)
R(Z)
SUP O SUPERVISOR ACCESS indicates whether the bus request is issued while in
supervisor mode. SUP
is asserted when the request has supervisor privileges, and
S
is deasserted otherwise. SUP
can be used to isolate supervisor code and data
H(Z)
structures from non-supervisor requests.
R(Z)
Table 3. 80960CF Pin DescriptionÐProcessor Control Signals
Name Type Description
RESET I RESET causes the chip to reset. When RESET is asserted, all external signals return
to the reset state. When RESET
is deasserted, initialization begins. When the 2-x clock
A(L)
mode is selected, RESET
must remain asserted for 16 PCLK2:1 cycles before being
H(Z)
deasserted in order to guarantee correct processor initialization. When the 1-x clock
R(Z)
mode is selected, RESET
must remain asserted for 10,000 PCLK2:1 cycles before
N(Z)
being deasserted in order to guarantee correct initialization. The CLKMODE pin
selects 1-x or 2-x input clock division of the CLKIN pin.
The processor’s Hold Acknowledge bus state functions while the chip is reset. If the
processor’s bus is in the Hold Acknowledge state when RESET
is asserted, the
processor will internally reset, but maintains the Hold Acknowledge state on external
pins until the Hold request is removed. If a hold request is made while the processor is
in the reset state, the processor bus grants HOLDA and enters the Hold Acknowledge
state.
FAIL O FAIL indicates failure of the processor’s self-test performed at initialization. When
RESET
is deasserted and the processor begins initialization, the FAIL pin is asserted.
S
An internal self-test is performed as part of the initialization process. If this self-test
H(Q)
passes, the FAIL
pin is deasserted otherwise it remains asserted. The FAIL pin is
R(0)
reasserted while the processor performs an external bus self-confidence test. If this
self-test passes, the processor deasserts the FAIL
pin and branches to the user’s
initialization routine; otherwise the FAIL
pin remains asserted. Internal self-test and the
use of the FAIL
pin can be disabled with the STEST pin.
11
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 3. 80960CF Pin DescriptionÐProcessor Control Signals (Continued)
Name Type Description
STEST I SELF TEST causes the processor’s internal self-test feature to be enabled or
disabled at initialization. STEST is read on the rising edge of RESET
. When asserted,
S(L)
the processor’s internal self-test and external bus confidence tests are performed
H(Z)
during processor initialization. When deasserted, only the external bus confidence
R(Z)
tests are performed during initialization.
ONCE I ON CIRCUIT EMULATION causes all outputs to be floated when asserted. ONCE is
continuously sampled while RESET
is low, and is latched on the rising edge of
A(L)
RESET
. To place the processor in the ONCE state:
H(Z)
(1) assert RESET
and ONCE
(order does not matter)
R(Z)
(2) wait for at least 16 CLKIN periods in 2-x mode, or 10,000 CLKIN periods in 1-x
mode, after V
CC
and CLKIN are within operating specifications
(3) deassert RESET
(4) wait at least 32 CLKIN periods
(The processor is now latched in the ONCE state as long as RESET is high.)
To exit the ONCE state, bring V
CC
and CLKIN to operating conditions, then assert
RESET
and bring ONCE high prior to deasserting RESET.
CLKIN must operate within the specified operating conditions of the processor until
step 4 above is completed. The CLKIN may then be changed to DC to achieve the
lowest possible ONCE mode leakage current.
ONCE can be used by emulator products or for board testers to effectively make an
installed processor transparent in the board.
CLKIN I CLOCK INPUT is an input for the external clock needed to run the processor. The
external clock is internally divided as prescribed by the CLKMODE pin to produce
A(E)
PCLK2:1.
H(Z)
R(Z)
CLKMODE I CLOCK MODE selects the division factor applied to the external clock input (CLKIN).
When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the
A(L)
processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to create
H(Z)
PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high or low in
R(Z)
a system, as the clock mode is not latched by the processor. If left unconnected, the
processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode.
PCLK2 O PROCESSOR OUTPUT CLOCKS provide a timing reference for all inputs and
outputs of the processor. All inputs and output timings are specified in relation to
PCLK1 S
PCLK2 and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are
H(Q)
provided to allow flexibility in the system’s allocation of capacitive loading on the
R(Q)
clock. PCLK2:1 may also be connected at the processor to form a single clock signal.
V
SS
Ð GROUND connections consist of 24 pins which must be connected externally to a
V
SS
board plane.
V
CC
Ð POWER connections consist of 24 pins which must be connected externally to a V
CC
board plane.
V
CCPLL
ÐV
CCPLL
is a separate VCCsupply pin for the phase lock loop used in 1x clock mode.
Connecting a simple low pass filter to V
CCPLL
may help reduce clock jitter (TCP)in
noisy environments. Otherwise, V
CCPLL
should be connected to VCC.
N/C Ð NO CONNECT pins must not be connected in a system.
12
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 4. 80960CF Pin DescriptionÐDMA and Interrupt Unit Control Signals
Name Type Description
DREQ3 I DMA REQUEST causes a DMA transfer to be requested. Each of the four signals
request a transfer on a single channel. DREQ0
requests channel 0, DREQ1 requests
DREQ2
A(L)
channel 1, etc. When two or more channels are requested simultaneously, the
DREQ1
H(Z)
channel with the highest priority is serviced first. Channel priority mode is
DREQ0
R(Z)
programmable.
DACK3 O DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of the
four signals acknowledge a transfer for a single channel. DACK0
acknowledges
DACK2
S
channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are asserted when the
DACK1
H(1)
requesting device of a DMA is accessed.
DACK0
R(1)
EOP3/TC3 I / O END OF PROCESS/TERMINAL COUNT can be programmed as either an input
(EOP3:0
) or as an output (TC3:0), but not both. Each pin is individually
EOP2/TC2
A(L)
programmable. When programmed as an input, EOPx causes the termination of a
EOP1/TC1
H(Z/Q)
current DMA transfer for the channel corresponding to the EOPx pin. EOP0
EOP0/TC0 R(Z)
corresponds to channel 0, EOP1
corresponds to channel 1, etc. When a channel is
configured for source
and
destination chaining, the EOP pin for that channel causes
termination of only the current buffer transferred and causes the next buffer to be
transferred. EOP3:0
are asynchronous inputs.
When programmed as an output, the channel’s TCx
pin indicates that the channel
byte count has reached 0 and a DMA has terminated. TCx
is driven with the same
timing as DACKx
during the last DMA transfer for a buffer. If the last bus request is
executed as multiple bus accesses, TCx remains asserted for the entire bus request.
XINT7 I EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins can be
configured in three modes.
XINT6
A(E/L)
In Dedicated Mode, each pin is a dedicated external interrupt source. Dedicated
XINT5
H(Z)
inputs can be individually programmed to be level (low) or edge (falling) activated.
XINT4
R(Z)
In Expanded Mode, the 8 pins act together as an 8-bit vectored interrupt source. The
XINT3
interrupt pins in this mode are level activated. Since the interrupt pins are active low,
XINT2
the vector number requested is the one’s complement of the positive logic value
XINT1
place on the port. This eliminates glue logic to interface to combinational priority
XINT0
encoders which output negative logic.
In Mixed Mode, XINT7:5
are dedicated sources and XINT4:0 act as the 5 most
significant bits of an expanded mode vector. The least significant bits are set to 010
internally.
NMI I NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated
A(E)
source.
H(Z)
R(Z)
13
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
3.3. 80960CF Pinout
3.3.1 80960CF PGA PINOUT
Tables 5 and 6 list the 80960CF pin names with
package location. Figure 4-a depicts the complete
80960CF pinout as viewed from the top side of the
component (i.e., pins facing down). Figure 4b shows
the complete 80960CF pinout as viewed from the
pin-side of the package (i.e., pins facing up). See
Section 4.0, Electrical Specifications for specifications and recommended connections.
Table 5. PGA Pin Name with Package Location (Signal Order)
Address Bus Data Bus Bus Control Processor Control I/O
Name ÀÀLocation Name ÀÀLocation Name ÀÀLocation Name ÀÀÀÀLocation Name ÀÀLocation
A31 ААААААААS15 D31 ААААААААR03 BE3 ААААААААS05 RESET АААААААA16 DREQ3 АААААA07
A30 ААААААААQ13 D30ААААААААQ05 BE2 ААААААААS06 DREQ2 АААААB06
A29 ААААААААR14 D29 ААААААААS02 BE1 ААААААААS07 FAIL ААААААААААA02 DREQ1 АААААA06
A28 ААААААААQ14 D28ААААААААQ04 BE0 ААААААААR09 DREQ0 АААААB05
A27 ААААААААS16 D27 ААААААААR02 STESTААААААААB02
A26 ААААААААR15 D26 ААААААААQ03 W/R АААААААS10 DACK3 АААААA10
A25 ААААААААS17 D25 ААААААААS01 ONCE ААААААААC03 DACK2 АААААA09
A24 ААААААААQ15 D24 ААААААААR01 ADS АААААААR06 DACK1 АААААA08
A23 ААААААААR16 D23 ААААААААQ02 CKLIN ААААААААC13 DACK0 АААААB08
A22 ААААААААR17 D22 ААААААААP03 READY АААААS03 CLKMODE ÀÀÀÀC14
A21 ААААААААQ16 D21ААААААААQ01 BTERMАААААR04 PCLK1 ААААААААB14 EOP/TC0 ÀÀÀA11
A20 ААААААААP15 D20 ААААААААP02 PCLK2ААААААААB13 EOP/TC1 ÀÀÀA12
A19 ААААААААP16 D19 ААААААААP01 WAIT АААААААS12 EOP/TC2 ÀÀÀA13
A18 ААААААААQ17 D18 ААААААААN02 BLAST АААААS08 V
SS
EOP/TC3 ÀÀÀA14
A17 ААААААААP17 D17 ААААААААN01
Location
A16 ААААААААN16 D16ААААААААM01 DT/RАААААААS11 C07, C08, C09, XINT7 ААААААC17
C10, C11, C12,
A15 ААААААААN17 D15 ААААААААL01 DEN АААААААS09 XINT6 ААААААC16
F15, G03, G15,
A14ААААААААM17 D14 ААААААААL02 XINT5 ААААААB17
H03, H15, J03,
J15, K03, K15,
A13 ААААААААL16 D13 ААААААААK01 LOCK
ААААААS14 XINT4 ААААААC15
L03, L15, M03,
A12 ААААААААL17 D12 ААААААААJ01 XINT3
ААААААB16
M15, Q07, Q08,
Q09, Q10, Q11
A11 ААААААААK17 D11 ААААААААH01 HOLD ААААААR05 XINT2
ААААААA17
A10 ААААААААJ17 D10 ААААААААH02 HOLDA АААААS04 V
CC
XINT1 ААААААA15
A9 АААААААААH17 D9 АААААААААG01 BREQ ААААААR13
Location
XINT0 ААААААB15
A8 АААААААААG17 D8 АААААААААF01 B07, B09,
B11, B12, C06,
A7 АААААААААG16 D7 АААААААААE01 D/C ААААААААS13 NMI ААААААААD15
E15, F03, F16,
A6 АААААААААF17 D6 АААААААААF02 DMA АААААААR12
G02, H16, J02,
J16, K02, K16, M02,
A5 АААААААААE17 D5 АААААААААD01 SUP АААААААQ12
M16, N03, N15,
A4 АААААААААE16 D4 АААААААААE02
Q06, R07, R08,
R10, R11
V
CCPLL
АААААААB10
A3 АААААААААD17 D3 АААААААААC01 BOFF ААААААB01 No Connect
A2 АААААААААD16 D2 АААААААААD02
Location
D1 АААААААААC02 A01, A03, A04, A05,
B03, B04, C04, C05,
D03
D0 АААААААААE03
14
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 6. PGA Pin Name with Package Location (Pin Order)
Address Bus Data Bus Bus Control Processor Control I/O
Location ÀÀName Location ÀÀName Location ÀÀName Location ÀÀÀÀName Location ÀÀName
A01 АААААААААNC C01 АААААААААD3 G01 АААААААААD9 M01 АААААААААD16 R01 ААААААААD24
A02 АААААААFAIL C02 АААААААААD1 G02ААААААААV
CC
M02 АААААААААV
CC
R02 ААААААААD27
A03 АААААААААNC C03 ААААААONCE G03 ААААААААV
SS
M03ААААААААААV
SS
R03 ААААААААD31
A04 АААААААААNC C04АААААААААNC G15 ААААААААV
SS
M15ААААААААААV
SS
R04АААААBTERM
A05 АААААААААNC C05АААААААААNC G16 АААААААААA7 M16 АААААААААV
CC
R05 ААААААHOLD
A06 АААААDREQ1 C06 ААААААААV
CC
G17 АААААААААA8 M17ААААААААААA14 R06 АААААААADS
A07 АААААDREQ3 C07 ААААААААV
SS
R07 ААААААААV
CC
A08 АААААDACK1 C08 ААААААААV
SS
H01 ААААААААD11 N01ААААААААААD17 R08 ААААААААV
CC
A09 АААААDACK2 C09 ААААААААV
SS
H02 ААААААААD10 N02ААААААААААD18 R09 ААААААААBE0
A10 АААААDACK3 C10 ААААААААV
SS
H03 ААААААААV
SS
N03ААААААААААV
CC
R10 ААААААААV
CC
A11 ÀÀÀEOP/TC0 C11 ААААААААV
SS
H15 ААААААААV
SS
N15ААААААААААV
CC
R11 ААААААААV
CC
A12 ÀÀÀEOP/TC1 C12 ААААААААV
SS
H16 ААААААААV
CC
N16 ААААААААААA16 R12 АААААААDMA
A13 АААEOP/TC2 C13ААААААCLKIN H17 АААААААААA9 N17ААААААААААA15 R13 ААААААBREQ
A14 АААEOP/TC3 C14 ÀÀCLKMODE R14 ААААААААA29
A15 ААААААXINT1 C15 ААААААXINT4 J01 ААААААААD12 P01 ААААААААААD19 R15 ААААААААA26
A16 АААААRESET C16 ААААААXINT6 J02 ААААААААV
CC
P02 ААААААААААD20 R16 ААААААААA23
A17 ААААААXINT2 C17 ААААААXINT7 J03 ААААААААV
SS
P03 ААААААААААD22 R17 ААААААААA22
J15 ААААААААV
SS
P15 ААААААААААA20
B01 ААААААBOFF D01 АААААААААD5 J16 ААААААААV
CC
P16 ААААААААААA19 S01 ААААААААD25
B02 АААААSTEST D02 АААААААААD2 J17 ААААААААA10 P17 ААААААААААA17 S02 ААААААААD29
B03 АААААААААNC D03АААААААААNC S03 АААААREADY
B04 АААААААААNC D15 ААААААААNMI K01 ААААААААD13 Q01 ААААААААААD21 S04 АААААHOLDA
B05 АААААDREQ0 D16 АААААААААA2 K02 ААААААААV
CC
Q02ААААААААААD23 S05 ААААААААBE3
B06 АААААDREQ2 D17 АААААААААA3 K03 ААААААААV
SS
Q03ААААААААААD26 S06 ААААААААBE2
B07 ААААААААV
CC
K15 ААААААААV
SS
Q04ААААААААААD28 S07 ААААААААBE1
B08 АААААDACK0 E01 АААААААААD7 K16 ААААААААV
CC
Q05ААААААААААD30 S08 АААААBLAST
B09 ААААААААV
CC
E02 АААААААААD4 K17 ААААААААA11 Q06ААААААААААV
CC
S09 АААААААDEN
B10 АААААV
CCPLL
E03 АААААААААD0 Q07 ААААААААААV
SS
S10 АААААААW/R
B11 ААААААААV
CC
E15 ААААААААV
CC
L01 ААААААААD15 Q08 ААААААААААV
SS
S11АААААААDT/R
B12 ААААААААV
CC
E16 АААААААААA4 L02 ААААААААD14 Q09 ААААААААААV
SS
S12АААААААWAIT
B13 АААААPCLK2 E17 АААААААААA5 L03 ААААААААV
SS
Q10 ААААААААААV
SS
S13 ААААААААD/C
B14 АААААPCLK1 L15 ААААААААV
SS
Q11 ААААААААААV
SS
S14 ААААААLOCK
B15 ААААААXINT0 F01 АААААААААD8 L16 ААААААААA13 Q12 АААААААААSUP S15 ААААААААA31
B16 ААААААXINT3 F02 АААААААААD6 L17 ААААААААA12 Q13 ААААААААААA30 S16 ААААААААA27
B17 ААААААXINT5 F03 ААААААААV
CC
Q14ААААААААААA28 S17 ААААААААA25
F15 ААААААААV
SS
Q15ААААААААААA24
F16 ААААААААV
CC
Q16ААААААААААA21
F17 АААААААААA6 Q17ААААААААААA18
15
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328– 3
Figure 4a. 80960CF PGA Pinout (View from Top Side)
16
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
271328– 4
Figure 4b. 80960CF PGA Pinout (View from Bottom Side)
17
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
3.4. Mechanical Data
3.4.1 CERAMIC PGA PACKAGE
271328– 5
Family: Ceramic Pin Grid Array Package
Symbol
Millimeters Inches
Min Max Notes Min Max Notes
A 3.56 4.57 0.140 0.180
A
1
0.64 1.14 SOLID LID 0.025 0.045 SOLID LID
A
2
23 0.30 SOLID LID 0.110 0.140 SOLID LID
A
3
1.14 1.40 0.045 0.055
B 0.43 0.51 0.017 0.020
D 44.07 44.83 1.735 1.765
D
1
40.51 40.77 1.595 1.605
e
1
2.29 2.79 0.090 0.110
L 2.54 3.30 0.100 0.130
N 168 168
S
1
1.52 2.54 0.060 0.100
ISSUE IWS REV X 7/15/88
Figure 5. 168-Lead Ceramic PGA Package Dimensions
18
SPECIAL ENVIRONMENT 80960CF-30, -25, -16
Table 7. Ceramic PGA Package Dimension Symbols
Letter or
Description of Dimensions
Symbol
A Distance from seating plane to highest point of body
A
1
Distance between seating plane and base plane (lid)
A
2
Distance from base plane to highest point of body
A
3
Distance from seating plane to bottom of body
B Diameter of terminal lead pin
D Largest overall package dimension of length
D
1
A body length dimension, outer lead center to outer lead center
e
1
Linear spacing between true lead position centerlines
L Distance from seating plane to end of lead
S
1
Other body dimension, outer lead center to edge of body
NOTES:
1. Controlling dimension: millimeter.
2. Dimension ‘‘e
1
’’ (‘‘e’’) is non-cumulative.
3. Seating plane (standoff) is defined by P.C. board hole size: 0.0415– 0.0430 inch.
4. Dimensions ‘‘B’’, ‘‘B
1
’’ and ‘‘C’’ are nominal.
5. Details of Pin 1 identifier are optional.
19
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