Intel Corporation S82595TX Datasheet
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October 1995COPYRIGHT©INTEL CORPORATION, 1996 Order Number: 281630-001
82595TX
ISA/PCMCIA HIGH INTEGRATION
ETHERNET CONTROLLER
Y
Optimal Integration for Lowest Cost
Solution
Ð Glueless 8-Bit/16-Bit ISA/PCMCIA 2.0
Bus Interface
Ð Provides Fully 802.3 Compliant AUI
and TPE Serial Interface
Ð Local DRAM Support up to
64 Kbytes
Ð FLASH/EPROM Boot Support up to
1 Mbyte for Diskless Workstations
Ð Hardware and Software Portable
between Motherboard, Adapter, and
PCMCIA LAN Card Solution
Y
High Performance Networking
Functions
Ð Concurrent Processing Functionality
for Enhanced Performance
Ð 16-Bit/32-Bit IO Accesses to Local
DRAM with Zero Added Wait-States
Ð Ring Buffer Structure for Continuous
Frame Reception and Transmit
Chaining
Ð Automatic Retransmission on
Collision
Ð Automatically Corrects TPE Polarity
Switching Problems
Y
Low Power CHMOS IV Technology
Y
Ease of Use
Ð Integrated Plug N’ Play
TM
Hardware
Functionality
Ð EEPROM Interface to Support
Jumperless Designs
Ð Software Structures Optimized to
Reduce Processing Steps
Ð Automatically Maps into Unused PC
IO Locations to Help Eliminate LAN
Setup Problems
Ð All Software Structures Contained in
One 16-Byte IO Space
Ð JTAG Port for Reduced Board
Testing Times
Ð Automatic or Manual Switching
between TPE and AUI Ports
Y
Power Management
Ð SL Compatible SMOUT Power Down
Input
Ð Software Power Down Command for
Non-SL Systems
Y
144-Lead tQFP Package Provides
Smallest Available Form Factor
Y
100% Backwards Hardware/Software
Compatible to 82595
281630– 1
Figure 1. 82595TX Block Diagram
82595TX
ISA/PCMCIA High Integration ETHERNET Controller
CONTENTS PAGE
1.0 INTRODUCTION ААААААААААААААААААААААА 5
1.1 82595TX Overview АААААААААААААААААА 5
1.2 Enhancements to the 82595 ААААААААА 5
1.3 Compliance to Industry
Standards АААААААААААААААААААААААААААА 5
1.3.1 Bus InterfaceÐISA IEEE
P996/PCMCIA 2.0 ААААААААААААААААА 6
1.3.2 ETHERNET/Twisted Pair
Ethernet InterfaceÐIEEE 802.36
Specification
ААААААААААААААААААААААА 6
2.0 82595TX PIN DEFINITIONS ААААААААААА 6
2.1 ISA Bus Interface АААААААААААААААААААА 6
2.2 PCMCIA Bus Interface ААААААААААААААА 8
2.3 Local Memory Interface АААААААААААААА 9
2.4 Miscellaneous Control АААААААААААААА 11
2.5 JTAG Control АААААААААААААААААААААА 11
2.6 Serial Interface ААААААААААААААААААААА 12
2.7 Power and Ground ААААААААААААААААА 13
2.8 82595TX Pin Summary ААААААААААААА 14
3.0 82595TX INTERNAL
ARCHITECTURE OVERVIEW АААААААААА 15
3.1 System Interface Overview ААААААААА 15
3.1.1 Concurrent Processing
Functionality
АААААААААААААААААААААА 15
3.2 Local Memory Interface АААААААААААА 15
3.3 CSMA/CD Unit ААААААААААААААААААААА 16
3.4 Serial Interface ААААААААААААААААААААА 16
4.0 ACCESSING THE 82595TX ААААААААААА 16
4.1 82595TX Register Map ААААААААААААА 16
4.1.1 IO Bank 0 ААААААААААААААААААААА 17
4.1.2 IO Bank 1 ААААААААААААААААААААА 18
4.1.3 IO Bank 2 ААААААААААААААААААААА 19
4.2 Writing to the 82595TX ААААААААААААА 19
4.3 Reading from the 82595TX ААААААААА 20
CONTENTS PAGE
4.4 Local DRAM Accesses
ААААААААААААА 20
4.4.1 Writing to Local Memory ААААААА 20
4.4.2 Reading from Local
Memory АААААААААААААААААААААААААА 20
4.5 Serial EEPROM Interface ААААААААААА 21
4.6 Boot EPROM/FLASH Interface ААААА 22
4.7 IA PROM Interface ААААААААААААААААА 22
4.8 PCMCIA CIS Structures АААААААААААА 22
4.9 PCMCIA Decode Functions ААААААААА 22
5.0 COMMAND AND STATUS
INTERFACE
АААААААААААААААААААААААААААА 23
5.1 Command OP Code Field ААААААААААА 23
5.2 ABORT (Bit 5) АААААААААААААААААААААА 23
5.3 Pointer Field (Bits 6 and 7) АААААААААА 23
5.4 82595TX Status Interface ААААААААААА 24
6.0 INITIALIZATION АААААААААААААААААААААА 24
7.0 FRAME TRANSMISSION ААААААААААААА 25
7.1 82595TX XMT Block Memory
Format
АААААААААААААААААААААААААААААА 25
7.2 XMT Chaining АААААААААААААААААААААА 27
7.3 Automatic Retransmission on
Collision
ААААААААААААААААААААААААААААА 30
8.0 FRAME RECEPTION ААААААААААААААААА 30
8.1 82595TX RCV Memory
Structure АААААААААААААААААААААААААААА 30
8.2 RCV Ring Buffer Operation ААААААААА 33
9.0 SERIAL INTERFACE ААААААААААААААААА 34
10.0 APPLICATION NOTES АААААААААААААА 35
10.1 Bus Interface АААААААААААААААААААААА 35
10.2 Local Memory Interface ААААААААААА 35
10.3 EEPROM Interface (ISA Only) ААААА 35
10.4 Serial Interface АААААААААААААААААААА 35
10.4.1 AUI Circuit ААААААААААААААААААА 35
10.4.2 TPE Circuit ААААААААААААААААААА 35
10.4.3 LED Circuit ААААААААААААААААААА 36
2
CONTENTS PAGE
10.5 Layout Guidelines
ААААААААААААААААА 36
10.5.1 General АААААААААААААААААААААА 36
10.5.2 Crystal ААААААААААААААААААААААА 36
10.5.3 82595TX Analog Differential
Signals ААААААААААААААААААААААААААА 36
10.5.4 Decoupling
Considerations АААААААААААААААААААА 36
11.0 ELECTRICAL SPECIFICATIONS
AND TIMINGS АААААААААААААААААААААААААА 37
11.1 Absolute Maximum Ratings АААААААА 37
11.1.1 Package Thermal
Specifications ААААААААААААААААААААА 38
CONTENTS PAGE
11.2 A.C. Timing Characteristics
АААААААА 38
11.3 A.C. Measurement Conditions ААААА 38
11.4 ISA Interface Timing ААААААААААААААА 39
11.5 PCMCIA Interface Timing АААААААААА 44
11.6 Local Memory Timings АААААААААААА 47
11.6.1 DRAM Timings ААААААААААААААА 47
11.6.2 FLASH/EPROM Timings ААААА 49
11.6.3 IA PROM Timings АААААААААААА 51
11.7 Interrupt Timing ААААААААААААААААААА 52
11.8 RESET and SMOUT Timing ААААААА 52
11.9 JTAG Timing АААААААААААААААААААААА 53
11.10 Serial Timings ААААААААААААААААААА 54
3
82595TX
281630– 2
Figure 2. 82595TX Pinout
4
82595TX
1.0 INTRODUCTION
1.1 82595TX Overview
The 82595TX is a highly integrated, high performance LAN controller which provides a cost effective
LAN solution for ISA compatible Personal Computer
(PC) motherboards (both desktop and portable),
add-on ISA adapter boards, and PCMCIA cards. The
82595TX integrates all of the major functions of a
buffered LAN solution into one chip with the exception of the local buffer memory, which is implemented by adding one DRAM component to the LAN solution. The 82595TX’s new Concurrent Processing
feature significantly enhances throughput performance. Both system bus and serial link activities occur
concurrently, allowing the 82595TX to maximize network bandwidth by minimizing delays associated
with transmit or receiving frames. The 82595TX’s
bus interface is a glueless attachment to either an
ISA or PCMCIA version 2.0 bus. Its serial interface
provides a Twisted Pair Ethernet (TPE) and an Attachment Unit Interface (AUI) connection. By integrating the majority of the LAN solution functions
into one cost effective component, production cost
saving can be achieved as well as significantly decreasing the design time for a solution. This level of
integration also allows an 82595TX solution to be
ported between different applications (PC motherboards, adapters, and PCMCIA IO cards), while
maintaining a compatible hardware and software
base. This results in further savings in both hardware
and software development costs for manufacturers
expanding into different applications i.e., an ISA
adapter vendor producing PCMCIA IO cards, etc.
The 82595TX’s software interface is optimized to reduce the number of processing steps that are required to interface to the 82595TX solution. The
82595TX’s initialization and control registers are directly addressable within one 16-byte IO address
block. The 82595TX can automatically resolve any
conflicts to an IO block by moving its IO offset to an
unused location in the case that a conflict occurs.
The 82595TX’s local memory is arranged in a simple
ring buffer structure for efficient transfer of transmit
and receive packets. The local memory, up to
64 Kbytes of DRAM, resides as either a 16-bit or 32bit IO port in the host systems IO map programmable through configuration. The 82595TX provides direct control over the local DRAM, including refresh.
The 82595TX performs a prefetch to the DRAM
memory allowing CPU IO cycles to this data with no
added wait-states. The 82595TX also provides an
interface to up to 1 Mbyte of FLASH or EPROM
memory. An interface to an EEPROM, which holds
solution configuration values and can also contain
the Node ID, allows for the implementation of a
‘‘jumperless’’ design. In addition, the 82595TX contains full hardware support for the implementation of
the ISA Plug N’ Play specification. Plug N’ Play eliminates jumpers and complicated setup utilities by allowing peripheral functions to be added to a PC automatically (such as adapter cards) without the need
to individually configure each parameter (e.g. Interrupt, IO Address, etc). This allows for configuration
ease-of-use, which results in minimal time associated with installation.
The 82595TX’s packaging and power management
features are designed to consume minimal board
real estate and system power. This is required for
applications such as portable PC motherboard designs and PCMCIA cards which require a solution
with very low real estate and power consumption.
The 82595TX package is a 144-lead tQFP (thin
Quad Flat Pack). Its dimensions are 20 mm by
20 mm, and 1.7 mm in height (roughly the same area
as a US Nickel, and the same height as a US Dime).
The 82595TX contains two power down modes; an
SL compatible power down mode which utilizes the
SL SMOUT input, and a POWER DOWN command
for non-SL systems.
1.2 Enhancements to the 82595
The 82595TX is fully backwards compatible to the
82595, both in pinout and software. However, the
82595TX contains several advanced functions from
the 82595 which increase performance and ease of
use. The following is a list of the major enhancements to the 82595TX:
Concurrent Processing Functionality
32-Bit Local Memory IO Port
Integrated Plug N’ Play support
Added EEPROM Interface for Plug N’ Play
Flash addressing up to 1 Mbyte (versus 256K for
82595)
For further information on these enhancements
and a description of all the differences between
the 82595 and 82595TX, please consult the
82595TX User’s Manual, available through your
local sales representative.
1.3 Compliance to Industry Standards
The 82595TX has two interfaces; the host system
interface, which is an ISA or PCMCIA bus interface,
and the serial, or network interface. Both interfaces
have been standardized by the IEEE.
5
82595TX
1.3.1 BUS INTERFACEÐ
ISA IEEE P996/PCMCIA 2.0
The 82595TX implements the full ISA bus interface.
It is compatible with the IEEE spec P996. The
82595TX also interfaces to ISA bus implementations
that deviate from the IEEE spec by requiring early
assertion of the IOCHRDY signal and alternate host
address decode timing. This alternate timing can be
configured in the 82595TX after a software test
which is run at initialization time. The 82595TX can
also be configured for a PCMCIA bus interface depending on the state of the PCMCIA/ISA input pin.
In this case the 82595TX implements the complete
PCMCIA interface, compatible to the PCMCIA revision 2.0 specification.
1.3.2 ETHERNET/TWISTED PAIR ETHERNET
INTERFACEÐIEEE 802.3 SPECIFICATION
The 82595TX’s serial interface provides either an
AUI port interface or a Twisted Pair Ethernet (TPE)
interface. The AUI port can be connected to an
Ethernet Transceiver cable drop, providing a fully
compliant IEEE 802.3 AUI interface. The TPE port
provides a fully compliant IEEE 10BASE-T interface.
The 82595TX can automatically switch to whichever
port (TPE or AUI) is active.
2.0 82595TX PIN DEFINITIONS
2.1 ISA Bus Interface
The ISA bus interface consists of three sections: an Address Bus, a Data Bus, and a Control section.
Symbol
Pin
Type Name and Function
No.
SA0 66 I ADDRESS BUS: These pins provide address decoding for up to 1 Kbyte of
address. These pins also provide 4 Kbytes of IO addressing to support the
SA1 67
Plug N’ Play Standard.
SA2 68
SA3 69
SA4 70
SA5 71
SA6 73
SA7 74
SA8 75
SA9 76
SA10 13
SA11 143
SA14 77 I ADDRESS BUS: These pins provide address decoding between the 16 Kbyte
and 1 Mbyte memory space. This allows for decoding of a Boot EPROM or a
SA15 78
FLASH in 16K increments.
SA16 79
SA17 80
SA18 81
SA19 82
6
82595TX
2.1 ISA Bus Interface (Continued)
Symbol
Pin
Type Name and Function
No.
SD0 46 I/O DATA BUS: This is the data interface between the 82595TX and the host
system. This data is buffered by one (8-bit design) or two (16-bit design)
SD1 47
transceivers. The 82595TX’s data lines should always be connected to
SD2 48
the B side of the data bus transceiver.
SD3 49
SD4 52
SD5 53
SD6 54
SD7 55
SD8 56
SD9 57
SD10 58
SD11 59
SD12 62
SD13 63
SD14 64
SD15 65
AEN 20 I ADDRESS ENABLE: Active high signal indicates a DMA cycle is active.
BALE 21 I BUFFERED ADDRESS LATCH ENABLE: Falling edge used to latch a
valid system address.
SMEMR 14 I MEMORY READ for system memory accesses below 1 Mbyte. Active low.
SMEMW 15 I MEMORY WRITE for system memory accesses below 1 Mbyte. Active
low.
MEMR/16IMEMORY READ for system memory accesses above or below 1 Mbyte.
Active low. This pin also determines if the 82595TX is operating in an 8- or
8/16 Detect
16-bit system. For 16-bit systems, it should always be connected.
MEMW 17 I MEMORY WRITE for system memory accesses above or below 1 Mbyte.
Active low.
IOR 18 I IO READ: Active low.
IOW 19 I IO WRITE: Active low.
IOCS16 40 O IO CHIP SELECT 16: Active low, open drain output which indicates that
an IO cycle access to the 82595TX solution is 16-bit wide. Driven for IO
cycles to the local memory or to the 82595TX.
IOCHRDY 37 O IO CHANNEL READY: Active high, open drain output. When driven low, it
extends host cycles to the 82595TX solution.
SBHE 32 I SYSTEM BUS HIGH ENABLE: Active low input indicates a data transfer
on the high byte (D8–D15) of the system bus (a 16-bit transfer).
INT0 26 O 82595TX INTERRUPT 0–4: One of these five pins is selected to be active
at a time (the other four are in Hi-Z state) by configuration. These active
INT1 27
high outputs serve as interrupts to the host system.
INT2 28
INT3 29
INT4 30
RESET DRV 12 I RESET DRIVE: Active high reset signal.
7
82595TX
2.2 PCMCIA Bus Interface
The PCMCIA bus interface consists of three sections: an Address Bus, a Data Bus, and a Control section.
Symbol
Pin
Type Name and Function
No.
A0 66 I ADDRESS BUS: These pins provide IO address decoding for up to 1 Kbyte.
A1 67
A2 68
A3 69
A4 70
A5 71
A6 73
A7 74
A8 75
A9 76
D0 46 I/O DATA BUS: This is the data interface between the 82595TX and the host
system.
D1 47
D2 48
D3 49
D4 52
D5 53
D6 54
D7 55
D8 56
D9 57
D10 58
D11 59
D12 62
D13 63
D14 64
D15 65
8
82595TX
2.2 PCMCIA Bus Interface (Continued)
Symbol
Pin
Type Name and Function
No.
OE 14 I OUTPUT ENABLE (Memory Read): Active low.
WE 15 I WRITE ENABLE (Memory Write): Active low.
IORD 18 I IO READ: Active low.
IOWR 19 I IO WRITE: Active low.
IOIS16 40 O IO IS 16: Active low output which indicates that an IO cycle access to the
82595TX solution is 16-bit wide. IOIS16
should be asserted prior to Card
Enable or CMD (IORD
or IOWR) assertion.
WAIT 37 O WAIT: Active low output when driven low, extends host cycles to the 82595TX.
IREQ 26 O 82595TX INTERRUPT: Active low output.
RESET 12 I RESET: Active high reset signal.
CE1 81 I Card Enable 1 and Card Enable 2: active low signals driven by the host.
These signals provide a card select based on an address decode (decode
CE2
82
done by the host) and also byte lane enables. When both CE1 and CE2 are
high, no host accesses are made to the card. If CE1
is low (active) and CE2 is
high (inactive), the device operates in byte access mode with valid data being
driven on D0 – D7, and A0 determines the selection of an odd or even byte.
When both CE1 and CE2 are low, a word access is taking place. In this case
A0 is ignored, and the data is transferred on D0–D15. Odd-byte-only accesses
can occur when CE1
is high and CE2 is low. In this case the data is driven on
D8–D15 and A0 is ignored. See Section 4.9 for a summary of the PCMCIA
decode functions.
REG 80 I REG: is an active low input used to determine whether a host access is to
Attribute memory (the 1st 1K of FLASH or CONF Regs) or to Common
memory (FLASH above 1K). If REG is low the access is to Attribute memory, if
REG
is high the access is to Common memory. REG is also asserted low for
all accesses to the 82595TX’s IO Registers (including the access to the local
DRAM via the 82595TX’s Local Memory IO Port). See Section 4.9 for a
summary of the PCMCIA decode functions.
EVENT 32 O EVENT: is an active low output which, when enabled, will be asserted
whenever a frame has been received by the 82595TX. This allows the
82595TX to ‘‘wake up’’ a system which has powered down (with the exception
of powering down the LAN). This output will remain asserted until the
82595TX’s RCV Interrupt (for the frame which woke up the system) has been
acknowledged.
2.3 Local Memory Interface
Symbol
Pin
Type Name and Function
No.
MADDR0 126 O LOCAL MEMORY ADDRESS (MADDR0 – MADDR8): These outputs contain
the multiplexed address for the local DRAM.
MADDR1 127
MADDR2 128
MADDR3 129
MADDR4 130
MADDR5 132
MADDR6 133
MADDR7 134
MADDR8 135
9
82595TX
2.3 Local Memory Interface (Continued)
Symbol
Pin
Type Name and Function
No.
MDATA0 120 I/O LOCAL DATA BUS (MDATA0 – MDATA3): The four I/O signals,
comprising the local data bus, are used to read or write data to
MDATA1 121
or from the 4-bit wide DRAM. These signals also provide the
MDATA2 122
lower 4 bits of data for accesses to an 8-bit FLASH/EPROM or
MDATA3 123
IA PROM if these components are used. A 3.3K pull-up resistor
connects to MDATA3 and enables EEPROM port 2.
RAS 9 O This active low output is the Row Address Strobe signal to the
DRAM.
CAS 6 O This active low output is the Column Address Strobe signal to
the DRAM.
LWE 1 O This active low output is the Write Enable to the DRAM.
FADDR14 126 O FLASH ADDRESS 14– 17 : These pins control the FLASH
addressing from 16K to 1M to allow paging of the FLASH in 16K
FADDR15 127
spaces. These addresses are under direct control of the FLASH
FADDR16 128
PAGING configuration register.
FADDR17 129
NOTE: ISA Bus I/F Only
FADDR18 6
FADDR19 31
FOE 130 O This output provides the active low Output Enable control to
the FLASH.
FWE 1 O This output provides the active low Write Enable control to the
FLASH.
BOOTCS 141 O BOOT EPROM/FLASH CS
IAPROMCS 143 O IA PROM CS
FL/IADATA4 132 I/O Provides the upper 4 bits of an 8 bit data path for both the Boot
EPROM/FLASH and IA PROM, for CPU accesses. A 3.3K pull-
FL/IADATA5 133
down resistor connected to FL/IADATA4 and a 3.3K pull-up
FL/IADATA6 134
resistor connected to FL/IADATA7 enables AUTOFLASH/Boot
FL/IADATA7 135
EPROM detect.
EEPROMCS 139 I/O EEPROM CS: Active high signal. If no EEPROM is connected,
this pin should be connected to V
CC
. In this case it will function
as an input to the 82595TX to indicate no EEPROM is
connected.
EEPROMSK O EEPROM SHIFT CLOCK: This output is used to shift data into
and out of the serial EEPROM.
Port 1 (EEPROM1SK) 120
Port 2 (EEPROM2SK) 105 NOTE: Port 2 must be used for Plug N’ Play
EEPROMDO I EEPROM DATA OUT
Port 1 (EEPROM1DO) 121
Port 2 (EEPROM2DO) 107 NOTE: Port 2 must be used for Plug N’ Play
EEPROMDI O EEPROM DATA IN
Port 1 (EEPROM1DI) 122
Port 2 (EEPROM1DI) 106 NOTE: Port 2 must be used for Plug N’ Play
10
82595TX
2.4 Miscellaneous Control
Symbol
Pin
Type Name and Function
No.
DIRL 42 O DIRECTION LOW: Controls the direction of the low byte data bus
transceiver. The direction defaults to always point in from the ISA bus to
the 82595TX (DIRL
e
1). This direction is turned around (82595TX out to
ISA bus, DIRL
e
0) only in the case of a read access to the 82595TX
based solution.
DIRH 45 O DIRECTION HIGH: Controls the direction of the high byte data bus
transceiver. The direction defaults to always point in from the ISA bus to
the 82595TX (DIRH
e
1). This direction is turned around (82595TX out to
ISA bus, DIRH
e
0) only in the case of a read access to the 82595TX
based solution. This signal is active for 16-bit accesses only.
SMOUT 11 I/O This active LOW signal, when asserted, places the 82595TX into a Power
Down mode. The 82595TX will remain in power down mode until SMOUT
is unasserted. If this line is unconnected to SMOUT from the system bus,
it can be used as an active low output which, when a POWER DOWN
command is issued to the 82595TX, can be used to power down other
external components (this output function is enabled by configuration).
PCMCIA/ISA 22 I This pin, when strapped low, selects an ISA bus interface. Strapped high
selects PCMCIA.
J0 107 I JUMPER: input for selecting between 7 ISA IO spaces (also selects
whether the IO location should be read from the EEPROM). These pins
J1 106 I/O
should be connected to either V
CC
or GND. The 82595TX reads the
J2 105 I/O
Jumper block during its initialization sequence.
J0 J1 J2 IO Address
GND GND GND Address Contained in EEPROM
V
CC
GND GND 2A0h
GND V
CC
GND 280h
V
CC
V
CC
GND 340h
GND GND V
CC
300h
V
CC
GND V
CC
360h
GND V
CC
V
CC
350h
V
CC
V
CC
V
CC
330h
2.5 JTAG Control
Symbol
Pin
Type Name and Function
No.
TDO 97 O JTAG TEST DATA OUT
TMS 98 I JTAG TEST MODE SELECT
TCK 99 I JTAG TEST CLOCK
TDI 100 I JTAG TEST DATA IN
11
82595TX
2.6 Serial Interface
Symbol
Pin
Type Name and Function
No.
TRMT 110 O Positive side of the differential output driver pair that drives 10 Mb/s
Manchester Encoded data on the TRMT pair of the AUI cable (Data Out A).
TRMT 111 O Negative side of the differential output driver pair that drives 10 Mb/s
Manchester Encoded data on the TRMT pair of the AUI cable (Data Out B).
RCV 103 I The positive input to a differential amplifier connected to the RCV pair of the
AUI cable (Data In A). It is driven with 10 Mb/s Manchester Encoded data.
RCV 104 I The negative input to a differential amplifier connected to the RCV pair of the
AUI cable (Data In B). It is driven with 10 Mb/s Manchester Encoded data.
CLSN 112 I The positive input to a differential amplifier connected to the CLSN pair of the
AUI cable (Collision In A).
CLSN 113 I The negative input to a differential amplifier connected to the CLSN pair of the
AUI cable (Collision In B).
TDH 93 O TRANSMIT DATA HIGH: Active high Manchester Encoded data to be
transmitted onto the twisted pair. This signal is used in conjunction with TDL,
TDH
, and TDL to generate the pre-conditioned twisted pair output waveform.
TDL 94 O TRANSMIT DATA LOW: Twisted Pair Output Driver. Active high Manchester
Encoded data with embedded pre-distortion information to be transmitted onto
the twisted pair. This signal is used in conjunction with TDH, TDH, and TDL to
generate the pre-conditioned twisted pair output waveform.
TDH 91 O TRANSMIT DATA HIGH INVERT: Twisted Pair Output Driver. Active low
Manchester Encoded data to be transmitted onto the twisted pair. This signal
is used in conjunction with TDL, TDH, and TDL
to generate the pre-
conditioned twisted pair output waveform.
TDL 92 O TRANSMIT DATA LOW INVERT: Twisted Pair Output Driver. Active low
Manchester Encoded data with embedded pre-distortion information to be
transmitted onto the twisted pair. This signal is used in conjunction with TDL,
TDH, and TDH
to generate the pre-conditioned twisted pair output waveform.
RD 102 I Active high Manchester Encoded data received from the twisted pair.
RD 101 I Active low Manchester Encoded data received from the twisted pair.
X1 115 I 20 MHz CRYSTAL INPUT: This pin can be driven with an external MOS level
clock when X2 is left floating. This input provides the timing for all of the
82595TX functional blocks.
X2 116 O 20 MHz CRYSTAL OUTPUT: If X1 is driven with an external MOS level clock,
X2 should be left floating.
12
82595TX
2.6 Serial Interface (Continued)
Symbol
Pin
Type Name and Function
No.
AUI LED/BNC DIS 83 O AUI LED INDICATOR: This output, when the 82595TX is used for
as a TPE/AUI solution, will turn on an LED when the 82595TX is
actively interfaced to its AUI serial port. When the 82595TX is used
as a BNC/AUI solution, this output becomes the BNC DIS output,
which can be used to power down the BNC Transceiver section (the
Transceiver and the DC to DC Converter) of the solution when the
BNC port is unconnected.
LILED 86 O LINK INTEGRITY LED: Normally on (low) ouput which indicates a
good link integrity status when the 82595TX is connected to an
active TPE port. This output will remain on when the Link Integrity
function has been disabled. It turns off (driven high) when Link
Integrity fails, or when the 82595TX is actively interfaced to an AUI
port. The minimum off time is 100 ms.
ACTLED 85 O LINK ACTIVITY LED: Normally off (high) output turns on to indicate
activity for transmission, reception, or collision. Flashes at a rate
dependent on the level of activity on the link.
POLED 84 O POLARITY LED: If the 82595TX detects that the receive TPE wires
are reversed, POLED will turn on (low) to indicate the fault. POLED
remains on even if automatic polarity correction is enabled, and the
82595TX has automatically corrected for the reversed wires.
2.7 Power and Ground
Symbol
Pin
Type Name and Function
No.
V
CC
3, 4, I POWER:a5Vg5%.
8, 23,
25, 35,
38, 41,
44, 51,
61, 87,
89, 95,
109, 117,
119, 125,
136, 142
V
SS
2, 5, 7, I GROUND: 0V.
10, 24, 33,
34, 36, 39,
43, 50 60,
72, 88, 90,
96, 108,
114, 118,
124, 131,
138, 140,
144
13
82595TX
2.8 82595TX Pin Summary
ISA/PCMCIA Bus Interface
ISA
MUXed
Pin P-Down
Pin Name
PCMCIA
Type State
Pin Name
SA0–SA11 (In) A0–A9 (In) Inactive
SA14–16 (In) Inactive
SA17 (In) REG
(In) Inactive/Act
(1)
SA18 (In) CE1 (In) Inactive/Act
(1)
SA19 (In) CE2 (In) Inactive
SD0–SD15 (I/O) D0– D15 (I/O) TS TS
SMEMR
(In) OE (In) Inactive
SMEMW
(In) WE (In) Inactive
IOR
(In) IORD (In) Inactive
IOW
(In) IOWR (In) Inactive/Act
(1)
INT0 (Out) IREQ (Out) TS TS
INT1–4 (Out) TS TS
RESET DRV (In) RESET (In) Act
IOCS16
(Out) IOIS16 (Out) OD/TS TS
BALE (In) Inactive
IOCHRDY (Out) WAIT
(Out) OD/2S TS
SBHE
(In) EVENT (Out) 2S Inactive/TS
AEN (In) Inactive/Act
(1)
MEMR (In) Inactive
MEMW
(In) Inactive
NOTE:
1. For hardware powerdown using SMOUT
, these pins will
be inactive. For software powerdown, these pins remain
active.
Local Memory Interface
Pin Name
MUXed Pin P-Down
Pin Name Type State
MADDR0–3 (Out) FADDR14–17 (Out) 2S TS
MADDR4 (Out) FOE
(Out) 2S TS
MADDR5–8 (Out) FL/IADATA4–7 (In) TS TS
MDATA0 (I/O) EEPROM1SK(Out) TS TS
MDATA1 (I/O) EEPROM1DO(In) TS TS
MDATA2 (I/O) EEPROM1DI(Out) TS TS
MDATA3 (I/O) TS TS
WE
(Out) FWE (Out) 2S TS
RAS
(Out) 2S PU
CAS
(Out) FADDR18 (Out) 2S PU
BOOTCS
(Out) 2S PU
IAPROMCS
(Out) SA11 (In) (Dual) 2S PU
EEPROMCS (I/O) TS PD
FADDR19 (Out) TS TS
Miscellaneous Control
MUXed
Pin P-Down Dual
Pin Name Pin
Type State Pin Name
Name
DIRL (Out) 2S PU
DIRH
(Out) 2S PU
J0(In) ACT EEPROM2D0
(In)
J1 (I/O) TS TS EEPROM2DI
(Out)
J2 (I/O) TS TS EEPROM2SK
(Out)
SMOUT
(I/O) TS ACT/TS
PCMCIA/ISA
(In) ACT
JTAG Control
Pin Name
MUXed Pin P-Down
Pin Name Type State
TMS (In) In Act
TCK (In) In Act
TDI (In) In Act
TDO (Out) 2S
Serial Interface
Pin Name
MUXed Pin P-Down
Pin Name Type State
TRMT (Out) Ana TS
TRMT
(Out) Ana TS
RCV (In) Ana In Act
RCV
(In) Ana In Act
CLSN (In) Ana In Act
CLSN (In) Ana In Act
TDH (Out) Ana TS
TDL (Out) Ana TS
TDH
(Out) Ana TS
TDL
(Out) Ana TS
RD (In) Ana In Act
RD
(In) Ana In Act
X1 (In) In Act
X2 (Out) 2S TS
LILED (Out) 2S TS
POLED (Out) 2S TS
ACTLED (Out) 2S TS
AUILED (Out) BNC DIS (Out) 2S TS
Legend:
TSÐTriState.
ODÐOpen Drain.
2SÐTwo State, will be found in eithera1or0logic level.
AnaÐAnalog pin (all serial interface signals).
ActÐInput buffer is active during Power Down.
In ActÐInput buffer is inactive during Power Down.
PUÐOutput in inactive state with weak internal Pull-up during Power Down.
PDÐOutput in inactive state with weak internal Pull-down during Power Down.
DualÐDual function pin.
14
82595TX
3.0 82595TX INTERNAL
ARCHITECTURE OVERVIEW
Figure 1 shows a high level block diagram of the
82595TX. The 82595TX is divided into four main
subsections; a system interface, a local memory
sub-system interface, a CSMA/CD unit, and a serial
interface.
3.1 System Interface Overview
The 82595TX’s system interface subsection includes a glueless ISA or PCMCIA bus interface (selectable by strapping), and the 82595TX’s IO registers (including the 82595TX’s command, status, and
Data In/Out registers). The system interface block
also interfaces with the 82595TX’s local memory interface subsystem and CSMA/CD subsystem.
The bus interface logic provides the control, address, and data interface to either an ISA compatible
or PCMCIA revision 2.0 bus. The 82595TX decodes
up to 1M of total memory address space. Address
decoding within 16K block increments (A14–A19)
are used for Flash or Boot EPROM. IO accesses are
decoded throughout the 1 Kbyte PC IO address
range (A10 and A11 provide up to 4K of IO addressing and are used for Plug N’ Play). The 82595TX
data bus interface provides either an 8- or 16-bit interface to the host system’s data bus. The control
interface provides complete handshaking interface
with the system bus to enable transfer of data between the 82595TX solution and the host system.
This logic also controls the direction of the Data Bus
transceivers.
The 82595TX’s IO registers provide 3 banks of directly addressable registers which are used as the
control and data interface to the 82595TX. There
are 16 IO registers per bank, with only one bank
enabled at a time. This allows the complete
82595TX software interface to be contained in one
16-byte IO space. The base address of this IO space
is selectable via either software (which can be
stored in a serial EEPROM interfaced to either of
two ports in the 82595TX), or by strapping the
82595TX IO Jumper block (J0 –J2). The 82595TX
can also detect conflicts to its base IO space, and
automatically resolve these conflicts either by allowing the selection of one Plug N’ Play card from multiple cards (using Plug N’ Play software), or by mapping itself into an un-used IO space (Automatic IO
Resolution). Included in the 82595TX IO registers
are the Command Register, the Status Register, and
the Local Memory IO Port register, which provides
the data interface to the local DRAM buffer contained in an 82595TX solution. Functions such as IO
window mapping, Interrupt enable, RCV and XMT
buffer initialization, etc. are also configured and controlled through the IO registers.
3.1.1 CONCURRENT PROCESSING
FUNCTIONALITY
The 82595TX’s Concurrent Processing feature significantly enchances data throughput performance
by performing both system bus and serial link activities concurrently. Transmission of a frame is started
by the 82595TX before that frame is completely copied into local memory. During reception, a frame is
processed by the host CPU before that frame is entirely copied to local memory. Transmit Concurrent
Processing feature is enabled by writing to BANK 2,
Register 1, Bit 0. A 1 written to this bit enables this
functionality, a 0 (default) disables it. To enable Receive Concurrent Processing, BANK 1, Register 7
must be programmed to value other than 00h (00h
disables RCV Concurrent Processing, and is default). (See Section 4.1 for the format of IO BANK 1
and 2.) Concurrent Processing is not recommended
for 8-bit interfaces. For more information on Transmit and Receive Concurrent Processing, refer to
Section 7.0 and Section 8.0.
3.2 Local Memory Interface
The 82595TX’s local memory interface includes a
DMA unit which controls data transfers to or from
the 82595TX’s local DRAM, control for access to an
IA PROM and a Boot EPROM/FLASH, and two interfaces to a serial EE PROM. The local memory interface subsection also arbitrates accesses to the
local memory by the host CPU and the 82595TX.
Data transfers between the 82595TX and the local
DRAM are always through the 82595TX’s Local
Memory 16-bit/32-bit IO Port. This allows the entire
DRAM memory (up to 64 Kbytes) to be mapped into
one IO location in the host systems IO map. By
setting a configuration bit in the 82595TX’s IO
Registers (32IO/HAR
Ý
), the local memory can be
extended from 16 bits to a full 32 bits. During 32-bit
accesses, the CPU would perform a doubleword access addressed to register 12 of BANK0. The ISA
bus will break this access up into two 16-bit accesses to Registers 12/13 followed by Registers 14/15,
(or 4 sequential 8-bit accesses in an 8-bit interface).
The CPU always accesses the 82595TX IO Port for
Receive or Transmit data transfers, while the
82595TX automatically increments the address to
the DRAM after each CPU access. The DRAMs data
path is a 4-bit interface (typically 64K by 4-bits wide,
or 256K by 4-bits wide) to allow for the lowest possible solution cost. The 82595TX implements a prefetch mechanism to the local DRAM so that the data
is always available to the CPU as either an 8- or 16bit word. In the case of the CPU reading from the
DRAM, the 82595 TX reads the next four 4-bit nibbles from the DRAM, the 82595TX between CPU
cycles so that the data is always available as a word
in the 82595TX’s Local Memory IO Port register. In
the case of the CPU writing to the DRAM, the data is
15
82595TX
written into the 82595TX’s Local Memory IO Port
then transferred to the DRAM by the 82595TX between CPU cycles. This prefetch mechanism of the
82595TX allows for IO read and writes to the local
memory to be performed with no additional waitstates (3 clocks per data transfer cycle).
The DMA unit provides addressing and control to
move RCV or XMT data between the 82595TX and
the local DRAM. For transmission, the CPU is required only to copy the data to the local memory,
initialize the 82595TX’s DMA Current Address Register (CAR) to point to the beginning of the frame,
and issue a Transmit Command to the 82595TX.
The DMA unit facilitates the transfers from the local
memory to the 82595TX as transmission takes
place. The DMA unit will reset upon collision during
a transmission, enabling automatic re-transmission
of the transmit frame. During reception, the DMA
unit implements a recyclable ring buffer structure
which can receive continuous back to back frames
without CPU intervention on a per frame basis (see
Section 8.2 for details).
The 82595TX provides address decoding and control to allow access to an external Boot EPROM/
FLASH or an IA PROM if these components are utilized in an 82595TX design (an IA PROM cannot be
used for Plug N’ Play). The 82595TX also provides
two complete interfaces to a serial EEPROM (Port1
or Port2) to replace jumper blocks used to contain
configuration information. Port1 is used to store configuration information such as IO Mapping Window,
Interrupt line selection, etc., and is backwards pin
compatible to the 82595TX EEPROM interface.
Port2 is used to store configuration information as in
Port1; in addition, it is used to store Plug N’ Play
information as defined in the Plug N’ Play Specification.
The 82595TX arbitrates accesses to the local memory sub-system by the CPU and the 82595TX. The
arbitration unit will hold off an 82595TX DMA cycle
to the local memory if a CPU cycle is already in progress. Likewise, it will hold off the CPU if an 82595TX
cycle is already in progress. The cycle which is held
off will be completed on termination of the preceding
cycle.
3.3 CSMA/CD Unit
The CSMA/CD unit implements the IEEE 802.3
CSMA/CD protocol. It performs such functions as
transmission deferral to link traffic, interframe spacing, exponential backoff for collision handling, address recognition, etc. The CSMA/CD unit serves as
the interface between the local memory and the serial interface. It serializes data transferred from the
local memory before it is passed to the serial interface unit for transmission. During frame reception, it
converts the serial data received from the serial interface to a byte format before it is transferred to
local memory. The CSMA/CD unit strips framing parameters such as the Preamble and SFD fields before the frame is passes to memory for reception.
For transmission, the CSMA/CD unit builds the
frame format before the frame is passed to the serial
interface for transmission.
3.4 Serial Interface
The 82595TX’s serial interface provides either an
AUI port interface or a Twisted Pair Ethernet (TPE)
interface. The AUI port can be connected to an
Ethernet Transceiver cable drop to provide a fully
compliant IEEE 802.3 AUI interface. The AUI port
can also interface to a transceiver device to
provide a fully compliant IEEE 802.3 10BASE2
(Cheapernet) interface. The TPE port provides a fully compliant 10BASE-T interface. The 82595TX automatically enables either to the AUI or TPE interface depending on which medium is connected to
the chip. Software configuration can override this
automatic selection.
4.0 ACCESSING THE 82595TX
All access to the 82595TX is made through one of
three banks of IO registers. Each bank contains 16
registers. Each register in a bank is directly accessible via addressing. Through the use of bank switching, the 82595TX utilizes only 16 IO locations in the
host system’s IO map to access each of its registers. The different banks are accessed by setting the
POINTER field in the 82595TX Command Register
to select each bank. The Command Register is Register for each bank.
4.1 82595TX Register Map
The 82595TX registers are contained in three banks
of 16 IO registers per bank. These three banks are
shown in the following three pages.
16
82595TX
4.1.1 IO BANK 0
The format for IO Bank 0 is shown below.
76543210
Reg 0
POINTER ABORT COMMAND OP CODE (CMD
Reg)
RCV EXEC EXEC TX RX RX STP
States States INT INT INT INT Reg 1
ID REGISTER 0 0
(Counter) 1 (Auto En) 0 1 RESERVED Reg 2
0 0 Cur/ 32 IO/ EXEC TX RX RX STP
Resvrd Resvrd Base
HAR Mask Mask Mask Mask Reg 3
RCV CAR/BAR
(Low) Reg 4
RCV CAR/BAR
(High) Reg 5
RCV STOP REG
(Low) Reg 6
RCV STOP REG
(High) Reg 7
RCV Copy Threshold REG
Reg 8
00000000
(Reserved) Reg 9
XMT CAR/BAR
(Low) Reg 10
XMT CAR/BAR
(High) Reg 11
Host Address Reg/32-Bit I/O (Byte 0)
(Low) Reg 12
Host Address Reg/32-Bit I/O (Byte 1)
(High) Reg 13
Local Memory/32-Bit I/O (Byte 2)
IO Port (Low) Reg 14
Local Memory/32-Bit I/O (Byte 3)
IO Port (High) Reg 15
17
82595TX
4.1.2 IO BANK 1
The format for IO Bank 1 is shown below.
76543210
Reg 0
POINTER ABORT COMMAND OP CODE (CMD
Reg)
Tri-ST Alt0000Host 0
INT RDY Tm Resvrd Resvrd Resvrd Resvrd Bus Wd Resvrd Reg 1
FL/BT Boot EPROM/FLASH 0
INT Select
Detect Decode Window Resvrd Reg 2
0 0 I/O Mapping
Window Reg 3
00000000
(Reserved) Reg 4
00000000
(Reserved) Reg 5
00000000
(Reserved) Reg 6
RCV BOF Threshold REG
Reg 7
RCV LOWER LIMIT REG
(High Byte) Reg 8
RCV UPPER LIMIT REG
(High Byte) Reg 9
XMT LOWER LIMIT REG
(High Byte) Reg 10
XMT UPPER LIMIT REG
(High Byte) Reg 11
FLASH PAGE FLASH WRITE FLASH PAGE
SELECT HIGH ENABLE SELECT Reg 12
00000SMOUT AL RDY AL RDY
OUT EN TEST PAS/FL Reg 13
00000000
(Reserved) Reg 14
00000000
(Reserved) Reg 15
18
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