Intel Corporation QA80188 Datasheet

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November 1994

COPYRIGHT

©

INTEL CORPORATION, 1995

Order Number: 272430-002

80186/80188

HIGH-INTEGRATION 16-BIT MICROPROCESSORS

Y

Integrated Feature Set
Ð Enhanced 8086-2 CPU
Ð Clock Generator
Ð 2 Independent DMA Channels
Ð Programmable Interrupt Controller
Ð 3 Programmable 16-bit Timers
Ð Programmable Memory and

Peripheral Chip-Select Logic
Ð Programmable Wait State Generator
Ð Local Bus Controller

Y

Available in 10 MHz and 8 MHz
Versions

Y

High-Performance Processor
Ð 4 Mbyte/Sec Bus Bandwidth

Interface

@

8 MHz (80186)

Ð 5 Mbyte/Sec Bus Bandwidth

Interface

@

10 MHz (80186)

Y

Direct Addressing Capability to 1 Mbyte
of Memory and 64 Kbyte I/O

Y

Completely Object Code Compatible
with All Existing 8086, 8088 Software
Ð 10 New Instruction Types

Y

Numerics Coprocessing Capability
Through 8087 Interface

Y

Available in 68 Pin:
Ð Plastic Leaded Chip Carrier (PLCC)
Ð Ceramic Pin Grid Array (PGA)
Ð Ceramic Leadless Chip Carrier (LCC)

Y

Available in EXPRESS
Ð Standard Temperature with Burn-In
Ð Extended Temperature Range

(

b

40§Ctoa85§C)

272430– 1

Figure 1. Block Diagram

1

80186/80188 High-Integration 16-Bit Microprocessors

CONTENTS PAGE

FUNCTIONAL DESCRIPTION

ААААААААААААА 9

Introduction АААААААААААААААААААААААААААААААА 9

CLOCK GENERATOR ААААААААААААААААААААА 9

Oscillator АААААААААААААААААААААААААААААААААА 9
Clock Generator ААААААААААААААААААААААААААА 9
READY Synchronization АААААААААААААААААААА 9
RESET Logic ААААААААААААААААААААААААААААААА 9

LOCAL BUS CONTROLLER ААААААААААААААА 9

Memory/Peripheral Control ААААААААААААААА 10
Local Bus Arbitration АААААААААААААААААААААА 10
Local Bus Controller and Reset АААААААААААА 10

PERIPHERAL ARCHITECTURE АААААААААА 10

Chip-Select/Ready Generation Logic АААААА 10
DMA Channels АААААААААААААААААААААААААААА 11
Timers АААААААААААААААААААААААААААААААААААА 11
Interrupt Controller АААААААААААААААААААААААА 12

CONTENTS PAGE

ABSOLUTE MAXIMUM RATINGS

АААААААА 15

D.C. CHARACTERISTICS АААААААААААААААА 15

A.C. CHARACTERISTICS АААААААААААААААА 16

EXPLANATION OF THE AC

SYMBOLS

АААААААААААААААААААААААААААААА 18

WAVEFORMS АААААААААААААААААААААААААААА 19

EXPRESS АААААААААААААААААААААААААААААААА 25

EXECUTION TIMINGS ААААААААААААААААААА 26

INSTRUCTION SET SUMMARY АААААААААА 27

FOOTNOTES ААААААААААААААААААААААААААААА 32

REVISION HISTORY ААААААААААААААААААААА 33

2

2

80186/80188

Contacts Facing Up

Contacts Facing Down

272430– 2

Figure 2. Ceramic Leadless Chip Carrier (JEDEC Type A)

Pins Facing Up Pins Facing Down

272430– 3

Figure 3. Ceramic Pin Grid Array

NOTE:

Pin names in parentheses apply to the 80188.

3

3

80186/80188

Leads Facing Up Leads Facing Down

272430– 4

Figure 4. Plastic Leaded Chip Carrier

NOTE:

Pin names in parentheses apply to the 80188.

4

4

80186/80188

Table 1. Pin Descriptions

Symbol

Pin

Type Name and Function

No.

V

CC

9ISYSTEM POWER:a5 volt power supply.

43

V

SS

26 I System Ground.
60

RESET 57 O Reset Output indicates that the CPU is being reset, and can be used as a system

reset. It is active HIGH, synchronized with the processor clock, and lasts an
integer number of clock periods corresponding to the length of the RES

signal.

X1 59 I Crystal Inputs X1 and X2 provide external connections for a fundamental mode

parallel resonant crystal for the internal oscillator. Instead of using a crystal, an

X2 58 O

external clock may be applied to X1 while minimizing stray capacitance on X2.
The input or oscillator frequency is internally divided by two to generate the
clock signal (CLKOUT).

CLKOUT 56 O Clock Output provides the system with a 50% duty cycle waveform. All device

pin timings are specified relative to CLKOUT.

RES 24 I An active RES causes the processor to immediately terminate its present

activity, clear the internal logic, and enter a dormant state. This signal may be
asynchronous to the processor clock. The processor begins fetching
instructions approximately 6(/2 clock cycles after RES

is returned HIGH. For
proper initialization, VCCmust be within specifications and the clock signal must
be stable for more than 4 clocks with RES

held LOW. RES is internally
synchronized. This input is provided with a Schmitt-trigger to facilitate power-on
RES

generation via an RC network.

TEST 47 I/O TEST is examined by the WAIT instruction. If the TEST input is HIGH when

‘‘WAIT’’ execution begins, instruction execution will suspend. TEST

will be
resampled until it goes LOW, at which time execution will resume. If interrupts
are enabled while the processor is waiting for TEST, interrupts will be serviced.
During power-up, active RES

is required to configure TEST as an input. This pin

is synchronized internally.

TMR IN 0 20 I Timer Inputs are used either as clock or control signals, depending upon the

programmed timer mode. These inputs are active HIGH (or LOW-to-HIGH

TMR IN 1 21 I

transitions are counted) and internally synchronized.

TMR OUT 0 22 O Timer outputs are used to provide single pulse or continous waveform

generation, depending upon the timer mode selected.

TMR OUT 1 23 O

DRQ0 18 I DMA Request is asserted HIGH by an external device when it is ready for DMA

Channel 0 or 1 to perform a transfer. These signals are level-triggered and

DRQ1 19 I

internally synchronized.

NMI 46 I The Non-Maskable Interrupt input causes a Type 2 interrupt. An NMI transition

from LOW to HIGH is latched and synchronized internally, and initiates the
interrupt at the next instruction boundary. NMI must be asserted for at least one
clock. The Non-Maskable Interrupt cannot be avoided by programming.

INT0 45 I Maskable Interrupt Requests can be requested by activating one of these pins.

When configured as inputs, these pins are active HIGH. Interrupt Requests are

INT1/SELECT

44 I

synchronized internally. INT2 and INT3 may be configured to provide active-

INT2/INTA0

42 I/O

LOW interrupt-acknowledge output signals. All interrupt inputs may be

INT3/INTA1

/IRQ 41 I/O

configured to be either edge- or level-triggered. To ensure recognition, all
interrupt requests must remain active until the interrupt is acknowledged. When
Slave Mode is selected, the function of these pins changes (see Interrupt
Controller section of this data sheet).

NOTE:

Pin names in parentheses apply to the 80188.

5

5

80186/80188

Table 1. Pin Descriptions (Continued)

Symbol

Pin

Type Name and Function

No.

A19/S6 65 O Address Bus Outputs (16–19) and Bus Cycle Status (3–6) indicate the four most

significant address bits during T

1

. These signals are active HIGH. During T2,T3,TW,

A18/S5 66 O

and T

4

, the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a

A17/S4 67 O

DMA-initiated bus cycle. During the same T-states, S3, S4, and S5 are always LOW.

A16/S3 68 O

The status pins float during bus HOLD or RESET.

AD15 (A15) 1 I/O Address/Data Bus signals constitute the time multiplexed memory or I/O address (T1)

and data (T

2,T3,TW

, and T4) bus. The bus is active HIGH. A0is analogous to BHE for

AD14 (A14) 3 I/O

the lower byte of the data bus, pins D

7

through D0. It is LOW during T1when a byte is

AD13 (A13) 5 I/O

to be transferred onto the lower portion of the bus in memory or I/O operations. BHE

AD12 (A12) 7 I/O

does not exist on the 80188, as the data bus is only 8 bits wide.

AD11 (A11) 10 I/O
AD10 (A10) 12 I/O
AD9 (A9) 14 I/O
AD8 (A8) 16 I/O
AD7 2 I/O
AD6 4 I/O
AD5 6 I/O
AD4 8 I/O
AD3 11 I/O
AD2 13 I/O
AD1 15 I/O
AD0 17 I/O

BHE/S7 64 O During T1the Bus High Enable signal should be used to determine if data is to be

enabled onto the most significant half of the data bus; pins D

15–D8

. BHE is LOW

(S7)

during T

1

for read, write, and interrupt acknowledge cycles when a byte is to be

transferred on the higher half of the bus. The S

7

status information is available during

T

2,T3

, and T4.S7is logically equivalent to BHE. BHE/S7 floats during HOLD. On the

80188, S7 is high during normal operation.

BHE

and A0 Encodings (80186 Only)

BHE A0

Function

Value Value

0 0 Word Transfer
0 1 Byte Transfer on upper half of data bus (D15 –D8)
1 0 Byte Transfer on lower half of data bus (D

7–D0

)

1 1 Reserved

ALE/QS0 61 O Address Latch Enable/Queue Status 0 is provided by the processor to latch the

address. ALE is active HIGH. Addresses are guaranteed to be valid on the trailing
edge of ALE. The ALE rising edge is generated off the rising edge of the CLKOUT
immediately preceding T

1

of the associated bus cycle, effectively one-half clock cycle
earlier than in the 8086. The trailing edge is generated off the CLKOUT rising edge in
T

1

as in the 8086. Note that ALE is never floated.

WR/QS1 63 O Write Strobe/Queue Status 1 indicates that the data on the bus is to be written into a

memory or an I/O device. WR is active for T2,T3, and TWof any write cycle. It is active
LOW, and floats during HOLD. When the processor is in queue status mode, the ALE/
QS0 and WR

/QS1 pins provide information about processor/instruction queue

interaction.

QS1 QS0 Queue Operation

0 0 No queue operation
0 1 First opcode byte fetched from the queue
1 1 Subsequent byte fetched from the queue
1 0 Empty the queue

NOTE:

Pin names in parentheses apply to the 80188.

6

6

80186/80188

Table 1. Pin Descriptions (Continued)

Symbol

Pin

Type Name and Function

No.

RD/QSMD 62 I/O Read Strobe is an active LOW signal which indicates that the processor is

performing a memory or I/O read cycle. It is guaranteed not to go LOW
before the A/D bus is floated. An internal pull-up ensures that RD

is HIGH
during RESET. Following RESET the pin is sampled to determine whether
the processor is to provide ALE, RD

, and WR, or queue status information.
To enable Queue Status Mode, RD must be connected to GND. RD will
float during bus HOLD.

ARDY 55 I Asynchronous Ready informs the processor that the addressed memory

space or I/O device will complete a data transfer. The ARDY pin accepts a
rising edge that is asynchronous to CLKOUT, and is active HIGH. The
falling edge of ARDY must be synchronized to the processor clock.
Connecting ARDY HIGH will always assert the ready condition to the CPU.
If this line is unused, it should be tied LOW to yield control to the SRDY pin.

SRDY 49 I Synchronous Ready informs the processor that the addressed memory

space or I/O device will complete a data transfer. The SRDY pin accepts an
active-HIGH input synchronized to CLKOUT. The use of SRDY allows a
relaxed system timing over ARDY. This is accomplished by elimination of
the one-half clock cycle required to internally synchronize the ARDY input
signal. Connecting SRDY high will always assert the ready condition to the
CPU. If this line is unused, it should be tied LOW to yield control to the
ARDY pin.

LOCK 48 O LOCK output indicates that other system bus masters are not to gain

control of the system bus while LOCK

is active LOW. The LOCK signal is
requested by the LOCK prefix instruction and is activated at the beginning
of the first data cycle associated with the instruction following the LOCK
prefix. It remains active until the completion of that instruction. No
instruction prefetching will occur while LOCK is asserted. When executing
more than one LOCK instruction, always make sure there are 6 bytes of
code between the end of the first LOCK instruction and the start of the
second LOCK instruction. LOCK

is driven HIGH for one clock during RESET

and then floated.

S0 52 O Bus cycle status S0 –S2

are encoded to provide bus-transaction

information:

S1

53 O

S2 54 O

Bus Cycle Status Information

S2 S1 S0 Bus Cycle Initiated

0 0 0 Interrupt Acknowledge
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 Halt
1 0 0 Instruction Fetch
1 0 1 Read Data from Memory
1 1 0 Write Data to Memory
1 1 1 Passive (no bus cycle)

The status pins float during HOLD.
S2

may be used as a logical M/IO indicator, and S1 as a DT/R indicator.

NOTE:

Pin names in parentheses apply to the 80188.

7

7

80186/80188

Table 1. Pin Descriptions (Continued)

Symbol

Pin

Type Name and Function

No.

HOLD 50 I HOLD indicates that another bus master is requesting the local bus. The

HOLD input is active HIGH. HOLD may be asynchronous with respect to the

HLDA 51 O

processor clock. The processor will issue a HLDA (HIGH) in response to a
HOLD request at the end of T

4

or Ti. Simultaneous with the issuance of
HLDA, the processor will float the local bus and control lines. After HOLD is
detected as being LOW, the processor will lower HLDA. When the processor
needs to run another bus cycle, it will again drive the local bus and control
lines.

UCS 34 O Upper Memory Chip Select is an active LOW output whenever a memory

reference is made to the defined upper portion (1K – 256K block) of memory.
This line is not floated during bus HOLD. The address range activating UCS

is

software programmable.

LCS 33 O Lower Memory Chip Select is active LOW whenever a memory reference is

made to the defined lower portion (1K – 256K) of memory. This line is not
floated during bus HOLD. The address range activating LCS

is software

programmable.

MCS0 38 O Mid-Range Memory Chip Select signals are active LOW when a memory

reference is made to the defined mid-range portion of memory (8K – 512K).

MCS1

37 O

These lines are not floated during bus HOLD. The address ranges activating

MCS2

36 O

MCS0–3 are software programmable.

MCS3

35 O

PCS0 25 O Peripheral Chip Select signals 0 – 4 are active LOW when a reference is made

to the defined peripheral area (64 Kbyte I/O space). These lines are not

PCS1

27 O

floated during bus HOLD. The address ranges activating PCS0 – 4 are

PCS2

28 O

software programmable.

PCS3

29 O

PCS4

30 O

PCS5/A1 31 O Peripheral Chip Select 5 or Latched A1 may be programmed to provide a

sixth peripheral chip select, or to provide an internally latched A1 signal. The
address range activating PCS5

is software-programmable. PCS5/A1 does
not float during bus HOLD. When programmed to provide latched A1, this pin
will retain the previously latched value during HOLD.

PCS6/A2 32 O Peripheral Chip Select 6 or Latched A2 may be programmed to provide a

seventh peripheral chip select, or to provide an internally latched A2 signal.
The address range activating PCS6 is software programmable. PCS6/A2
does not float during bus HOLD. When programmed to provide latched A2,
this pin will retain the previously latched value during HOLD.

DT/R 40 O Data Transmit/Receive controls the direction of data flow through an

external data bus transceiver. When LOW, data is transferred to the
processsor. When HIGH, the processor places write data on the data bus.

DEN 39 O Data Enable is provided as a data bus transceiver output enable. DEN is

active LOW during each memory and I/O access. DEN is HIGH whenever
DT/R

changes state. During RESET, DEN is driven HIGH for one clock, then

floated. DEN

also floats during HOLD.

NOTE:

Pin names in parentheses apply to the 80188.

8

8

80186/80188

FUNCTIONAL DESCRIPTION

Introduction

The following Functional Description describes the
base architecture of the 80186. The 80186 is a very
high integration 16-bit microprocessor. It combines
15–20 of the most common microprocessor system
components onto one chip while providing twice the
performance of the standard 8086. The 80186 is ob­ject code compatible with the 8086/8088 microproc­essors and adds 10 new instruction types to the
8086/8088 instruction set.

For more detailed information on the architecture,
please refer to the 80C186XL/80C188XL User’s
Manual. The 80186 and the 80186XL devices are
functionally and register compatible.

CLOCK GENERATOR

The processor provides an on-chip clock generator
for both internal and external clock generation. The
clock generator features a crystal oscillator, a divide­by-two counter, synchronous and asynchronous
ready inputs, and reset circuitry.

Oscillator

The oscillator circuit is designed to be used with a
parallel resonant fundamental mode crystal. This is
used as the time base for the processor. The crystal
frequency selected will be double the CPU clock fre­quency. Use of an LC or RC circuit is not recom­mended with this oscillator. If an external oscillator is
used, it can be connected directly to the input pin X1
in lieu of a crystal. The output of the oscillator is not
directly available outside the processor. The recom­mended crystal configuration is shown in Figure 5.

x

80186-10 (10 MHz) 20

272430– 5

80186 (8 MHz) 16

Figure 5. Recommended

Crystal Configuration

Intel recommends the following values for crystal se­lection parameters:

Temperature Range: 0 to 70

§

C
ESR (Equivalent Series Resistance): 30X max
C

0

(Shunt Capacitance of Crystal): 7.0 pf max

C

1

(Load Capacitance): 20 pfg2pf

Drive Level: 1 mW max

Clock Generator

The clock generator provides the 50% duty cycle
processor clock for the processor. It does this by
dividing the oscillator output by 2 forming the sym­metrical clock. If an external oscillator is used, the
state of the clock generator will change on the fall­ing edge of the oscillator signal. The CLKOUT pin
provides the processor clock signal for use outside
the device. This may be used to drive other system
components. All timings are referenced to the output
clock.

READY Synchronization

The processor provides both synchronous and asyn­chronous ready inputs. In addition, the processor, as
part of the integrated chip-select logic, has the capa­bility to program WAIT states for memory and
peripheral blocks.

RESET Logic

The processor provides both a RES input pin and a
synchronized RESET output pin for use with other
system components. The RES

input pin is provided
with hysteresis in order to facilitate power-on Reset
generation via an RC network. RESET output is
guaranteed to remain active for at least five clocks
given a RES input of at least six clocks.

LOCAL BUS CONTROLLER

The processor provides a local bus controller to
generate the local bus control signals. In addition, it
employs a HOLD/HLDA protocol for relinquishing
the local bus to other bus masters. It also provides
outputs that can be used to enable external buffers
and to direct the flow of data on and off the local
bus.

9

9

80186/80188

Memory/Peripheral Control

The processor provides ALE, RD, and WR bus con­trol signals. The RD

and WR signals are used to
strobe data from memory or I/O to the processor or
to strobe data from the processor to memory or I/O.
The ALE line provides a strobe to latch the address
when it is valid. The local bus controller does not
provide a memory/I/O

signal. If this is required, use

the S2

signal (which will require external latching),
make the memory and I/O spaces nonoverlapping,
or use only the integrated chip-select circuitry.

Local Bus Arbitration

The processor uses a HOLD/HLDA system of local
bus exchange. This provides an asynchronous bus
exchange mechanism. This means multiple masters
utilizing the same bus can operate at separate clock
frequencies. The processor provides a single
HOLD/HLDA pair through which all other bus mas­ters may gain control of the local bus. External cir­cuitry must arbitrate which external device will gain
control of the bus when there is more than one alter­nate local bus master. When the processor relin­quishes control of the local bus, it floats DEN

,RD,

WR

,S0–S2, LOCK, AD0– AD15 (AD0–AD7),

A16–A19 (A8 – A19), BHE

(S7), and DT/R to allow

another master to drive these lines directly.

Local Bus Controller and Reset

During RESET the local bus controller will perform
the following action:

#

Drive DEN,RD, and WR HIGH for one clock cy­cle, then float.

NOTE:

RD

is also provided with an internal pull-up de­vice to prevent the processor from inadvertently
entering Queue Status Mode during RESET.

#

Drive S0–S2 to the inactive state (all HIGH) and
then float.

#

Drive LOCK HIGH and then float.

#

Float AD0 – 15 (AD0 – AD7), A16 – 19 (A8–A19),
BHE

(S7), DT/R.

#

Drive ALE LOW (ALE is never floated).

#

Drive HLDA LOW.

PERIPHERAL ARCHITECTURE

All of the integrated peripherals are controlled by
16-bit registers contained within an internal 256-byte
control block. The control block may be mapped into

either memory or I/O space. Internal logic will recog­nize control block addresses and respond to bus cy­cles. During bus cycles to internal registers, the bus
controller will signal the operation externally (i.e., the
RD

,WR, status, address, data, etc., lines will be driv-

en as in a normal bus cycle), but D

15–0(D7–0

),
SRDY, and ARDY will be ignored. The base address
of the control block must be on an even 256-byte
boundary (i.e., the lower 8 bits of the base address
are all zeros).

The control block base address is programmed by a
16-bit relocation register contained within the control
block at offset FEH from the base address of the
control block. It provides the upper 12 bits of the
base address of the control block.

In addition to providing relocation information for the
control block, the relocation register contains bits
which place the interrupt controller into Slave Mode,
and cause the CPU to interrupt upon encountering
ESC instructions.

Chip-Select/Ready Generation Logic

The processor contains logic which provides
programmable chip-select generation for both mem­ories and peripherals. In addition, it can be pro­grammed to provide READY (or WAIT state) genera­tion. It can also provide latched address bits A1 and
A2. The chip-select lines are active for all memory
and I/O cycles in their programmed areas, whether
they be generated by the CPU or by the integrated
DMA unit.

MEMORY CHIP SELECTS

The processor provides 6 memory chip select out­puts for 3 address areas; upper memory, lower
memory, and midrange memory. One each is provid­ed for upper memory and lower memory, while four
are provided for midrange memory.

UPPER MEMORY CS

The processor provides a chip select, called UCS,
for the top of memory. The top of memory is usually
used as the system memory because after reset the
processor begins executing at memory location
FFFF0H.

LOWER MEMORY CS

The processor provides a chip select for low memo­ry called LCS

. The bottom of memory contains the

interrupt vector table, starting at location 00000H.

10

10