Intel Corporation PA28F400BL-T150, PA28F400BL-B150 Datasheet

4-MBlT (256K x 16, 512K x 8)
LOW-POWER BOOT BLOCK

FLASH MEMORY FAMILY

28F400BL-T/B, 28F004BL-T/B

Y

Low Voltage Operation for Very
Low-Power Portable Applications
ÐV
ÐV

Y

Expanded Temperature Range
Ð

Y

x8/x16 Input/Output Architecture

e

3.0V–3.6V Read

CC

e

3.15V–3.6V Program/Erase

CC

b

20§Ctoa70§C

Ð 28F400BL-T, 28F400BL-B
Ð For High Performance and High

Integration 16-bit and 32-bit CPUs

Y

x8-only Input/Output Architecture
Ð 28F004BL-T, 28F004BL-B
Ð For Space Constrained 8-bit

Applications

Y

Upgradeable to Intel’s SmartVoltage
Products

Y

Optimized High Density Blocked
Architecture
Ð One 16-KB Protected Boot Block
Ð Two 8-KB Parameter Blocks
Ð One 96-KB Main Block
Ð Three 128-KB Main Blocks
Ð Top or Bottom Boot Locations

Y

Extended Cycling Capability
Ð 10,000 Block Erase Cycles

Y

Automated Word/Byte Write and Block
Erase
Ð Command User Interface
Ð Status Registers
Ð Erase Suspend Capability

Y

SRAM-Compatible Write Interface

Y

Automatic Power Savings Feature
Ð 0.8 mA typical I

Active Current in

CC

Static Operation

Y

Very High-Performance Read
Ð 150 ns Maximum Access Time
Ð 65 ns Maximum Output Enable Time

Y

Low Power Consumption
Ð 15 mA Typical Active Read Current

Y

Reset/Deep Power-Down Input:
Ð 0.2 mAI

CC

Typical

Ð Acts as Reset for Boot Operations

Y

Write Protection for Boot Block

Y

Hardware Data Protection Feature
Ð Erase/Write Lockout During Power

Transitions

Y

Industry Standard Surface Mount
Packaging
Ð 28F400BL: JEDEC ROM

Compatible
44-Lead PSOP
56-Lead TSOP

Ð 28F004BL: 40-Lead TSOP

Y

12V Word/Byte Write and Block Erase
ÐV

Y

ETOXTMIII Flash Technology

e

12Vg5% Standard

PP

Ð 3.3V Read

*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

November 1995COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 290450-005

28F400BL-T/B, 28F004BL-T/B

Intel’s 4-Mbit Low Power Flash Memory Family is an extension of the Boot Block Architecture which includes
block-selective erasure, automated write and erase operations and standard microprocessor interface. The
4-Mbit Low Power Flash Memory Family enhances the Boot Block Architecture by adding more density and
blocks, x8/x16 input/output control, very low power, very high speed, an industry standard ROM compatible
pinout and surface mount packaging. The 4-Mbit low power flash family opens a new capability for 3V battery­operated portable systems and is an easy upgrade to Intel’s 2-Mbit Low Power Boot Block Flash Memory
Family.

The Intel 28F400BL-T/B are 16-bit wide low power flash memory offerings. These high density flash memories
provide user selectable bus operation for either 8-bit or 16-bit applications. The 28F400BL-T and 28F400BL-B
are 4,194,304-bit non-volatile memories organized as either 524,288 bytes or 262,144 words of information.
They are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the
industry standard ROM/EPROM pinout. The Intel 28F004BL-T/B are 8-bit wide low power flash memories
with 4,194,304 bits organized as 524,288 bytes of information. They are offered in a 40-Lead TSOP package,
which is ideal for space-constrained portable systems.

These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The 28F400BL-T/28F004BL-T provide block locations compatible with
Intel’s Low Voltage MCS-186 family, i386
compatibility with Intel’s 80960KX and 80960SX families as well as other low voltage embedded microproces­sors.

The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 150 ns, these 4-Mbit low power flash devices are very high performance memories at

3.3V which interface to a wide range of low voltage microprocessors and microcontrollers. A deep power­down mode lowers the total V
systems such as Handy Cellular Phones. For very high speed applications using a 5V supply, refer to the Intel

CC

28F400BX-T/B, 28F004BX-T/B 4-Mbit Boot Block Flash Memory family datasheet.

Manufactured on Intel’s 0.8 micron ETOX III process, the 4-Mbit flash memory family provides world class
quality, reliability and cost-effectiveness at the 4 Mbit density level.

TM

, i486TMmicroprocessors. The 28F400BL-B/28F004BL-B provide

power consumption to 0.66 mW which is critical in handheld battery powered

2

28F400BL-T/B, 28F004BL-T/B

1.0 PRODUCT FAMILY OVERVIEW

Throughout this datasheet 28F400BL refers to both
the 28F400BL-T and 28F400BL-B devices and
28F004BL refers to both the 28F004BL-T and
28F004BL-B devices. The 4-Mbit flash family refers
to both the 28F400BL and 28F004BL products. This
datasheet comprises the specifications for four sep­arate products in the 4-Mbit flash family, Section 1
provides an overview of the 4-Mbit flash family in­cluding applications, pinouts and pin descriptions.
Sections 2 and 3 describe in detail the specific mem­ory organizations for the 28F400BL and 28F004BL
products respectively, Section 4 combines a de­scription of the family’s principles of operations. Fi­nally section 5 describes the family’s operating
specifications.

Product Family

x8/x16 Products x8-Only Products

28F400BL-T 28F004BL-T

28F400BL-B 28F004BL-B

1.1 Designing for Upgrade to
SmartVoltage Products

Today’s high volume boot block products are up­gradeable to Intel’s SmartVoltage boot block prod­ucts that provide program and erase operation at 5V
or 12V V
Intel’s SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this datasheet:

1. DU pin is replaced by WP

lock and unlock the boot block with logic signals.

2. 5V Program/Erase operation uses proven pro-

gram and erase techniques with 5V
plied to V

3. Enhanced circuits optimize performance at 3.3V

V

CC

Refer to the 2, 4 or 8Mbit SmartVoltage Boot Block
Flash Memory datasheets for complete specifica­tions.

When you design with 12V V
you should provide the capability in your board de­sign to upgrade to SmartVoltage products.

Follow these guidelines to ensure compatibility:

1. Connect DU (WP

a control signal or to V

2. If adding a switch on V

switch to GND for complete write protection.

3. Allow for connecting 5V to V

12V from the V

and read operation at 3V or 5V VCC.

PP

Ý

to provide a means to

.

PP

.

boot block products

PP

Ý

on SmartVoltage products) to

or GND.

CC

for write protection,

PP

and disconnect

line, if desired.

PP

PP

g

10% ap-

1.2 Main Features

The 28F400BL/28F004BL boot block flash memory
family is a very high performance 4-Mbit (4,194,304
bit) memory family organized as either 256 KWords
(262,144 words) of 16 bits each or 512 Kbytes
(524,288 bytes) of 8 bits each.

Seven Separately Erasable Blocks including a
Hardware-Lockable boot block (16,384 Bytes),
two parameter blocks (8,192 Bytes each) and four
main blocks (1 block of 98,304 Bytes and 3 blocks

of 131,072 Bytes) are included on the 4-Mbit family.
An erase operation erases one of the main blocks in
typically 3.4 seconds and the boot or parameter
blocks in typically 2.0 seconds, independent of the
remaining blocks. Each block can be independently
erased and programmed 10,000 times.

The Boot Block is located at either the top (-T) or
the bottom (-B) of the address map in order to ac­commodate different microprocessor protocols for
boot code location. The hardware Iockable boot
block provides the most secure code storage. The
boot block is intended to store the kernel code re­quired for booting-up a system. When the RP
between 11.4V and 12.6V the boot block is unlocked
and program and erase operations can be per­formed. When the RP

Ý

pin is at or below 4.1V the
boot block is locked and program and erase opera­tions to the boot block are ignored.

The 28F400BL products are available in the
ROM/EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package and
the 56-Lead TSOP (Thin Small Outline, 1.2mm thick)
package as shown in Figures 3 and 4, The
28F004BL products are available in the 40-Lead
TSOP (1.2mm thick) package as shown in Figure 5.

The Command User Interface (CUI) serves as the
interface between the microprocessor or microcon­troller and the internal operation of the 28F400BL
and 28F004BL flash memory products.

Program and Erase Automation allow program
and erase operations to be executed using a two­write command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, there­by unburdening the microprocessor or microcontrol­ler. Writing of memory data is performed in word or
byte increments for the 28F400BL family and in byte
increments for the 28F004BL family typically within
11 ms.

Ý

pin is

3

28F400BL-T/B, 28F004BL-T/B

The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.

Maximum Access Time of 150 ns (t
over the commercial temperature range (0

a

70§C), VCCsupply voltage range (3.0V to 3.6V,

) is achieved

ACC

Cto

§

4.5V to 5.5V) and 50 pF output load.

I

Program current is 40 mA for x16 operation

pp

and 30 mA for x8 operation. I
30 mA maximum. V
voltage is 11.4V to 12.6V (V

erase and programming

PP

der all operating conditions.

Typical I

for the x16 products and the x8 products.

Active Current of 15 mA is achieved

CC

Erase current is

PP

e

12Vg5%) un-

PP

The 4-Mbit flash family is also designed with an Au­tomatic Power Savings (APS) feature to minimize
system battery current drain and allow for very low
power designs. Once the device is accessed to read
the array data, APS mode will immediately put the
memory in static mode of operation where I
current is typically 0.8 mA until the next read is initia-

CC

active

ted.

When the CEÝand RPÝpins are at VCCand the

Ý

BYTE

pin (28F400BX-L-only) is at either VCCor
GND the CMOS Standby mode is enabled where
I

is typically 45 mA.

CC

A Deep Power-Down Mode is enabled when the
PWD pin is at ground minimizing power consumption
and providing write protection during power-up con­ditions. I
is 0.20 mA typical. An initial maximum access time

current during deep power-down mode

CC

or Reset Time of 600 ns is required from RP
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 1 ms until
writes to the Command User Interface are recog­nized. When RP

Ý

is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature pre­vents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to RP

Ý

to reset the memory to nor­mal read mode upon activation of the Reset pin.
When the CPU enters reset mode, it expects to read
the contents of a memory location. Furthermore,
with on-chip program/erase automation in the

Ý

4-Mbit family and the RP

functionality for data pro­tection, when the CPU is reset and even if a program
or erase command is issued, the device will not rec­ognize any operation until RP

Ý

returns to its normal

state.

For the 2SF400BL, Byte-wide or Word-wide In­put/Output Control is possible by controlling the

Ý

BYTE

pin. When the BYTEÝpin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through DQ[0:7]. During the byte­wide mode, DQ[8:14]are tri-stated and DQ15/A
becomes the lowest order address pin. When the

Ý

BYTE

pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DQ[0:15].

1.3 Applications

The 4-Mbit low power boot block flash memory fami­ly combines high density, very low power, high per­formance, cost-effective flash memories with block­ing and hardware protection capabilities. Its flexibility
and versatility will reduce costs throughout the prod­uct life cycle. Flash memory is ideal for Just-In-Time
production flow, reducing system inventory and
costs, and eliminating component handling during
the production phase. During the product life cycle,
when code updates or feature enhancements be­come necessary, flash memory will reduce the up­date costs by allowing either a user-performed code
change via floppy disk or a remote code change via
a serial link. The 4-Mbit flash family provides full
function, blocked flash memories suitable for a wide
range of applications. These applications include
Extended PC BIOS and ROM-able applications
storage, Handy Digital Cellular Phone program
and data storage and various other low power em­bedded applications where both program and data
storage are required.

Portable systems such as Notebook/Palmtop com­puters, are ideal applications for the 4-Mbit low pow-

Ý

er flash products. Portable and handheld personal
computer applications are becoming more complex
with the addition of power management software to
take advantage of the latest microprocessor tech­nology, the availability of ROM-based application
software, pen tablet code for electronic hand writing,
and diagnostic code. Figure 1 shows an example of
a 28F400BL-T application.

This increase in software sophistication augments
the probability that a code update will be required
after the Notebook is shipped. The 4-Mbit flash
products provide an inexpensive update solution for
the notebook and handheld personal computers
while extending their product lifetime. Furthermore,
the 4-Mbit flash products’ deep power-down mode
provides added flexibility for these battery-operated
portable designs which require operation at very low
power levels.

b

1

4

28F400BL-T/B, 28F004BL-T/B

The 4-Mbit low power flash products also provide
excellent design solutions for Handy Digital Cellular
Phone applications requiring low voltage supply,
high performance, high density storage capability
coupled with modular software designs, and a small
form factor package (x8-only bus). The 4-Mbit’s
blocking scheme allows for an easy segmentation of
the embedded code with; 16-Kbytes of Hardware­Protected Boot code, 4 Main Blocks of program
code and 2 Parameter Blocks of 8-Kbytes each for
frequently updatable data storage and diagnostic

Figure 1. 28F400BL Interface to Intel386TMEX Embedded Processor

messages (e.g., phone numbers, authorization
codes). Figure 2 is an example of such an applica­tion with the 28F004BL-T.

These are a few actual examples of the wide range
of applications for the 4-Mbit low power Boot Block
flash memory family which enable system designers
achieve the best possible product design. Only your
imagination limits the applicability of such a versatile
low power product family.

290450– 7

290450– 23

Figure 2. 28F004BL Interface to INTEL 80L188EB Low Voltage 8-bit Embedded Processor

5

28F400BL-T/B, 28F004BL-T/B

1.4 Pinouts

The 28F400BL 44-Lead PSOP pinout follows the
industry standard ROM/EPROM pinout as shown
in Figure 3 and provides an upgrade for the
28F200BL Low Power Boot Block flash memory
family. Furthermore, the 28F400BL 56-Lead TSOP

pinout shown in Figure 4 provides density upgrades
to future higher density boot block memories.

The 28F004BL 40-Lead TSOP pinout shown in Fig­ure 5 is 100% compatible and provides a density
upgrade for the 28F002BL 2-Mbit Low Power Boot
Block flash memory family.

290450– 24

Figure 3. PSOP Lead Configuration for x8/x16 28F400BL

6

28F400BL-T/B, 28F004BL-T/B

Figure 4. TSOP Lead Configuration for x8 28F400BL

Figure 5. TSOP Lead Configuration for x8 28F004BL

290450– 6

290450– 5

7

28F400BL-T/B, 28F004BL-T/B

1.5 Pin Descriptions for x8/x16 28F400BL

Symbol Type Name and Function

A0–A

17

A

9

DQ0–DQ

DQ8–DQ

Ý

CE

Ý

RP

Ý

OE

Ý

WE

I ADDRESS INPUTS for memory addresses. Addresses are internally latched

during a write cycle.

I ADDRESS INPUT: When A9is at 12V the signature mode is accessed. During this

mode A
a logic low only the lower byte of the signatures are read. DQ

decodes between the manufacturer and device ID’s. When BYTEÝis at

0

care in the signature mode when BYTEÝis low.

I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle

7

during a program command. Inputs commands to the command user interface
when CE

Ý

and WEÝare active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and status register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.

I/O DATA INPUT/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle

15

during a program command. Data is internally latched during the write and program
cycles. The data pins float to tri-state when the chip is deselected or the outputs
are disabled as in the byte-wide mode (BYTE

/A

DQ

becomes the lowest order address for data output on DQ0–DQ7.

b

15

1

I CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

Ý

sense amplifiers. CE

is active low; CEÝhigh deselects the memory device and
reduces power consumption to standby levels. If CE
at a CMOS high level, the standby current will increase due to current flow through

Ý

the CE

and RPÝinput stages.

I RESET/DEEP POWER-DOWN: Provides Three-State control. Puts the device in

deep power-down mode. Locks the boot block from program/erase.

When RP

Ý

is at logic high level and equals 4.1V maximum the boot block is

locked and cannot be programmed or erased.

e

Ý

When RP

11.4V minimum the boot block is unlocked and can be programmed

or erased.

When RP

Ý

is at a logic low level the boot block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RP

Ý

transitions from logic low to logic high, the flash memory

enters the read-array mode.

I OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

read cycle. OEÝis active low.

I WRITE ENABLE: Controls writes to the Command Register and array blocks.

Ý

is active low. Addresses and data are latched on the rising edge of the WE

WE
pulse.

/A

b

15

e

Ý

‘‘0’’). In the byte-wide mode

Ý

and RPÝare high, but not

is a don’t

1

Ý

8

28F400BL-T/B, 28F004BL-T/B

1.5 Pin Descriptions for x8/x16 28F400BL (Continued)

Symbol Type Name and Function

Ý

BYTE

V

PP

V

CC

GND GROUND: For all internal circuitry.

NC NO CONNECT: Pin may be driven or left floating.

DU DON’T USE PIN: Pin should not be connected to anything.

I BYTEÝENABLE: Controls whether the device operates in the byte-wide mode (x8) or

the word-wide mode (x16). BYTE
read and programmed on DQ
address that decodes between the upper and lower byte. DQ
during the byte-wide mode. BYTE
read and programmed on DQ

e

Ý

‘‘0’’ enables the byte-wide mode, where data is

–DQ7and DQ15/A

0

e

Ý

‘‘1’’ enables the word-wide mode where data is

–DQ15.

0

b

1

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.

PP

k

V

PPLMAX

memory contents cannot be altered.

Note: V

DEVICE POWER SUPPLY (3.3Vg0.3, 5Vg10%)

becomes the lowest order

–DQ14are tri-stated

8

9

28F400BL-T/B, 28F004BL-T/B

1.6 Pin Descriptions for x8 28F004BL

Symbol Type Name and Function

A0–A

18

A

9

DQ0–DQ

Ý

CE

Ý

RP

Ý

OE

Ý

WE

V

PP

V

CC

GND GROUND: For all internal circuitry.

NC NO CONNECT: Pin may be driven or left floating.

DU DON’T USE PIN: Pin should not be connected to anything.

I ADDRESS INPUTS for memory addresses. Addresses are internally latched during

a write cycle.

I ADDRESS INPUT: When A9is at 12V the signature mode is accessed. During this

mode A

I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle

7

during a program command. Inputs commands to the command user interface
when CE

decodes between the manufacturer and device ID’s.

0

Ý

and WEÝare active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and status register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.

I CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

Ý

sense amplifiers. CE

is active low; CEÝhigh deselects the memory device and

reduces power consumption to standby levels.

I RESET/DEEP POWER-DOWN: Provides Three-State control. Puts the device in

deep power-down mode. Locks the Boot Block from program/erase.

When RP

Ý

is at logic high level and equals 4.1V maximum the Boot Block is locked

and cannot be programmed or erased.

e

Ý

When RP

11.4V minimum the Boot Block is unlocked and can be programmed

or erased.

When RPÝis at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RP

Ý

transitions from logic low to logic high, the flash memory

enters the read-array mode.

I OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

Ý

read cycle. OE

is active low.

I WRITE ENABLE: Controls writes to the Command Register and array blocks. WE

is active low. Addresses and data are latched on the rising edge of the WEÝpulse.

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.

PP

k

V

PPLMAX

memory contents cannot be altered.

Note: V

DEVICE POWER SUPPLY (3.3Vg0.3V, 5Vg10%)

Ý

10

2.0 28F400BL PRODUCTS DESCRIPTION

28F400BL-T/B, 28F004BL-T/B

290450– 1

Figure 6. 28F400BL Word/Byte-Wide Block Diagram

11

28F400BL-T/B, 28F004BL-T/B

2.1 28F400BL Memory Organization

2.1.1 BLOCKING

The 28F400BL uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block ad­dress range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F400BL is
a random read/write memory, only erasure is per­formed by block.

2.1.1.1 Boot Block Operation and Data

The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow­er failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RP
be erased and written when RP
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address lo­cations of the boot block for the 28F400BL-T and
28F400BL-B.

2.1.1.2 Parameter Block Operation

The 28F400BL has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to provide
storage for frequently updated system parameters
and configuration or diagnostic information. The pa­rameter blocks can also be used to store additional
boot or main code. The parameter blocks however,
do not have the hardware write protection feature
that the boot block has. The parameter blocks pro­vide for more efficient memory utilization when deal­ing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for ad­dress locations of the parameter blocks for the
28F400BL-T and 28F400BL-B.

2.1.1.3 Main Block Operation

Four main blocks of memory exist on the 28F400BL
(3 x 128-Kbyte blocks and 1 x 96-Kbyte blocks). See
the following section on Block Memory Map for the
address location of these blocks for the 28F400BL-T
and 28F400BL-B products.

Protection

Ý

is not at 12V. The boot block can

Ý

is held at 12V for

2.1.2 BLOCK MEMORY MAP

Two versions of the 28F400BL product exist to sup­port two different memory maps of the array blocks
in order to accommodate different microprocessor
protocols for boot code location. The 28F400BL-T
memory map is inverted from the 28F400BL-B mem­ory map.

2.1.2.1 28F400BL-B Memory Map

The 28F400BL-B device has the 16-Kbyte boot
block located from 00000H to 01FFFH to accommo­date those microprocessors that boot from the bot­tom of the address map at 00000H. In the
28F400BL-B the first 8-Kbyte parameter block re­sides in memory space from 02000H to 02FFFH.
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96-Kbyte main block resides in memory space from
04000H to 0FFFFH. The three 128-Kbyte main
block resides in memory space from 10000H to
1FFFFH, 20000H to 2FFFFH and 30000H to
3FFFFH (word locations). See Figure 7.

(Word Addresses)

3FFFFH

128-Kbyte MAIN BLOCK

30000H

2FFFFH

128-Kbyte MAIN BLOCK

20000H

1FFFFH

128-Kbyte MAIN BLOCK

10000H

0FFFFH

96-Kbyte MAIN BLOCK

04000H
03FFFH

03000H
02FFFH

02000H
01FFFH

00000H

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

Figure 7. 28F400BL-B Memory Map

12

2.1.2.2 28F400BL-T Memory Map

The 28F400BL-T device has the 16-Kbyte boot
block located from 3E000H to 3FFFFH to accommo­date those microprocessors that boot from the top
of the address map. In the 28F400BX-T the first
8-Kbyte parameter block resides in memory space
from 3D000H to 3DFFFH. The second 8-Kbyte pa­rameter block resides in memory space from
3C000H to 3CFFFH. The 96-Kbyte main block re­sides in memory space from 30000H to 3BFFFH.
The three 128-Kbyte main blocks reside in memory
space from 20000H to 2FFFFH, 10000H to 1FFFFH
and 00000H to 0FFFFH as shown in Figure 8.

(Word Addresses)

3FFFFH

3E000H

3DFFFH

3D000H

3CFFFH

3C000H

3BFFFH

30000H

2FFFFH

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

28F400BL-T/B, 28F004BL-T/B

128-Kbyte MAIN BLOCK

20000H

1FFFFH

128-Kbyte MAIN BLOCK

10000H

0FFFFH

128-Kbyte MAIN BLOCK

00000H

Figure 8. 28F400BL-T Memory Map

13

28F400BL-T/B, 28F004BL-T/B

3.0 28F004BL PRODUCTS DESCRIPTION

290450– 3

14

Figure 9. 28F004BL and Byte-Wide Block Diagram