Intel Corporation PA28F200BX-T120, PA28F200BX-B80, PA28F200BX-T80 Datasheet

2-MBIT (128K x 16, 256K x 8)

BOOT BLOCK

FLASH MEMORY FAMILY

28F200BX-T/B, 28F002BX-T/B

x8/x16 Input/Output Architecture Ð 28F200BX-T, 28F200BX-B Ð For High Performance and High

Integration 16-bit and 32-bit CPUs

x8-only Input/Output Architecture Ð 28F002BX-T 28F002BX-B Ð For Space Constrained 8-bit

Applications

Upgradeable to Intel’s SmartVoltage Products

Optimized High-Density Blocked Architecture Ð One 16-KB Protected Boot Block Ð Two 8-KB Parameter Blocks Ð One 96-KB Main Block Ð One 128 KB Main Block Ð Top or Bottom Boot Locations

Extended Cycling Capability Ð 100,000 Block Erase Cycles

Automated Word/Byte Write and Block Erase Ð Command User Interface Ð Status Registers Ð Erase Suspend Capability

SRAM-Compatible Write Interface

Automatic Power Savings Feature Ð 1 mA Typical I

Active Current in

Static Operation

Hardware Data Protection Feature Ð Erase/Write Lockout during Power

Transitions

Very High-Performance Read Ð 60/80/120 ns Maximum Access Time Ð 30/40/40 ns Maximum Output Enable

Time

Low Power Consumption Ð 20 mA Typical Active Read Current

Reset/Deep Power-Down Input Ð 0.2 mAI

Typical

Ð Acts as Reset for Boot Operations

Extended Temperature Operation

40§Ctoa85§C

Write Protection for Boot Block

Industry Standard Surface Mount Packaging Ð 28F200BX: JEDEC ROM Compatible

44-Lead PSOP 56-Lead TSOP

Ð 28F002BX: 40-Lead TSOP

12V Word/Byte Write and Block Erase

ÐV ÐV

ETOXTMIII Flash Technology

12Vg5% Standard

12Vg10% Option

Ð 5V Read

Independent Software Vendor Support

*Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

28F200BX-T/B, 28F002BX-T/B

Intel’s 2-Mbit Flash Memory Family is an extension of the Boot Block Architecture which includes block-selective erasure, automated write and erase operations and standard microprocessor interface. The 2-Mbit Flash Memory Family enhances the Boot Block Architecture by adding more density and blocks, x8/x16 input/output control, very high speed, low power, an industry-standard ROM compatible pinout and surface mount packaging. The 2-Mbit flash family allows for an easy upgrade to Intel’s 4-Mbit Boot Block Flash Memory Family.

The Intel 28F200BX-T/B are 16-bit wide flash memory offerings. These high-density flash memories provide user selectable bus operation for either 8-bit or 16-bit applications. The 28F200BX-T and 28F200BX-B are 2,097,152-bit nonvolatile memories organized as either 262,144 bytes or 131,072 words of information. They are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industrystandard ROM/EPROM pinout.

The Intel 28F002BX-T/B are 8-bit wide flash memories with 2,097,152 bits organized as 262,144 bytes of information. They are offered in a 40-lead TSOP package, which is ideal for space-constrained portable systems.

These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified word/byte write and block erasure. The 28F200BX-T/28F002BX-T provide block locations compatible with Intel’s MCS 28F002BX-B provide compatibility with Intel’s 80960KX and 80960SX families as well as other embedded microprocessors.

The boot block includes a data protection feature to protect the boot code in critical applications. With a maximum access time of 60 ns, these 2-Mbit flash devices are very high-performance memories which interface at zero wait-state to a wide range of microprocessors and microcontrollers. A deep power-down mode lowers the total V For very low-power applications using a 3.3V supply, refer to the Intel 28F200BX-TL/BL, 28F002BX-TL/BL 2-Mbit Boot Block Flash Memory Family datasheet.

-186 family, 80286, i386TM, i486TM, i860TMand 80960CA microprocessors. The 28F200BX-B/

power consumption to 1 mW typical. This is critical in handheld battery-powered systems.

Manufactured on Intel’s 0.8 micron ETOX III process, the 2-Mbit flash memory family provides world-class quality, reliability and cost-effectiveness at the 2-Mbit density level.

28F200BX-T/B, 28F002BX-T/B

1.0 PRODUCT FAMILY OVERVIEW

Throughout this datasheet the 28F200BX refers to both the 28F200BX-T and 28F200BX-B devices and 28F002BX refers to both the 28F002BX-T and 28F002BX-B devices. The 2-Mbit flash memory family refers to both the 28F200BX and 28F002BX products. This datasheet comprises the specifications for four separate products in the 2-Mbit flash memory family. Section 1 provides an overview of the 2-Mbit flash memory family including applications, pinouts and pin descriptions. Sections 2 and 3 describe in detail the specific memory organizations for the 28F200BX and 28F002BX products respectively. Section 4 combines a description of the family’s principles of operations. Finally Section 5 describes the family’s operating specifications.

PRODUCT FAMILY

x8/x16 Products x8-Only Products

28F200BX-T 28F002BX-T

28F200BX-B 28F002BX-B

1.1 Designing for Upgrade to SmartVoltage Products

Today’s high volume boot block products are upgradable to Intel’s SmartVoltage boot block products that provide program and erase operation at 5V or 12V V Intel’s SmartVoltage boot block products provide the following enhancements to the boot block products described in this data sheet:

1. DU pin is replaced by WP

to lock and unlock the boot block with logic signals.

2. 5V Program/Erase operation uses proven pro-

gram and erase techniques with 5V plied to VPP.

3. Enhanced circuits optimize performance at 3.3V

Refer to the 2, 4 or 8 Mbit SmartVoltage Boot Block Flash Memory Data Sheets for complete specifications.

When you design with 12V V you should provide the capability in your board design to upgrade to SmartVoltage products.

Follow these guidelines to ensure compatibility:

1. Connect DU (WPÝon SmartVoltage products) to

a control signal or to V

2. If adding a switch on VPPfor write protection,

switch to GND for complete write protection.

3. Allow for connecting 5V to V

12V from the V

and read operation at 3V or 5V VCC.

to provide a means

boot block products

or GND.

and disconnect

line, if desired.

10% ap-

1.2 Main Features

The 28F200BX/28F002BX boot block flash memory family is a very high performance 2-Mbit (2,097,152 bit) memory family organized as either 128 KWords (131,072 words) of 16 bits each or 256 Kbytes (262,144 bytes) of 8 bits each.

Five Separately Erasable Blocks including a hardware-lockable boot block (16,384 Bytes), two parameter blocks (8,192 Bytes each) and two main blocks (1 block of 98,304 Bytes and 1 block of

131,072 Bytes) are included on the 2-Mbit family. An erase operation erases one of the main blocks in typically 2.4 seconds, and the boot or parameter blocks in typically 1.0 second. Each block can be independently erased and programmed 100,000 times.

The Boot Block is located at either the top (28F200BX-T, 28F002BX-T) or the bottom (28F200BX-B, 28F002BX-B) of the address map in order to accommodate different microprocessor protocols for boot code location. The hardware locka- ble boot block provides the most secure code storage. The boot block is intended to store the kernel code required for booting-up a system. When the

pin is between 11.4V and 12.6V the boot block is unlocked and program and erase operations can be performed. When the RP the boot block is locked and program and erase operations to the boot block are ignored.

The 28F200BX products are available in the ROM/ EPROM compatible pinout and housed in the 44Lead PSOP (Plastic Small Outline) package and the 56-Lead TSOP (Thin Small Outline, 1.2mm thick) package as shown in Figures 3 and 4. The 28F002BX products are available in the 40-Lead TSOP (1.2mm thick) package as shown in Figure 5.

The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the 28F200BX and 28F002BX flash memory products.

Program and Erase Automation allows program and erase operations to be executed using a twowrite command sequence to the CUI. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in word or byte increments for the 28F200BX family and in byte increments for the 28F002BX family typically within 9 ms which is a 100% improvement over current flash memory products.

pin is at or below 6.5V

28F200BX-T/B, 28F002BX-T/B

The Status Register (SR) indicates the status of the WSM and whether the WSM successfully completed the desired program or erase operation.

Maximum Access Time of 60 ns (t over the commercial temperature range (0 70

C), 5% VCCsupply voltage range (4.75V to

) is achieved

ACC

Cto

5.25V) and 30 pF output load. Refer to Figure 19; vs Output Load Capacitance for larger output

ACC

loads. Maximum Access Time of 80 ns (t achieved over the commercial temperature range, 10% V output load.

operation and 30 mA for x8 operation. I current is 30 mA maximum. V gramming voltage is 11.4V to 12.6V (V

5%) under all operating conditions. As an op-

tion, V

supply range (4.5V to 5.5V) and 100 pF

maximum Program current is 40 mA for x16

erase and pro-

can also vary between 10.8V to 13.2V (V

12Vg10%) with a guaranteed number of 100

ACC

Erase

) is

12V

block erase cycles.

Typical I for the x16 products (28F200BX), typical I Current of 20 mA is achieved for the x8 products

(28F200BX, 28F002BX). Refer to the I rent derating curves in this datasheet.

Active Current of 25 mA is achieved

active cur-

Active

The 2-Mbit boot block flash family is also designed with an Automatic Power Savings (APS) feature to minimize system battery current drain and allow for very low power designs. Once the device is accessed to read array data, APS mode will immediately put the memory in static mode of operation where I next read is initiated.

When the CE BYTE

active current is typically 1 mA until the

and RPÝpins are at VCCand the

pin (28F200BX-only) is at either VCCor GND the CMOS Standby mode is enabled where I

is typically 50 mA.

A Deep Power-Down Mode is enabled when the

pin is at ground minimizing power consumption and providing write protection during power-up conditions. I is 0.20 mA typical. An initial maximum access time

current during deep power-down mode

or Reset Time of 300 ns is required from RP switching until outputs are valid. Equivalently, the device has a maximum wake-up time of 215 ns until writes to the Command User Interface are recognized. When RP

is at ground the WSM is reset, the Status Register is cleared and the entire device is protected from being written to. This feature prevents data corruption and protects the code stored in the device during system reset. The system Reset pin can be tied to RP

to reset the memory to normal read mode upon activation of the Reset pin. With on-chip program/erase automation in the 2-Mbit family and the RP

functionality for data pro-

tection, when the CPU is reset and even if a program or erase command is issued, the device will not rec-

ognize any operation until RP

returns to its normal

state.

For the 28F200BX, Byte-wide or Word-wide Input/Output Control is possible by controlling the

BYTE

pin. When the BYTEÝpin is at a logic low the device is in the byte-wide mode (x8) and data is read and written through DQ[0:7]. During the bytewide mode, DQ[8:14]are tri-stated and DQ15/A becomes the lowest order address pin. When the

BYTE

pin is at a logic high the device is in the word-wide mode (x16) and data is read and written through DQ[0:15].

1.3 Applications

The 2-Mbit boot block flash family combines high density, high performance, cost-effective flash memories with blocking and hardware protection capabilities. Its flexibility and versatility will reduce costs throughout the product life cycle. Flash memory is ideal for Just-In-Time production flow, reducing system inventory and costs, and eliminating component handling during the production phase. During the product life cycle, when code updates or feature enhancements become necessary, flash memory will reduce the update costs by allowing either a userperformed code change via floppy disk or a remote code change via a serial link. The 2-Mbit boot block flash family provides full function, blocked flash memories suitable for a wide range of applications. These applications include Extended PC BIOS,

Digital Cellular Phone program and data storage, Telecommunication boot/firmware, and various

other embedded applications where both program and data storage are required.

Reprogrammable systems such as personal computers, are ideal applications for the 2-Mbit flash products. Portable and handheld personal computer applications are becoming more complex with the addition of power management software to take advantage of the latest microprocessor technology, the availability of ROM-based application software, pen tablet code for electronic hand writing, and diagnostic code. Figure 1 shows an example of a

28F200BX-T application.

This increase in software sophistication augments the probability that a code update will be required after the PC is shipped. The 2-Mbit flash products provide an inexpensive update solution for the notebook and handheld personal computers while extending their product lifetime. Furthermore, the 2-Mbit flash products’ power-down mode provides added flexibility for these battery-operated portable designs which require operation at very low power levels.

28F200BX-T/B, 28F002BX-T/B

The 2-Mbit flash products also provide excellent design solutions for Digital Cellular Phone and Telecommunication switching applications requiring high performance, high density storage capability coupled with modular software designs, and a small form factor package (x8-only bus). The 2-Mbit’s blocking scheme allows for an easy segmentation of the embedded code with; 16 Kbytes of HardwareProtected Boot code, 2 Main Blocks of program code and 2 Parameter Blocks of 8 Kbytes each for frequently updatable data storage and diagnostic

Figure 1. 28F200BX Interface to Intel386TMEX Embedded Processor

messages (e.g. phone numbers, authorization codes). Figure 2 is an example of such an application with the 28F002BX-T.

These are a few actual examples of the wide range of applications for the 2-Mbit Boot Block flash memory family which enable system designers to achieve the best possible product design. Only your imagination limits the applicability of such a versatile product family.

290448– 4

290448– 24

Figure 2. 28F002BX Interface to INTEL 80C188EB 8-Bit Embedded Microprocessor

28F200BX-T/B, 28F002BX-T/B

1.4 Pinouts

The 28F200BX 44-Lead PSOP pinout follows the industry standard ROM/EPROM pinout as shown in Figure 3 with an upgrade to the 28F400BX (4-Mbit flash family). Furthermore, the 28F200BX 56-Lead TSOP pinout shown in Figure 4 provides density upgrades to the 28F400BX and to future higher density boot block memories.

28F400BX 28F400BX

The 28F002BX 40-Lead TSOP pinout shown in Figure 5 is 100% compatible and provides a density upgrade to the 28F004BX 4-Mbit Boot Block flash memory.

290448– 25

Figure 3. PSOP Lead Configuration for x8/x16 28F200BX

28F200BX-T/B, 28F002BX-T/B

28F400BX 28F400BX

290448– 3

Figure 4. TSOP Lead Configuration for x8/x16 28F200BX

28F004BX 28F004BX

290448– 20

Figure 5. TSOP Lead Configuration for x8 28F002BX

28F200BX-T/B, 28F002BX-T/B

1.5 Pin Descriptions for the x8/x16 28F200BX

Symbol Type Name and Function

A0–A

DQ0–DQ

DQ8–DQ

BYTE

GND GROUND: For all internal circuitry.

NC NO CONNECT: Pin may be driven or left floating.

DU DON’T USE PIN: Pin should not be connected to anything.

I ADDRESS INPUTS for memory addresses. Addresses are internally latched

during a write cycle.

I ADDRESS INPUT: When A9is at 12V the signature mode is accessed. During this

mode A a logic low only the lower byte of the signatures are read. DQ care in the signature mode when BYTE

I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle

during a program command. Inputs commands to the Command User Interface when CE

decodes between the manufacturer and device ID’s. When BYTEÝis at

is low.

and WEÝare active. Data is internally latched during the write and program cycles. Outputs array, Intelligent Identifier and Status Register data. The data pins float to tri-state when the chip is deselected or the outputs are disabled.

I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle

during a program command. Data is internally latched during the write and program cycles. Outputs array data. The data pins float to tri-state when the chip is deselected or the outputs are disabled as in the byte-wide mode (BYTE

In the byte-wide mode DQ output on DQ

I CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

sense amplifiers. CE

–DQ7.

is active low; CEÝhigh deselects the memory device and

reduces power consumption to standby levels. If CE

becomes the lowest order address for data

at a CMOS high level, the standby current will increase due to current flow through the CEÝand RPÝinput stages.

I RESET/DEEP POWER-DOWN: Provides three-state control. Puts the device in

deep power-down mode. Locks the boot block from program/erase.

When RP

is at logic high level and equals 6.5V maximum the boot block is

locked and cannot be programmed or erased.

When RP

11.4V minimum the boot block is unlocked and can be programmed

or erased. When RPÝis at a logic low level the boot block is locked, the deep power-down

mode is enabled and the WSM is reset preventing any blocks from being programmed or erased, therefore providing data protection during power transitions. When RP

transitions from logic low to logic high the flash memory

enters the read array mode.

I OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

read cycle. OE

I WRITE ENABLE: Controls writes to the Command Register and array blocks.

is active low. Addresses and data are latched on the rising edge of the WE

is active low.

pulse.

I BYTEÝENABLE: Controls whether the device operates in the byte-wide mode

(x8) or the word-wide mode (x16). BYTE

pin must be controlled at CMOS levels to meet 100 mA CMOS current in the standby mode. BYTE byte-wide mode, where data is read and programmed on DQ

DQ and lower byte. DQ8–DQ14are tri-stated during the byte-wide mode. BYTE on DQ

becomes the lowest order address that decodes between the upper

‘‘1’’ enables the word-wide mode where data is read and programmed

–DQ15.

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block.

PPLMAX

memory contents cannot be altered.

Note: V

DEVICE POWER SUPPLY (5Vg10%, 5Vg5%)

is a don’t

‘‘0’’).

and RPÝare high, but not

‘‘0’’ enables the

–DQ7and

28F200BX-T/B, 28F002BX-T/B

1.6 Pin Descriptions for x8 28F002BX

Symbol Type Name and Function

A0–A

DQ0–DQ7I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle

ÝRPÝ

GND GROUND: For all internal circuitry.

NC NO CONNECT: Pin may be driven or left floating.

DU DON’T USE PIN: Pin should not be connected to anything.

I ADDRESS INPUTS for memory addresses. Addresses are internally latched during

a write cycle.

I ADDRESS INPUT: When A9is at 12V the signature mode is accessed. During this

mode A

decodes between the manufacturer and device ID’s.

during a program command. Inputs commands to the command user interface

when CE

and WEÝare active. Data is internally latched during the write and program cycles. Outputs array, Intelligent Identifier and status register data. The data pins float to tri-state when the chip is deselected or the outputs are disabled.

I CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

sense amplifiers. CE reduces power consumption to standby levels. If CE

is active low; CEÝhigh deselects the memory device and

and RPÝare high, but not at a CMOS high level, the standby current will increase due to current flow through the CEÝand RPÝinput stages.

I RESET/DEEP POWERDOWN: Provides Three-State control. Puts the device in

deep powerdown mode. Locks the Boot Block from program/erase.

When RP

is at logic high level and equals 6.5V maximum the Boot Block is locked

and cannot be programmed or erased.

When RP

11.4V minimum the Boot Block is unlocked and can be programmed

or erased. When RP

is at a logic low level the Boot Block is locked, the deep powerdown mode is enabled and the WSM is reset preventing any blocks from being programmed or erased, therefore providing data protection during power transitions. When RP

transitions from logic low to logic high, the flash memory

enters the read-array mode.

I OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

read cycle. OE

is active low.

I WRITE ENABLE: Controls writes to the Command Register and array blocks. WE

is active low. Addresses and data are latched on the rising edge of the WEÝpulse.

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or programming data in each block. Note: V

memory contents cannot be altered.

PPLMAX

DEVICE POWER SUPPLY (5Vg10%, 5Vg5%)

28F200BX-T/B, 28F002BX-T/B

2.0 28F200BX WORD/BYTE-WIDE PRODUCTS DESCRIPTION

290448– 1

Figure 6. 28F200BX Word/Byte-Wide Block Diagram

28F200BX-T/B, 28F002BX-T/B

2.1 28F200BX Memory Organization

2.1.1 BLOCKING

The 28F200BX uses a blocked array architecture to provide independent erasure of memory blocks. A block is erased independently of other blocks in the array when an address is given within the block address range and the Erase Setup and Erase Confirm commands are written to the CUI. The 28F200BX is a random read/write memory, only erasure is performed by block.

2.1.1.1 Boot Block Operation and Data Protection

The 16-Kbyte boot block provides a lock feature for secure code storage. The intent of the boot block is to provide a secure storage area for the kernel code that is required to boot a system in the event of power failure or other disruption during code update. This lock feature ensures absolute data integrity by preventing the boot block from being written or erased when RP be erased and written when RP the duration of the erase or program operation. This allows customers to change the boot code when necessary while providing security when needed. See the Block Memory Map section for address locations of the boot block for the 28F200BX-T and 28F200BX-B.

is not at 12V. The boot block can

is held at 12V for

2.1.1.3 Main Block Operation

Two main blocks of memory exist on the 28F200BX (1 x 128 Kbyte block and 1 x 96-Kbyte block). See the following section on Block Memory Map for the address location of these blocks for the 28F200BX-T and 28F200BX-B products.

2.1.2 BLOCK MEMORY MAP

Two versions of the 28F200BX product exist to support two different memory maps of the array blocks in order to accommodate different microprocessor protocols for boot code location. The 28F200BX-T memory map is inverted from the 28F200BX-B memory map.

2.1.2.1 28F200BX-B Memory Map

The 28F200BX-B device has the 16-Kbyte boot block located from 00000H to 01FFFH to accommodate those microprocessors that boot from the bottom of the address map at 00000H. In the 28F200BX-B the first 8-Kbyte parameter block resides in memory space from 02000H to 02FFFH. The second 8-Kbyte parameter block resides in memory space from 03000H to 03FFFH. The 96-Kbyte main block resides in memory space from 04000H to 0FFFFH. The 128-Kbyte main block resides in memory space from 10000H to 1FFFFH (word locations). See Figure 7.

2.1.1.2 Parameter Block Operation

The 28F200BX has 2 parameter blocks (8 Kbytes each). The parameter blocks are intended to provide storage for frequently updated system parameters and configuration or diagnostic information. The parameter blocks can also be used to store additional boot or main code. The parameter blocks however, do not have the hardware write protection feature that the boot block has. The parameter blocks provide for more efficient memory utilization when dealing with parameter changes versus regularly blocked devices. See the Block Memory Map section for address locations of the parameter blocks for the 28F200BX-T and 28F200BX-B.

(Word Addresses)

1FFFFH

128-Kbyte MAIN BLOCK

10000H

0FFFFH

96-Kbyte MAIN BLOCK

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

00000H

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

Figure 7. 28F200BX-B Memory Map

28F200BX-T/B, 28F002BX-T/B

2.1.2.2 28F200BX-T Memory Map

The 28F200BX-T device has the 16-Kbyte boot block located from 1E000H to 1FFFFH to accommodate those microprocessors that boot from the top of the address map. In the 28F200BX-T the first 8-Kbyte parameter block resides in memory space from 1D000H to 1DFFFH. The second 8-Kbyte parameter block resides in memory space from 1C000H to 1CFFFH. The 96-Kbyte main block resides in memory space from 10000H to 1BFFFH. The 128-Kbyte main block resides in memory space from 00000H to 0FFFFH as shown in Figure 8.

(Word Addresses)

1FFFFH

1E000H

1DFFFH

1D000H

1CFFFH

1C000H

1BFFFH

10000H

0FFFFH

00000H

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

Figure 8. 28F200BX-T Memory Map

3.0 28F002BX BYTE-WIDE PRODUCTS DESCRIPTION

28F200BX-T/B, 28F002BX-T/B

290448– 19

Figure 9. 28F002BX Byte-Wide Block Diagram

28F200BX-T/B, 28F002BX-T/B

3.1 28F002BX Memory Organization

3.1.1 BLOCKING

The 28F002BX uses a blocked array architecture to provide independent erasure of memory blocks. A block is erased independently of other blocks in the array when an address is given within the block address range and the Erase Setup and Erase Confirm commands are written to the CUI. The 28F002BX is a random read/write memory, only erasure is performed by block.

3.1.1.1 Boot Block Operation and Data Protection

The 16-Kbyte boot block provides a lock feature for secure code storage. The intent of the boot block is to provide a secure storage area for the kernel code that is required to boot a system in the event of power failure or other disruption during code update. This lock feature ensures absolute data integrity by preventing the boot block from being programmed or erased when RP can be erased and programmed when RP at 12V for the duration of the erase or program operation. This allows customers to change the boot code when necessary while still providing security when needed. See the Block Memory Map section for address locations of the boot block for the 28F002BX-T and 28F002BX-B.

3.1.1.2 Parameter Block Operation

The 28F002BX has 2 parameter blocks (8 Kbytes each). The parameter blocks are intended to provide storage for frequently updated system parameters and configuration or diagnostic information. The parameter blocks can also be used to store additional boot or main code. The parameter blocks however, do not have the hardware write protection feature that the boot block has. Parameter blocks provide for more efficient memory utilization when dealing with small parameter changes versus regularly blocked devices. See the Block Memory Map section for address locations of the parameter blocks for the 28F002BX-T and 28F002BX-B.

is not at 12V. The boot block

is held

3.1.1.3 Main Block Operation

Two main blocks of memory exist on the 28F002BX (1 x 128-Kbyte block and 1 x 96-Kbyte block). See the following section on Block Memory Map for address location of these blocks for the 28F002BX-T and 28F002BX-B.

3.1.2 BLOCK MEMORY MAP

Two versions of the 28F002BX product exist to support two different memory maps of the array blocks in order to accommodate different microprocessor protocols for boot code location. The 28F002BX-T memory map is inverted from the 28F002BX-B memory map.

3.1.2.1 28F002BX-B Memory Map

The 28F002BX-B device has the 16-Kbyte boot block located from 00000H to 03FFFH to accommodate those microprocessors that boot from the bottom of the address map at 00000H. In the 28F002BX-B the first 8-Kbyte parameter block resides in memory from 04000H to 05FFFH. The second 8-Kbyte parameter block resides in memory space from 06000H to 07FFFH. The 96-Kbyte main block resides in memory space from 08000H to 1FFFFH. The 128-Kbyte main block resides in memory space from 20000H to 3FFFFH. See Figure 10.

3FFFFH

128-Kbyte MAIN BLOCK

20000H

1FFFFH

96-Kbyte MAIN BLOCK

08000H 07FFFH

06000H 05FFFH

04000H 03FFFH

00000H

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

Figure 10. 28F002BX-B Memory Map

28F200BX-T/B, 28F002BX-T/B

3.1.2.2 28F002BX-T Memory Map

The 28F002BX-T device has the 16-Kbyte boot block located from 3C000H to 3FFFFH to accommodate those microprocessors that boot from the top of the address map. In the 28F002BX-T the first 8-Kbyte parmeter block resides in memory space from 3A000H to 3BFFFH. The second 8-Kbyte parameter block resides in memory space from 38000H to 39FFFH. The 96-Kbyte main block resides in memory space from 20000H to 37FFFH. The 128-Kbyte main block resides in memory space from 00000H to 1FFFFH.

3FFFFH

3C000H

3BFFFH

3A000H

39FFFH

38000H

37FFFH

20000H

1FFFFH

00000H

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

Figure 11. 28F002BX-T Memory Map

4.0 PRODUCT FAMILY PRINCIPLES

OF OPERATION

Flash memory augments EPROM functionality with in-circuit electrical write and erase. The 2-Mbit flash

family utilizes a Command User Interface (CUI) and internally generated and timed algorithms to simplify write and erase operations.

The CUI allows for 100% TTL-level control inputs, fixed power supplies during erasure and programming, and maximum EPROM compatibility.

In the absence of high voltage on the V 2-Mbit boot block flash family will only successfully

pin, the

execute the following commands: Read Array, Read Status Register, Clear Status Register and Intelligent Identifier mode. The device provides standard EPROM read, standby and output disable operations. Manufacturer Identification and Device Identification data can be accessed through the CUI or through the standard EPROM A9 high voltage access (V

) for PROM programming equipment.

The same EPROM read, standby and output disable functions are available when high voltage is applied to the VPPpin. In addition, high voltage on VPPallows write and erase of the device. All functions associated with altering memory contents: write and erase, Intelligent Identifier read and Read Status are accessed via the CUI.

The purpose of the Write State Machine (WSM) is to completely automate the write and erasure of the device. The WSM will begin operation upon receipt of a signal from the CUI and will report status back through a Status Register. The CUI will handle the

interface to the data and address latches, as well as system software requests for status while the WSM is in operation.

4.1 28F200BX Bus Operations

Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.

+ 33 hidden pages

Intel Corporation PA28F200BX-T120, PA28F200BX-B80, PA28F200BX-T80 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual