Intel Corporation PA28F200BL-T150, PA28F200BL-B150 Datasheet

2-MBIT (128K x 16, 256K x 8)

LOW-POWER BOOT BLOCK

FLASH MEMORY FAMILY

28F200BL-T/B, 28F002BL-T/B

Y

Low Voltage Operation for Very Low
Power Portable Applications
ÐV

Y

Expanded Temperature Range
Ð

Y

x8/x16 Input/Output Architecture

e

3.0V–3.6V

CC

b

20§Ctoa70§C

Ð 28F200BL-T, 28F200BL-B
Ð For High Performance and High

Integration 16-bit and 32-bit CPUs

Y

x8-only Input/Output Architecture
Ð 28F002BL-T, 28F002BL-B
Ð For Space Constrained 8-bit

Applications

Y

Upgradeable to Intel’s SmartVoltage
Products

Y

Optimized High-Density Blocked
Architecture
Ð One 16-KB Protected Boot Block
Ð Two 8-KB Parameter Blocks
Ð One 96-KB Main Block
Ð One 128-KB Main Block
Ð Top or Bottom Boot Locations

Y

Extended Cycling Capability
Ð 10,000 Block Erase Cycles

Y

Automated Word/Byte Write and Block
Erase
Ð Command User Interface
Ð Status Registers
Ð Erase Suspend Capability

Y

SRAM-Compatible Write Interface

Y

Automatic Power Savings Feature
Ð 0.8 mA Typical I

Active Current in

CC

Static Operation

Y

Very High-Performance Read
Ð 150 ns Maximum Access Time
Ð 65 ns Maximum Output Enable Time

Y

Low Power Consumption
Ð 15 mA Typical Active Read Current

Y

Reset/Deep Power-Down Input
Ð 0.2 mAI

CC

Typical

Ð Acts as Reset for Boot Operations

Y

Write Protection for Boot Block

Y

Hardware Data Protection Feature
Ð Erase/Write Lockout during Power

Transitions

Y

Industry Standard Surface Mount
Packaging
Ð 28F200BL: JEDEC ROM Compatible

44-Lead PSOP
56-Lead TSOP

Ð 28F002BL: 40-Lead TSOP

Y

12V Word/Byte Write and Block Erase
ÐV

Y

ETOXTMIII Flash Technology

e

12Vg5% Standard

PP

Ð 3.3V Read

Y

Independent Software Vendor Support

*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

December 1995COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 290449-006

28F200BL-T/B, 28F002BL-T/B

Intel’s 2-Mbit Low Power Flash Memory Family is an extension of the Boot Block Architecture which includes
block-selective erasure, automated write and erase operations and standard microprocessor interface. The
2-Mbit Flash Memory Family enhances the Boot Block Architecture by adding more density and blocks,
x8/x16 input/output control, very low power, very high speed, an industry standard ROM compatible pinout
and surface mount packaging. The 2-Mbit Low Power Flash Family opens a new capability for 3V battery-oper­ated portable systems and allows for an easy upgrade to Intel’s 4-Mbit Low Power Boot Block Flash Memory
Family.

The Intel 28F200BL-T/B are 16-bit wide flash memory offerings. These high density flash memories provide
user selectable bus operation for either 8-bit or 16-bit applications. The 28F200BL-T and 28F200BL-B are
2,097,152-bit non-volatile memories organized as either 262,144 bytes or 131,072 words of information. They
are offered in 44-Lead plastic SOP and 56-Lead TSOP packages. The x8/x16 pinout conforms to the industry
standard ROM/EPROM pinout.

The Intel 28F002BL-T/B are 8-bit wide flash memories with 2,097,152 bits organized as 262,144 bytes of
information. They are offered in a 40-Lead TSOP package, which is ideal for space-constrained portable
systems.

These devices use an integrated Command User Interface (CUI) and Write State Machine (WSM) for simplified
word/byte write and block erasure. The 28F200BL-T/28F002BL-T provide block locations compatible with
Intel’s low voltage MCS-186 family, i386
compatibility with Intel’s 80960KX and 80960SX families as well as other low voltage embedded microproces­sors.

The boot block includes a data protection feature to protect the boot code in critical applications. With a
maximum access time of 150 ns, these 2-Mbit flash devices are very high performance low power memories
which interface to a wide range of low power microprocessors and microcontrollers. A deep power-down mode
lowers the total V
as Handy Phones. For very high speed applications using a 5V supply, refer to the Intel 28F200BX-T/B,

power consumption to 0.66 mW. This is critical in handheld battery powered systems such

CC

28F002BX-T/B 2-Mbit Boot Block Flash Memory Family datasheet.

TM

, i486TMmicroprocessors. The 28F200BL-B/28F002BL-B provide

Manufactured on Intel’s 0.8 micron ETOX III process, the 2-Mbit low power flash memory family provides world
class quality, reliability and cost-effectiveness at the 2-Mbit density level.

2

28F200BL-T/B, 28F002BL-T/B

1.0 PRODUCT FAMILY OVERVIEW

Throughout this datasheet 28F200BL refers to both
the 28F200BL-T and 28F200BL-B devices and
28F002BL refers to both the 28F002BL-T and
28F002BL-B devices. The 2-Mbit flash family refers
to both the 28F200BL and 28F002BL products. This
datasheet comprises the specifications for four sep­arate products in the 2-Mbit flash memory family.
Section 1 provides an overview of the 2-Mbit flash
memory family including applications, pinouts and
pin descriptions. Sections 2 and 3 describe in detail
the specific memory organizations for the 28F200BL
and 28F002BL products respectively. Section 4
combines a description of the family’s principles of
operations. Finally, section 5 describes the family’s
operating specifications.

PRODUCT FAMILY

x8/x16 Products x8-Only Products

28F200BL-T 28F002BL-T
28F200BL-B 28F002BL-B

1.1 Designing for Upgrade to
SmartVoltage Products

Today’s high volume boot block products are up­gradable to Intel’s SmartVoltage boot block prod­ucts that provide program and erase operation at 5V
or 12V V
Intel’s SmartVoltage boot block products provide the
following enhancements to the boot block products
described in this data sheet:

1. DU pin is replaced by WP

to lock and unlock the boot block with logic sig­nals.

2. 5V Program/Erase operation uses proven pro-

gram and erase techniques with 5V
plied to V

3. Enhanced circuits optimize performance at 3.3V

V

CC

Refer to the 2, 4 or 8 Mbit SmartVoltage Boot Block
Flash Memory Data Sheets for complete specifica­tions.

When you design with 12V V
you should provide the capability in your board de­sign to upgrade to SmartVoltage products.

and read operation at 3V or 5V VCC.

PP

Ý

to provide a means

.

PP

.

boot block products

PP

g

10% ap-

Follow these guidelines to ensure compatibility:

Ý

1. Connect DU (WP
a control signal or to V

on SmartVoltage products) to

or GND.

CC

2. If adding a switch on VPPfor write protection,
switch to GND for complete write protection.

3. Allow for connecting 5V to V
12V from line V

line, if desired.

PP

and disconnect

PP

1.2 Main Features

The 28F200BL/28F002BL low power boot block
flash memory family is a very low power and very
high performance 2-Mbit (2,097,152 bit) memory
family organized as either 128 Kwords (131,072
words) of 16 bits each or 256 Kbytes (262,144
bytes) of 8 bits each.

Five Separately Erasable Blocks including a Hard­ware-Lockable boot block (16,384 Bytes), two pa­rameter blocks (8,192 Bytes each) and two main
blocks (1 block of 98,304 Bytes and 1 block of

131,072 Bytes) are included on the 2-Mbit family. An
erase operation erases one of the 5 blocks in typi­cally 3.4 seconds and the boot or parameter blocks
in typically 2.0 seconds, independent of the remain­ing blocks. Each block can be independently erased
and programmed 10,000 times.

The Boot Block is located at either the top
(28F200BL-T, 28F002BL-T) or the bottom
(28F200BL-B, 28F002BL-B) of the address map in
order to accommodate different microprocessor pro­tocols for boot code location. The hardware locka-
ble boot block provides the most secure code stor­age. The boot block is intended to store the kernel
code required for booting-up a system. When the

Ý

RP

pin is between 11.4V and 12.6V the boot block
is unlocked and program and erase operations can
be performed. When the RP
the boot block is locked and program and erase op­erations to the boot block are ignored.

The 28F200BL products are available in the
ROM/EPROM compatible pinout and housed in the
44-Lead PSOP (Plastic Small Outline) package and
the 56-Lead TSOP (Thin Small Outline, 1.2 mm
thick) package as shown in Figures 3 and 4. The
28F002BL products are available in the 40-Lead
TSOP (1.2 mm thick) package as shown in Figure 5.

The Command User Interface (CUI) serves as the
interface between the microprocessor or microcon­troller and the internal operation of the 28F200BL
and 28F002BL flash memory products.

Ý

pin is at or below 4.1V

3

28F200BL-T/B, 28F002BL-T/B

Program and Erase Automation allow program

and erase operations to be executed using a two­write command sequence to the CUI. The internal
Write State Machine (WSM) automatically executes
the algorithms and timings necessary for program
and erase operations, including verifications, there­by unburdening the microprocessor or microcontrol­ler. Writing of memory data is performed in word or
byte increments for the 28F200BL family and in byte
increments for the 28F002BL family typically within
11 ms.

The Status Register (SR) indicates the status of the
WSM and whether the WSM successfully completed
the desired program or erase operation.

Maximum Access Time of 150 ns (t
over the commercial temperature range (0

a

70§C), over VCCsupply voltage range (3.0V to

) is achieved

ACC

Cto

§

3.6V, 4.5V to 5.5V) and 50 pF output load.

I

Program current is 40 mA for x16 operation

PP

and 30 mA for x8 operation. I
30 mA maximum. V
voltage is 11.4V to 12.6V (V

erase and programming

PP

der all operating conditions.

Typical I

for the x16 products and the x8 products.

Active Current of 15 mA is achieved

CC

Erase current is

PP

e

12Vg5%) un-

PP

The 2-Mbit flash family is also designed with an Au­tomatic Power Savings (APS) feature to minimize
system battery current drain and allow for extremely
low power designs. Once the device is accessed to
read the array data, APS mode will immediately put
the memory in static mode of operation where I
active current is typically 0.8 mA until the next read

CC

is initiated.

When the CE
BYTE
the CMOS Standby mode is enabled where I
typically 40 mA.

Ý

Ý

pin (28F200BL-only) is at either VCCor GND

and RPÝpins are at VCCand the

CC

A Deep Power-down Mode is enabled when the
RPÝpin is at ground minimizing power consumption
and providing write protection during power-up con­ditions. I
is 0.20 mA typical. An initial maximum access time

current during deep power-down mode

CC

or Reset Time of 600 ns is required from RP
switching until outputs are valid. Equivalently, the
device has a maximum wake-up time of 1 ms until
writes to the Command User Interface are recog­nized. When RP

Ý

is at ground the WSM is reset, the
Status Register is cleared and the entire device is
protected from being written to. This feature pre­vents data corruption and protects the code stored
in the device during system reset. The system Reset
pin can be tied to RP

Ý

to reset the memory to nor-

mal read mode upon activation of the Reset pin.
When the CPU enters reset mode, it expects to read
the contents of a memory location. Furthermore,
with on-chip program/erase automation in the

Ý

2-Mbit family and the RP

functionality for data pro­tection, after the CPU is reset and even if a program
or erase command is issued, the device will not rec­ognize any operation until RP

Ý

returns to its normal

state.

For the 28F200BL, Byte-wide or Word-wide In­put/Output Control is possible by controlling the

Ý

BYTE

pin. When the BYTEÝpin is at a logic low
the device is in the byte-wide mode (x8) and data is
read and written through DQ[0:7]. During the byte­wide mode, DQ[8:14]are tri-stated and DQ
becomes the lowest order address pin. When the

Ý

BYTE

pin is at a logic high the device is in the
word-wide mode (x16) and data is read and written
through DQ[0:15].

1.3 Applications

The 2-Mbit low power boot block flash memory fami­ly combines high density, 3V operation, high per­formance, cost-effective flash memories with block­ing and hardware protection capabilities. Its flexibility
and versatility will reduce costs throughout the prod­uct life cycle. Flash memory is ideal for Just-In-Time
production flow, reducing system inventory and
costs, and eliminating component handling during
the production phase. During the product life cycle,
when code updates or feature enhancements be­come necessary, flash memory will reduce the up­date costs by allowing either a user-performed code
change via floppy disk or a remote code change via
a serial link. The 2-Mbit boot block flash memory
family provides full function, blocked flash memories
suitable for a wide range of applications. These ap­plications include Extended PC BIOS, Handy Digi-
tal Cellular Phone program and data storage and

is

various other portable embedded applications where
both program and data storage are required.

Reprogrammable systems such as Notebook and
Palmtop computers, are ideal applications for the
2-Mbit low power flash products. Portable and han­dheld personal computer applications are becoming
more complex with the addition of power manage-

Ý

ment software to take advantage of the latest micro­processor technology, the availability of ROM-based
application software, pen tablet code for electronic
handwriting, and diagnostic code. Figure 1 shows an
example of a 28F200BL-T application.

This increase in software sophistication augments
the probability that a code update will be required
after the PC is shipped. The 2-Mbit low power flash
memory products provide an inexpensive update so-

/A

b

15

1

4

28F200BL-T/B, 28F002BL-T/B

lution for the notebook and handheld personal com­puters while extending their product lifetime. Fur­thermore, the 2-Mbit flash memory products’ deep
power-down mode provides added flexibility for
these battery-operated portable designs which re­quire operation at extremely low power levels.

The 2-Mbit low power flash products also provide
excellent design solutions for Handy Digital Cellular
Phone applications requiring high density storage,
high performance capabilities coupled with low volt­age operation, and a small form factor package (x8­only bus). The 2-Mbit’s blocking scheme allows for
an easy segmentation of the embedded code with:
16 Kbytes of Hardware-Protected Boot code, 2 Main

Blocks of program code and 2 Parameter Blocks of
8 Kbytes each for frequently updatable data storage
and diagnostic messages (e.g., phone numbers, au­thorization codes). Figure 2 is an example of such an
application with the 28F002BL-T.

These are a few actual examples of the wide range
of applications for the 2-Mbit Low Power Boot Block
flash memory family which enables system design­ers to achieve the best possible product design.
Only your imagination limits the applicability of such
a versatile low power product family.

290449– 6

Figure 1. 28F200BL-T Interface to Intel386TMEX Embedded Processor

290449– 22

Figure 2. 28F002BL-T Interface to INTEL 80L188EB, Low Voltage 8-Bit Embedded Microprocessor

5

28F200BL-T/B, 28F002BL-T/B

1.4 Pinouts

The 28F200BL 44-Lead PSOP pinout follows the in­dustry standard ROM/EPROM pinout as shown in
Figure 3 with an upgrade to the 28F400BL
(4-Mbit low power flash family). Furthermore,
the 28F200BL 56-Lead TSOP pinout shown in

Figure 4 provides density upgrades to the 28F400BL
and to future higher density boot block memories.

The 28F002BL 40-Lead TSOP pinout shown in Fig­ure 5 is 100% compatible and has a density up­grade to the 28F004BL 4-Mbit Low Power Boot
Block flash memory.

290449– 24

Figure 3. PSOP Lead Configuration for x8/x16 28F200BL

6

28F200BL-T/B, 28F002BL-T/B

Figure 4. TSOP Lead Configuration for x8/x16 28F200BL

Figure 5. TSOP Lead Configuration for x8 28F002BL

290449– 4

290449– 5

7

28F200BL-T/B, 28F002BL-T/B

1.5 Pin Descriptions for x8/x16 28F200BL

Symbol Type Name and Function

A0–A

16

A

9

DQ0–DQ

DQ8–DQ

Ý

CE

Ý

RP

Ý

OE

Ý

WE

I ADDRESS INPUTS for memory addresses. Addresses are internally latched

during a write cycle.

I ADDRESS INPUT: When A9is at 12V the signature mode is accessed. During this

mode A
a logic low only the lower byte of the signatures are read. DQ

decodes between the manufacturer and device ID’s. When BYTEÝis at

0

care in the signature mode when BYTEÝis low.

I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle

7

during a program command. Inputs commands to the command user interface
when CE

Ý

and WEÝare active. Data is internally latched during the write and
program cycles. Outputs array, Intelligent Identifier and Status Register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.

I/O DATA INPUT/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle

15

during a program command. Data is internally latched during the write and program
cycles. Outputs array data. The data pins float to tri-state when the chip is
deselected or the outputs are disabled as in the byte-wide mode (BYTE

/A

In the byte-wide mode DQ
output on DQ

-DQ7.

0

becomes the lowest order address for data

b

15

1

I CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

sense amplifiers. CE

Ý

is active low; CEÝhigh deselects the memory device and
reduces power consumption to standby levels. If CEÝand RPÝare high, but not
at a CMOS high level, the standby current will increase due to current flow through

Ý

the CE

and RPÝinput stages.

I RESET/DEEP POWER-DOWN: Provides Three-State control. Puts the device in

deep power-down mode. Locks the boot block from program/erase.

When RP

Ý

is at logic high level and equals 4.1V maximum the boot block is

locked and cannot be programmed or erased.

e

When RP

Ý

11.4V minimum the boot block is unlocked and can be programmed

or erased.

When RP

Ý

is at a logic low level the boot block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RP

Ý

transitions from logic low to logic high, the flash memory

enters the read-array mode.

I OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

read cycle. OE

Ý

is active low.

I WRITE ENABLE: Controls writes to the Command Register and array blocks.

Ý

WE

is active low. Addresses and data are latched on the rising edge of the WE

pulse.

/A

is a don’t

b

15

1

e

Ý

‘‘0’’).

Ý

8

28F200BL-T/B, 28F002BL-T/B

1.5 Pin Descriptions for x8/x16 28F200BL (Continued)

Symbol Type Name and Function

Ý

BYTE

V

PP

V

CC

GND GROUND: For all internal circuitry.

NC NO CONNECT: Pin may be driven or left floating.

DU DON’T USE PIN: Pin should not be connected to anything.

I BYTEÝENABLE: Controls whether the device operates in the byte-wide mode (x8) or

the word-wide mode (x16). BYTE
read and programmed on DQ
address that decodes between the upper and lower byte. DQ
during the byte-wide mode. BYTE
read and programmed on DQ

e

Ý

‘‘0’’ enables the byte-wide mode, where data is

–DQ7and DQ15/A

0

e

Ý

‘‘1’’ enables the word-wide mode where data is

–DQ15.

0

b

1

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.

PP

k

V

PPLMAX

memory contents cannot be altered.

Note: V

DEVICE POWER SUPPLY (3.3Vg0.3V, 5Vg10%)

becomes the lowest order

–DQ14are tri-stated

8

9

28F200BL-T/B, 28F002BL-T/B

1.6 Pin Descriptions for x8 28F002BL

Symbol Type Name and Function

A0–A

17

A

9

DQ0–DQ7I/O DATA INPUTS/OUTPUTS: Inputs array data on the second CEÝand WEÝcycle

Ý

CE

Ý

RP

Ý

OE

Ý

WE

V

PP

V

CC

GND GROUND: For all internal circuitry

NC NO CONNECT: Pin may be driven or left floating

DU DON’T USE PIN: Pin should not be connected to anything

I ADDRESS INPUTS for memory addresses. Addresses are internally latched during

a write cycle.

I ADDRESS INPUT: When A9is at 12V the signature mode is accessed. During this

mode A

decodes between the manufacturer and device ID’s.

0

during a program command. Inputs commands to the command user interface

Ý

when CE

and WEÝare active. Data is internally latched during the write and
program cycles. Outputs array Intelligent Identifier and status register data. The
data pins float to tri-state when the chip is deselected or the outputs are disabled.

I CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and

Ý

sense amplifiers. CE

is active low; CEÝhigh deselects the memory device and

reduces power consumption to standby levels.

I RESET/DEEP POWER-DOWN: Provides Three-State control. Puts the device in

deep power-down mode. Locks the Boot Block from program/erase.

When RP

Ý

is at logic high level and equals 4.1V maximum the Boot Block is locked

and cannot be programmed or erased.

e

Ý

When RP

11.4V minimum the Boot Block is unlocked and can be programmed

or erased.

When RPÝis at a logic low level the Boot Block is locked, the deep power-down
mode is enabled and the WSM is reset preventing any blocks from being
programmed or erased, therefore providing data protection during power
transitions. When RP

Ý

transitions from logic low to logic high, the flash memory

enters the read-array mode.

I OUTPUT ENABLE: Gates the device’s outputs through the data buffers during a

Ý

read cycle. OE

is active low.

I WRITE ENABLE: Controls writes to the Command Register and array blocks. WE

is active low. Addresses and data are latched on the rising edge of the WEÝpulse.

PROGRAM/ERASE POWER SUPPLY: For erasing memory array blocks or
programming data in each block.

PP

k

V

PPLMAX

memory contents cannot be altered.

Note: V

DEVICE POWER SUPPLY (3.3Vg0.3V, 5Vg10%)

Ý

10

2.0 28F200BL PRODUCTS DESCRIPTION

28F200BL-T/B, 28F002BL-T/B

290449– 1

Figure 6. 28F200BL Word/Byte-Wide Block Diagram

11

28F200BL-T/B, 28F002BL-T/B

2.1 28F200BL Memory Organization

2.1.1 BLOCKlNG

The 28F200BL uses a blocked array architecture to
provide independent erasure of memory blocks. A
block is erased independently of other blocks in the
array when an address is given within the block ad­dress range and the Erase Setup and Erase Confirm
commands are written to the CUI. The 28F200BL is
a random read/write memory, only erasure is per­formed by block.

2.1.1.1 Boot Block Operation and Data
Protection

The 16-Kbyte boot block provides a lock feature for
secure code storage. The intent of the boot block is
to provide a secure storage area for the kernel code
that is required to boot a system in the event of pow­er failure or other disruption during code update.
This lock feature ensures absolute data integrity by
preventing the boot block from being written or
erased when RP
be erased and written when RP
the duration of the erase or program operation. This
allows customers to change the boot code when
necessary while providing security when needed.
See the Block Memory Map section for address lo­cations of the boot block for the 28F200BL-T and
28F200BL-B.

Ý

is not at 12V. The boot block can

Ý

is held at 12V for

2.1.1.3 Main Block Operation

Two main blocks of memory exist on the 28F200BL
(1 x 128-Kbyte block and 1 x 96-Kbyte blocks). See
the following section on Block Memory Map for the
address location of these blocks for the 28F200BL-T
and 28F200BL-B products.

2.1.2 BLOCK MEMORY MAP

Two versions of the 28F200BL product exist to sup­port two different memory maps of the array blocks
in order to accommodate different micropro- cessor
protocols for boot code location. The 28F200BL-T
memory map is inverted from the 28F200BL-B mem­ory map.

2.1.2.1 28F200BL-B Memory Map

The 28F200BL-B device has the 16-Kbyte boot
block located from 00000H to 01FFFH to accom­modate those microprocessors that boot from the
bottom of the address map at 00000H. In the
28F200BL-B the first 8-Kbyte parameter block re­sides in memory space from 02000H to 02FFFH.
The second 8-Kbyte parameter block resides in
memory space from 03000H to 03FFFH. The
96-Kbyte main block resides in memory space from
04000H to 0FFFFH. The 128-Kbyte main block re­sides in memory space from 10000H to 1FFFFH
(word locations). See Figure 7.

2.1.1.2 Parameter Block Operation

The 28F200BL has 2 parameter blocks (8 Kbytes
each). The parameter blocks are intended to pro­vide storage for frequently updated system parame­ters and configuration or diagnostic information. The
parameter blocks can also be used to store addition­al boot or main code. The parameter blocks howev­er, do not have the hardware write protection feature
that the boot block has. The parameter blocks pro­vide for more efficient memory utilization when deal­ing with parameter changes versus regularly blocked
devices. See the Block Memory Map section for ad­dress locations of the parameter blocks for the
28F200BL-T and 28F200BL-B.

12

(Word Addresses)

1FFFFH

128-Kbyte MAIN BLOCK

10000H

0FFFFH

96-Kbyte MAIN BLOCK

04000H
03FFFH

03000H
02FFFH

02000H
01FFFH

00000H

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

16-Kbyte BOOT BLOCK

Figure 7. 28F200BL-B Memory Map

28F200BL-T/B, 28F002BL-T/B

2.1.2.2 28F200BL-T Memory Map

The 28F200BL-T device has the 16-Kbyte boot
block located from 1E000H to 1FFFFH to accommo­date those microprocessors that boot from the top
of the address map. In the 28F200BL-T the first
8-Kbyte parameter block resides in memory space
from 1D000H to 1DFFFH. The second 8-Kbyte pa­rameter block resides in memory space from
1C000H to 1CFFFH. The 96-Kbyte main block re­sides in memory space from 10000H to 1BFFFH.
The 128-Kbyte main block resides in memory space
from 00000H to 0FFFFH as shown below in Figure

8.

(Word Addresses)

1FFFFH

1E000H

1DFFFH

1D000H

1CFFFH

1C000H

1BFFFH

10000H

0FFFFH

00000H

16-Kbyte BOOT BLOCK

8-Kbyte PARAMETER BLOCK

8-Kbyte PARAMETER BLOCK

96-Kbyte MAIN BLOCK

128-Kbyte MAIN BLOCK

Figure 8. 28F200BL-T Memory Map

13