Intel Corporation NG80960KA-16, NG80960KA-25 Datasheet
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. May 1993
© INTEL CORPORATION, 1993 Order Number: 270775-005
80960KA
EMBEDDED 32-BIT MICROPROCESSOR
The 80960KA is a member of Intel’s i960® 32-bit processor family, which is designed especially for embedded
applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960KA has a large
register set, multiple parallel execution units and a high-bandwidth burst bus. Using advanced RISC technology,
this high performance processor is capable of execution rates in excess of 9.4 million instructions per second
*
.
The 80960KA is well-suited for a wide range of applications including non-impact printers, I/O control and
specialty instrumentation.
Figure 1. The 80960KA Processor’s Highly Parallel Architecture
* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment
Corporation)
■ High-Performance Embedded Architecture
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at 25 MHz
■ 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached Instruc-
tions
■ Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored On-Chip
— Register Scoreboarding
■ 4 Gigabyte, Linear Address Space
■ Pin Compatible with 80960KB
■ Built-in Interrupt Controller
— 31 Priority Levels, 256 Vectors
— 3.4 µs Latency @ 25 MHz
■ Easy to Use, High Bandwidth 32-Bit Bus
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
■ 132-Lead Packages:
— Pin Grid Array (PGA)
— Plastic Quad Flat-Pack (PQFP)
SIXTEEN
32-BIT GLOBAL
REGISTERS
64- BY 32-BIT
LOCAL
REGISTER
CACHE
32-BIT
INSTRUCTION
EXECUTION
UNIT
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS
CONTROL
LOGIC
32-BIT
BURST
BUS
ii
1.0 THE i960® PROCESSOR ................................ 1
1.1. Key Performance Features .......................... 2
1.1.1. Memory Space And Addressing Modes . 4
1.1.2. Data Types ............................................. 4
1.1.3. Large Register Set ................................. 4
1.1.4. Multiple Register Sets ............................ 5
1.1.5. Instruction Cache ................................... 5
1.1.6. Register Scoreboarding ......................... 5
1.1.7. High Bandwidth Local Bus ..................... 6
1.1.8. Interrupt Handling ................................... 6
1.1.9. Debug Features ..................................... 6
1.1.10. Fault Detection ..................................... 7
1.1.11. Built-in Testability ................................. 7
1.1.12. CHMOS ................................................ 7
2.0 ELECTRICAL SPECIFICATIONS .................. 10
2.1. Power and Grounding ................................ 10
2.2. Power Decoupling Recommendations ....... 10
2.3. Connection Recommendations .................. 11
2.4. Characteristic Curves ................................. 11
2.5. Test Load Circuit ........................................ 14
2.6. Absolute Maximum Ratings ....................... 15
2.7. DC Characteristics ..................................... 15
2.8. AC Specifications ....................................... 16
2.8.1. AC Specification Tables ....................... 17
3.0 MECHANICAL DATA ..................................... 21
3.1. Packaging .................................................. 21
3.1.1. Pin Assignment .................................... 21
3.2. Pinout ......................................................... 25
3.3. Package Thermal Specification ................. 29
4.0. WAVEFORMS ............................................... 33
5.0. REVISION HISTORY ..................................... 38
FIGURES
Figure 1. The 80960KA Processor’s Highly
Parallel Architecture ............................ i
Figure 2. 80960KA Programming
Environment ........................................ 1
Figure 3. Instruction Formats ............................. 4
Figure 4. Multiple Register Sets Are Stored
On-Chip ...............................................6
Figure 5. Connection Recommendations
for Low Current Drive Network ..........11
Figure 6. Connection Recommendations
for High Current Drive Network ......... 11
Figure 7. Typical Supply Current vs.
Case Temperature ............................12
Figure 8. Typical Current vs. Frequency
(Room Temp) .................................... 12
Figure 9. Typical Current vs. Frequency
(Hot Temp) ........................................ 13
Figure 10. Worst-Case Voltage vs. Output
Current on Open-Drain Pins .............. 13
Figure 11. Capacitive Derating Curve ................13
Figure 12. Test Load Circuit for Three-State
Output Pins ......................................14
Figure 13. Test Load Circuit for Open-Drain
Output Pins ......................................14
Figure 14. Drive Levels and Timing Relationships
for 80960KA Signals ......................... 16
Figure 15. Processor Clock Pulse (CLK2) .......... 20
Figure 16. RESET Signal Timing ....................... 20
Figure 17. 32-Lead Pin-Grid Array
(PGA) Package .................................21
Figure 18. 80960KA PGA Pinout—View from
Bottom (Pins Facing Up) ................... 22
Figure 19. 80960KA PGA Pinout—View from
Top (Pins Facing Down) ....................23
Figure 20. 80960KA 132-Lead Plastic Quad
Flat-Pack (PQFP) Package ...............23
Figure 21. PQFP Pinout - View From Top .......... 24
Figure 22. HOLD Timing .................................... 30
Figure 23. 16 MHz Maximum Allowable
Ambient Temperature ....................... 31
80960KA
EMBEDDED 32-BIT MICROPROCESSOR
CONTENTS
iii
Figure 24. 20 MHz Maximum Allowable
Ambient Temperature ....................... 31
Figure 25. 25 MHz Maximum Allowable
Ambient Temperature ....................... 32
Figure 26. Maximum Allowable Ambient
Temperature for the Extended
Temperature TA-80960KA at
20 MHz in PGA Package .................. 32
Figure 27. Non-Burst Read and Write
Transactions Without Wait States ..... 33
Figure 28. Burst Read and Write Transaction
Without Wait States ......................... 34
Figure 29. Burst Write Transaction with
2, 1, 1, 1 Wait States ........................ 35
Figure 30. Accesses Generated by Quad Word
Read Bus Request, Misaligned Two
Bytes from Quad Word Boundary
(1, 0, 0, 0 Wait States) ...................... 36
Figure 31. Interrupt Acknowledge Transaction .. 37
TABLES
Table 1. 80960KA Instruction Set .....................3
Table 2. Memory Addressing Modes ................ 4
Table 3. 80960KA Pin Description:
L-Bus Signals ...................................... 8
Table 4. 80960KA Pin Description:
Support Signals ...................................9
Table 5. DC Characteristics ............................15
Table 6. 80960KA AC Characteristics
(16 MHz) ........................................... 17
Table 7. 80960KA AC Characteristics
(20 MHz) ........................................... 18
Table 8. 80960KA AC Characteristics
(25 MHz) ........................................... 19
Table 9. 80960KA PGA Pinout —
In Pin Order .......................................25
Table 10. 80960KA PGA Pinout —
In Signal Order .................................. 26
Table 11. 80960KA PQFP Pinout —
In Pin Order .......................................27
Table 12. 80960KA PQFP Pinout —
In Signal Order .................................. 28
Table 13. 80960KA PGA Package
Thermal Characteristics ....................29
Table 14. 80960KA PQFP Package
Thermal Characteristics ....................30
80960KA
1
1.0 THE i960® PROCESSOR
The 80960KA is a member of the 32-bit architecture
from Intel known as the i960 processor family. These
were especially designed to serve the needs of
embedded applications. The embedded market
includes applications as diverse as industrial
automation, avionics, image processing, graphics and
networking. These types of applications require high
integration, low power consumption, quick interrupt
response times and high performance. Since time to
market is critical, embedded microprocessors need to
be easy to use in both hardware and software
designs.
All members of the i960 processor family share a
common core architecture which utilizes RISC
technology so that, except for special functions, the
family members are object-code compatible. Each
new processor in the family adds its own special set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.
Software written for the 80960KA will run without
modification on any other member of the 80960
Family. It is also pin-compatible with the 80960KB
which includes an integrated floating-point unit and
the 80960MC which is a military-grade version that
supports multitasking, memory management, multiprocessing and fault tolerance.
Figure 2. 80960KA Programming Environment
INSTRUCTION CACHE
INSTRUCTION
STREAM
FETCH LOAD STORE
SIXTEEN 32-BIT GLOBAL REGISTERS
g0
g15
SIXTEEN 32-BIT LOCAL REGISTERS
REGISTER CACHE
FOUR 80-BIT FLOATING POINT REGISTERS
r0
r15
CONTROL REGISTERS
INSTRUCTION
EXECUTION
INSTRUCTION
POINTER
ARITHMETIC
CONTROLS
PROCESS
CONTROLS
TRACE
CONTROLS
ARCHITECTURALLY
DEFINED
DATA STRUCTURES
FFFF FFFFH0000 0000H
ADDRESS SPACE
PROCESSOR STATE
REGISTERS
80960KA
2
1.1. Key Performance Features
The 80960 architecture is based on the most recent
advances in microprocessor technology and is
grounded in Intel’s long experience in the design and
manufacture of embedded microprocessors. Many
features contribute to the 80960KA’s exceptional
performance:
1. Large Register Set. Having a large number of
registers reduces the number of times that a
processor needs to access memory. Modern
compilers can take advantage of this feature to
optimize execution speed. For maximum flexibility, the
80960KA provides thirty-two 32-bit registers. (See
Figure 2.)
2. Fast Instruction Execution. Simple functions
make up the bulk of instructions in most programs so
that execution speed can be improved by ensuring
that these core instructions are executed as quickly
as possible. The most frequently executed instructions such as register-register moves, add/subtract,
logical operations and shifts execute in one to two
cycles. (Table 1 contains a list of instructions.)
3. Load/Store Architecture. One way to improve
execution speed is to reduce the number of times that
the processor must access memory to perform an
operation. As with other processors based on RISC
technology, the 80960KA has a Load/Store architecture. As such, only the LOAD and STORE instructions reference memory; all other instructions operate
on registers. This type of architecture simplifies
instruction decoding and is used in combination with
other techniques to increase parallelism.
4. Simple Instruction Formats. All instructions in
the 80960KA are 32 bits long and must be aligned on
word boundaries. This alignment makes it possible to
eliminate the instruction alignment stage in the
pipeline. To simplify the instruction decoder, there are
only five instruction formats; each instruction uses
only one format. (See Figure 3.)
5. Overlapped Instruction Execution. Load
operations allow execution of subsequent instructions
to continue before the data has been returned from
memory, so that these instructions can overlap the
load. The 80960KA manages this process transparently to software through the use of a register scoreboard. Conditional instructions also make use of a
scoreboard so that subsequent unrelated instructions
may be executed while the conditional instruction is
pending.
6. Integer Execution Optimization. When the
result of an arithmetic execution is used as an
operand in a subsequent calculation, the value is sent
immediately to its destination register. Yet at the same
time, the value is put on a bypass path to the ALU,
thereby saving the time that otherwise would be
required to retrieve the value for the next operation.
7. Bandwidth Optimizations. The 80960KA gets
optimal use of its memory bus bandwidth because the
bus is tuned for use with the on-chip instruction
cache: instruction cache line size matches the
maximum burst size for instruction fetches. The
80960KB automatically fetches four words in a burst
and stores them directly in the cache. Due to the size
of the cache and the fact that it is continually filled in
anticipation of needed instructions in the program
flow, the 80960KA is relatively insensitive to memory
wait states. The benefit is that the 80960KA delivers
outstanding performance even with a low cost
memory system.
8. Cache Bypass. If a cache miss occurs, the
processor fetches the needed instruction then sends
it on to the instruction decoder at the same time it
updates the cache. Thus, no extra time is spent to
load and read the cache.
80960KA
3
Table 1. 80960KA Instruction Set
Data Movement Arithmetic Logical Bit and Bit Field
Load
Store
Move
Load Address
Add
Subtract
Multiply
Divide
Remainder
Modulo
Shift
And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Exclusive Nor
Not
Nand
Rotate
Set Bit
Clear Bit
Not Bit
Check Bit
Alter Bit
Scan For Bit
Scan Over Bit
Extract
Modify
Comparison Branch Call/Return Fault
Compare
Conditional Compare
Compare and Increment
Compare and Decrement
Unconditional Branch
Conditional Branch
Compare and Branch
Call
Call Extended
Call System
Return
Branch and Link
Conditional Fault
Synchronize Faults
Debug Miscellaneous Decimal
Modify Trace Controls
Mark
Force Mark
Atomic Add
Atomic Modify
Flush Local Registers
Modify Arithmetic Controls
Scan Byte for Equal
Test Condition Code
Modify Process Controls
Decimal Move
Decimal Add with Carry
Decimal Subtract with
Carry
Synchronous
Synchronous Load
Synchronous Move
80960KA
4
Figure 3. Instruction Formats
Opcode Displacement
Opcode Reg/Lit Reg M Displacement
Opcode Reg Reg/Lit Modes Ext’d Op Reg/Lit
Opcode Reg Base M X Offset
Opcode Reg Base Mode Scale xx Offset
Displacement
Control
Compare and
Branch
Register to
Register
Memory Access—
Short
Memory Access—
Long
1.1.1. Memory Space And Addressing Modes
The 80960KA offers a linear programming environment so that all programs running on the processor
are contained in a single address space. Maximum
address space size is 4 Gigabytes (2
32
bytes).
For ease of use the 80960KA has a small number of
addressing modes, but includes all those necessary
to ensure efficient execution of high-level languages
such as C. Table 2 lists the modes.
Table 2. Memory Addressing Modes
• 12-Bit Offset
• 32-Bit Offset
• Register-Indirect
• Register + 12-Bit Offset
• Register + 32-Bit Offset
• Register + (Index-Register x Scale-Factor)
• Register x Scale Factor + 32-Bit Displacement
• Register + (Index-Register x Scale-Factor) +
32-Bit Displacement
• Scale-Factor is 1, 2, 4, 8 or 16
1.1.2. Data Types
The 80960KA recognizes the following data types:
Numeric:
• 8-, 16-, 32- and 64-bit ordinals
• 8-, 16-, 32- and 64-bit integers
Non-Numeric:
• Bit
• Bit Field
• Triple Word (96 bits)
• Quad-Word (128 bits)
1.1.3. Large Register Set
The 80960KA programming environment includes a
large number of registers. In fact, 32 registers are
available at any time. The availability of this many
registers greatly reduces the number of memory
accesses required to perform algorithms, which leads
to greater instruction processing speed.
There are two types of general-purpose registers:
local and global. The global registers consist of
sixteen 32-bit registers (G0 though G15). These
registers perform the same function as the general-
80960KA
5
purpose registers provided in other popular microprocessors. The term global refers to the fact that these
registers retain their contents across procedure calls.
The local registers, on the other hand, are procedure
specific. For each procedure call, the 80960KA
allocates 16 local registers (R0 through R15). Each
local register is 32 bits wide.
1.1.4. Multiple Register Sets
To further increase the efficiency of the register set,
multiple sets of local registers are stored on-chip (See
Figure 4). This cache holds up to four local register
frames, which means that up to three procedure calls
can be made without having to access the procedure
stack resident in memory.
Although programs may have procedure calls nested
many calls deep, a program typically oscillates back
and forth between only two to three levels. As a
result, with four stack frames in the cache, the probability of having a free frame available on the cache
when a call is made is very high. In fact, runs of representative C-language programs show that 80% of the
calls are handled without needing to access memory.
If four or more procedures are active and a new
procedure is called, the 80960KA moves the oldest
local register set in the stack-frame cache to a
procedure stack in memory to make room for a new
set of registers. Global register G15 is the frame
pointer (FP) to the procedure stack.
Global registers are not exchanged on a procedure
call, but retain their contents, making them available
to all procedures for fast parameter passing.
1.1.5. Instruction Cache
To further reduce memory accesses, the 80960KA
includes a 512-byte on-chip instruction cache. The
instruction cache is based on the concept of locality
of reference; most programs are not usually executed
in a steady stream but consist of many branches,
loops and procedure calls that lead to jumping back
and forth in the same small section of code. Thus, by
maintaining a block of instructions in cache, the
number of memory references required to read
instructions into the processor is greatly reduced.
To load the instruction cache, instructions are fetched
in 16-byte blocks; up to four instructions can be
fetched at one time. An efficient prefetch algorithm
increases the probability that an instruction will
already be in the cache when it is needed.
Code for small loops often fits entirely within the
cache, leading to a great increase in processing
speed since further memory references might not be
necessary until the program exits the loop. Similarly,
when calling short procedures, the code for the
calling procedure is likely to remain in the cache so it
will be there on the procedure’s return.
1.1.6. Register Scoreboarding
The instruction decoder is optimized in several ways.
One optimization method is the ability to overlap
instructions by using register scoreboarding.
Register scoreboarding occurs when a LOAD moves
a variable from memory into a register. When the
instruction initiates, a scoreboard bit on the target
register is set. Once the register is loaded, the bit is
reset. In between, any reference to the register
contents is accompanied by a test of the scoreboard
bit to ensure that the load has completed before
processing continues. Since the processor does not
need to wait for the LOAD to complete, it can execute
additional instructions placed between the LOAD and
the instruction that uses the register contents, as
shown in the following example:
ld data_2, r4
ld data_2, r5
Unrelated instruction
Unrelated instruction
add R4, R5, R6
In essence, the two unrelated instructions between
LOAD and ADD are executed “for free” (i.e., take no
apparent time to execute) because they are executed
while the register is being loaded. Up to three load
instructions can be pending at one time with three
corresponding scoreboard bits set. By exploiting this
feature, system programmers and compiler writers
have a useful tool for optimizing execution speed.
80960KA
6
Figure 4. Multiple Register Sets Are Stored On-Chip
REGISTER
CACHE
ONE OF FOUR
LOCAL
REGISTER SETS
LOCAL REGISTER SET
R
15
R
0
31
0
1.1.7. High Bandwidth Local Bus
The 80960KA CPU resides on a high-bandwidth
address/data bus known as the local bus (L-Bus). The
L-Bus provides a direct communication path between
the processor and the memory and I/O subsystem
interfaces. The processor uses the L-Bus to fetch
instructions, manipulate memory and respond to
interrupts. L-Bus features include:
• 32-bit multiplexed address/data path
• Four-word burst capability which allows transfers
from 1 to 16 bytes at a time
• High bandwidth reads and writes with
66.7 MBytes/s burst (at 25 MHz)
Table 3 defines L-bus signal names and functions;
Table 4 defines other component-support signals
such as interrupt lines.
1.1.8. Interrupt Handling
The 80960KA can be interrupted in two ways: by the
activation of one of four interrupt pins or by sending a
message on the processor’s data bus.
The 80960KA is unusual in that it automatically
handles interrupts on a priority basis and can keep
track of pending interrupts through its on-chip
interrupt controller. Two of the interrupt pins can be
configured to provide 8259A-style handshaking for
expansion beyond four interrupt lines.
1.1.9. Debug Features
The 80960KA has built-in debug capabilities. There
are two types of breakpoints and six trace modes.
Debug features are controlled by two internal 32-bit
registers: the Process-Controls Word and the TraceControls Word. By setting bits in these control words,
a software debug monitor can closely control how the
processor responds during program execution.
The 80960KA provides two hardware breakpoint
registers on-chip which, by using a special command,
can be set to any value. When the instruction pointer
matches either breakpoint register value, the
breakpoint handling routine is automatically called.
The 80960KA also provides software breakpoints
through the use of two instructions: MARK and
FMARK. These can be placed at any point in a
program and cause the processor to halt execution at
that point and call the breakpoint handling routine.
The breakpoint mechanism is easy to use and
provides a powerful debugging tool.
Tracing is available for instructions (single step
execution), calls and returns and branching. Each
trace type may be enabled separately by a special
80960KA
7
debug instruction. In each case, the 80960KA
executes the instruction first and then calls a trace
handling routine (usually part of a software debug
monitor). Further program execution is halted until the
routine completes, at which time execution resumes
at the next instruction. The 80960KA’s tracing
mechanisms, implemented completely in hardware,
greatly simplify the task of software test and debug.
1.1.10. Fault Detection
The 80960KA has an automatic mechanism to handle
faults. Fault types include trace and arithmetic faults.
When the processor detects a fault, it automatically
calls the appropriate fault handling routine and saves
the current instruction pointer and necessary state
information to make efficient recovery possible. Like
interrupt handling routines, fault handling routines are
usually written to meet the needs of specific applications and are often included as part of the operating
system or kernel.
For each of the fault types, there are numerous
subtypes that provide specific information about a
fault. The fault handler can use this specific information to respond correctly to the fault.
1.1.11. Built-in Testability
Upon reset, the 80960KA automatically conducts an
exhaustive internal test of its major blocks of logic.
Then, before executing its first instruction, it does a
zero check sum on the first eight words in memory to
ensure that the memory image was programmed
correctly. If a problem is discovered at any point
during the self-test, the 80960KA asserts its FAILURE
pin and will not begin program execution. Self test
takes approximately 47,000 cycles to complete.
System manufacturers can use the 80960KA’s selftest feature during incoming parts inspection. No
special diagnostic programs need to be written. The
test is both thorough and fast. The self-test capability
helps ensure that defective parts are discovered
before systems are shipped and, once in the field, the
self-test makes it easier to distinguish between
problems caused by processor failure and problems
resulting from other causes.
1.1.12. CHMOS
The 80960KA is fabricated using Intel’s CHMOS IV
(Complementary High Speed Metal Oxide Semiconductor) process. The 80960KA is currently available
in 16, 20 and 25 MHz versions.
80960KA
8
Table 3. 80960KA Pin Description: L-Bus Signals (Sheet 1 of 2)
NAME TYPE DESCRIPTION
CLK2 I SYSTEM CLOCK provides the fundamental timing for 80960KA systems. It is divided
by two inside the 80960KA to generate the internal processor clock.
LAD31:0 I/O
T.S.
LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to and
from memory. During an address (T
a
) cycle, bits 2-31 contain a physical word
address (bits 0-1 indicate SIZE; see below). During a data (T
d
) cycle, bits 0-31
contain read or write data. These pins float to a high impedance state when not
active.
Bits 0-1 comprise SIZE during a T
a
cycle. SIZE specifies burst transfer size in words.
LAD1 LAD0
0 0 1 Word
0 1 2 Words
1 0 3 Words
1 1 4 Words
ALE
O
T.S.
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a T
a
cycle and deasserted before the beginning of the Td state. It is
active LOW and floats to a high impedance state during a hold cycle (T
h
).
ADS
O
O.D.
ADDRESS/DATA STATUS indicates an address state. ADS is asserted every T
a
state and deasserted during the following Td state. For a burst transaction, ADS is
asserted again every T
d
state where READY was asserted in the previous cycle.
W/R
O
O.D.
WRITE/READ specifies, during a Ta cycle, whether the operation is a write or read. It
is latched on-chip and remains valid during T
d
cycles.
DT/R
O
O.D.
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the
L-Bus. It is low during T
a
and Td cycles for a read or interrupt acknowledgment; it is
high during T
a
and Td cycles for a write. DT/R never changes state when DEN is
asserted.
READY
I READY indicates that data on LAD lines can be sampled or removed. IfREADY is not
asserted during a T
d
cycle, the Td cycle is extended to the next cycle by inserting a
wait state (T
w
) and ADS is not asserted in the next cycle.
LOCK
I/O
O.D.
BUS LOCK prevents bus masters from gaining control of the L-Bus during
Read/Modify/Write (RMW) cycles. The processor or any bus agent may assert
LOCK
.
At the start of a RMW operation, the processor examines the LOCK
pin. If the pin is
already asserted, the processor waits until it is not asserted. If the pin is not asserted,
the processor asserts LOCK
during the Ta cycle of the read transaction. The
processor deasserts LOCK
in the Ta cycle of the write transaction. During the time
LOCK
is asserted, a bus agent can perform a normal read or write but not a RMW
operation.
The processor also asserts LOCK
during interrupt-acknowledge transactions.
Do not leave LOCK
unconnected. It must be pulled high for the processor to function
properly.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
80960KA
9
BE3:0 O
O.D.
BYTE ENABLE LINES specify the data bytes (up to four) on the bus which are used
in the current bus cycle. BE3
corresponds to LAD31:24; BE0 corresponds to LAD7:0.
The byte enables are provided in advance of data:
• Byte enables asserted during T
a
specify the bytes of the first data word.
• Byte enables asserted during T
d
specify the bytes of the next data word, if any (the
word to be transmitted following the next assertion of READY
).
Byte enables that occur during T
d
cycles that precede the last assertion of READY
are undefined. Byte enables are latched on-chip and remain constant from one T
d
cycle to the next when READY is not asserted.
For reads, byte enables specify the byte(s) that the processor will actually use. L-Bus
agents are required to assert only adjacent byte enables (e.g., asserting just BE0
and
BE2
is not permitted) and are required to assert at least one byte enable. Address
bits A
0
and A1 can be decoded externally from the byte enables.
HOLD I HOLD: A request from an external bus master to acquire the bus. When the
processor receives HOLD and grants bus control to another master, it floats its threestate bus lines and open-drain control lines, asserts HLDA and enters the T
h
state.
When HOLD deasserts, the processor deasserts HLDA and enters the T
i
or Ta state.
HLDA O
T.S.
HOLD ACKNOWLEDGE: Notifies an external bus master that the processor has
relinquished control of the bus.
CACHE O
T.S.
CACHE indicates when an access is cacheable during a T
a
cycle. It is not asserted
during any synchronous access, such as a synchronous load or move instruction
used for sending an IAC message. The CACHE signal floats to a high impedance
state when the processor is idle.
Table 4. 80960KA Pin Description: Support Signals (Sheet 1 of 2)
NAME TYPE DESCRIPTION
BADAC
I BAD ACCESS, if asserted in the cycle following the one in which the lastREADY of a
transaction is asserted, indicates an unrecoverable error occurred on the current bus
transaction or a synchronous load/store instruction has not been acknowledged.
During system reset the BADAC
signal is interpreted differently. If the signal is high, it
indicates that this processor will perform system initialization. If it is low, another
processor in the system will perform system initialization instead.
RESET I RESET clears the processor’s internal logic and causes it to reinitialize.
During RESET assertion, the input pins are ignored (except for BADAC
and
IAC
/INT0), the three-state output pins are placed in a high impedance state and other
output pins are placed in their non-asserted states.
RESET must be asserted for at least 41 CLK2 cycles for a predictable RESET. The
HIGH to LOW transition of RESET should occur after the rising edge of both CLK2
and the external bus clock and before the next rising edge of CLK2.
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
Table 3. 80960KA Pin Description: L-Bus Signals (Sheet 2 of 2)
NAME TYPE DESCRIPTION
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
80960KA
10
FAILURE O
O.D.
INITIALIZATION FAILURE indicates that the processor did not initialize correctly.
After RESET deasserts and before the first bus transaction begins, FAILURE
asserts
while the processor performs a self-test. If the self-test completes successfully, then
FAILURE
deasserts. The processor then performs a zero checksum on the first eight
words of memory. If it fails, FAILURE
asserts for a second time and remains
asserted. If it passes, system initialization continues and FAILURE
remains
deasserted.
IAC
/INT
0
I INTERAGENT COMMUNICATION REQUEST/INTERRUPT 0 indicates an IAC
message or an interrupt is pending. The bus interrupt control register determines how
the signal is interpreted. To signal an interrupt or IAC request in a synchronous
system, this pin — as well as the other interrupt pins — must be enabled by being
deasserted for at least one bus cycle and then asserted for at least one additional
bus cycle. In an asynchronous system the pin must remain deasserted for at least
two bus cycles and then asserted for at least two more bus cycles.
During system reset, this signal must be in the logic high condition to enable normal
processor operation. The logic low condition is reserved.
INT
1
I INTERRUPT 1, like INT0, provides direct interrupt signaling.
INT
2
/INTR I INTERRUPT2/INTERRUPT REQUEST: The interrupt control register determines
how this pin is interpreted. If INT
2
, it has the same interpretation as the INT0 and INT
1
pins. If INTR, it is used to receive an interrupt request from an external interrupt
controller.
INT
3
/INTA I/O
O.D.
INTERRUPT3/INTERRUPT ACKNOWLEDGE: The bus interrupt control register
determines how this pin is interpreted. If INT
3
, it has the same interpretation as the
INT
0
, INT1 and INT2 pins. If INTA, it is used as an output to control interrupt-
acknowledge transactions. The INTA
output is latched on-chip and remains valid
during T
d
cycles; as an output, it is open-drain.
N.C. N/A NOT CONNECTED indicates pins should not be connected. Never connect any pin
marked N.C. as these pins may be reserved for factory use.
Table 4. 80960KA Pin Description: Support Signals (Sheet 2 of 2)
NAME TYPE DESCRIPTION
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
2.0 ELECTRICAL SPECIFICATIONS
2.1. Power and Grounding
The 80960KA is implemented in CHMOS IV
technology and therefore has modest power requirements. Its high clock frequency and numerous output
buffers (address/data, control, error and arbitration
signals) can cause power surges as multiple output
buffers simultaneously drive new signal levels. For
clean on-chip power distribution, V
CC
and VSS pins
separately feed the device’s functional units. Power
and ground connections must be made to all
80960KA power and ground pins. On the circuit
board, all V
cc
pins must be strapped closely together,
preferably on a power plane; all V
ss
pins should be
strapped together, preferably on a ground plane.
2.2. Power Decoupling
Recommendations
Place a liberal amount of decoupling capacitance
near the 80960KA. When driving the L-bus the
processor can cause transient power surges, particularly when connected to a large capacitive load.
Low inductance capacitors and interconnects are
recommended for best high frequency electrical
performance. Inductance is reduced by shortening
board traces between the processor and decoupling
capacitors as much as possible.
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