Intel Corporation NG80960JD-66, NG80960JD-50 Datasheet

PRODUCT PREVIEW

80960JD

3.3 V EMBEDDED 32-BIT MICROPROCESSOR

• 3.3 V, 5 V Tolerant, Version of the 80960JD Processor

■ Pin/Code Compatible with all 80960Jx

Processors

■ High-Performance Embedded Architecture

— One Instruction/Clock Execution
— Core Clock Rate is 2x the Bus Clock
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— User/Supervisor Protection Model

■ Two-Way Set Associative Instruction Cache

— 80960JD - 4 Kbyte
— Programmable Cache Locking

Mechanism

■ Direct Mapped Data Cache

— 80960JD - 2 Kbyte
— Write Through Operation

■ On-Chip Stack Frame Cache

— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority

Interrupts

■ On-Chip Data RAM

— 1 Kbyte Critical Variable Storage
— Single-Cycle Access

■ 3.3 V Supply Voltage

— 5 V Tolerant Inputs
— TTL Compatible Outputs

■ High Bandwidth Burst Bus

— 32-Bit Multiplexed Address/Data
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering

■ High-Speed Interrupt Controller

— 31 Programmable Priorities
— Eight Maskabl e Pins pl u s NMI
— Up to 240 Vectors in Expanded Mode

■ Two On-Chip Timers

— Independe nt 32-B i t Count i ng
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources

■ Halt Mode for Low Power

■ IEEE 1149.1 (JTAG) Boundary Scan

Compatibility

■ Packages

— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack (PQFP)

132

PIN 1

99

A80960JD

XXXXXXXXC0

M

© 19xx

i

33

Figure 1. 80960JD Microprocessor

© INTEL CORPORATION, 1996 November 1996 Order Number: 272971-001

i960

NG80960J D

XXXXXXXXC0S

M

i

®

©19xx

66

Information in this document is provided in connection with Intel products. No license, express or implied, by
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*Third-party brands and names are t he property of their respective owners.
Copies of documents which have an ordering number and are referenced in this document, or other Intel

literature, may be obtained from:
Intel Corporation

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or call 1-800-548-4725

©INTEL CORPORATION, 1996

Contents

80960JD

3.3 V EMBEDDED 32-BIT MICROPROCESSOR

1.0 PURPOSE .................................................................................................................................................. 1

2.0 80960JD OVERVIEW ................................................................................................................................ 1

2.1 80960 Processor Core ........................................................................................................................ 2

2.2 Burst Bus ............................................................................................................................................2

2.3 Timer Unit ...........................................................................................................................................3

2.4 Priority Interrupt Controller .................................................................................................................3

2.5 Instruction Set Summary ....................................................................................................................3

2.6 Faults and Debugging ...................... ..................................................................................................3

2.7 Low Power Operation ......................................................................................................................... 3

2.8 Test Features ..................................................................................................................................... 4

2.9 Memory-Mapped Control Registers ....................................................................................................4

2.10 Data Types and Memory Addressing Modes ................................................................................... 4

3.0 PACKAGE INFORMATION .......................................................................................................................6

3.1 Pin Descriptions .................................................................................................................................. 6

3.1.1 Functional Pin Definitions ........................................................................................................6

3.1.2 80960Jx 132-Lead PGA Pinout .............. .................................................................. .............12

3.1.3 80960Jx PQFP Pinout ........................................................................................................... 16

3.2 Package Thermal Specifications ...................................................................................................... 19

3.3 Thermal Management Accessories ..................................................................................................21

4.0 ELECTRICAL SPECIFICATIONS ...........................................................................................................22

4.1 Absolute Maximum Ratings .............................................................................................................. 22

4.2 Operating Conditions ........................................................................................................................22

4.3 Connection Recommendations ........................................................................................................ 22

4.4 V

4.5 VCCPLL Pin Requirements .............................................................................................................. 23

4.6 DC Specifications ............................................................................................................................. 24

4.7 AC Specifications ............................................................................................................................. 26

5.0 BUS FUNCTIONAL WAVEFORMS ........................................................................................................ 37

6.0 DEVICE IDENTIFICATION ......................................................................................................................51

7.0 REVISION HISTORY ............................................................................................................................... 53

Pin Requirements (V

CC5

4.7.1 AC Test Conditions and Derating Curves ..............................................................................29

4.7.2 AC Timing Waveforms ........................................................................................................... 30

) .......... ...... ... ..... ...... ...... ...... ... ..... ...... ...... ..... ...... ... ...... ..... ...... ...... ... .. 23

DIFF

iii

Contents

FIGURES

Figure 1. 80960JD Micro processor ............................................................... ...................... .......... ........... ......i

Figure 2. 80960JD Block Diagram ................................................................................................................2

Figure 3. 132-Lead Pin Grid Array Bottom View - Pins Facing Up .............................................................12

Figure 4. 132-Lead Pin Grid Array Top View - Pins Facing Down ..............................................................13

Figure 5. 132-Lead PQFP - Top View .........................................................................................................16

Figure 6. VCC5 Current-Limiting Resistor ...................................................................................................23

Figure 7. VCCPLL Lowpass Filter ...............................................................................................................23

Figure 8. AC Test Load ...............................................................................................................................29

Figure 9. Output Delay or Hold vs. Load Capacitance ................................................................................29

Figure 10. CLKIN Waveform .........................................................................................................................30

Figure 11. Output D el ay Waveform for T
Figure 12. Out put Float Waveform for T
Figure 13. Input Setup and Hold Wav eform for T
Figure 14. Input Setup and Hold Wav eform for T
Figure 15. Input Setup and Hold Wav eform for T
Figure 16. Input Setup and Hold Wav eform for T
Figure 17. Relat i ve Timings Waveform for T

Figure 18. DT/R and DEN Timings Waveform ..............................................................................................34

Figure 19. TCK Waveform ............................................................................................................................34

Figure 20. Input Setup and Hold Wav eforms for T
Figure 21. Out put Delay and Output Float Waveform for T
Figure 22. Out put Delay and Output Float Waveform for T
Figure 23. Input Setup and Hold Wav eform for T

Figure 24. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ..................................37

Figure 25. Burs t Read and Write Trans actions Without Wait States, 32-Bit Bus .......... ................................38

Figure 26. Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ...................................................39

Figure 27. Burs t Read and Write Trans actions Without Wait States, 8-Bit Bus ..................... ...................... .40

Figure 28. Burs t Read and Write Trans actions With 1, 0 Wait States

and Extra Tr State on Read, 16-Bit Bus .......................................................................................41

Figure 29. Bus Transactions Generated by Double Word Read Bus Request,

Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian ............... ........... ....42

Figure 30. HOLD/HOLDA Waveform For Bus Arbitration .............................................................................43

Figure 31. Cold Reset Waveform ..................................................................................................................44

Figure 32. Warm Reset Waveform ................................................................................................................45

Figure 33. Entering the ONCE State .............................................................................................................46

Figure 34. Summary of Aligned and Unaligned Accesses (32-Bit Bus) ........................................................49

Figure 35. Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ....................................50

Figure 36. 80960JD Device Identification Register ............................................... ........................................51

................................................................................................30

OV1

...................................................................................................31

OF

and T

IS1

and T

IS2

and T

IS3

and T

IS4

, T

LX

LXL

BSIS1

BSIS2

......................................................................31

IH1

......................................................................32

IH2

......................................................................32

IH3

......................................................................33

IH4

and T

.................................................................... 33

LXA

and T

and T

........... ................. ................. ................ 35

BSIH1

AND T

BSOV1

and T

BSOV2

.......... ........ ......... ........ ......... ......... ........ ..3 6

BSIH2

........... ..... ...... ...... ...... .. ...... ..3 5

BSOF1

............................................. 36

BSOF2

iv

Contents

TABLES

Table 1. 80960Jx Instruction Set ......................... ........... ........... .................................................... ..............5

Table 2. Pin Description Nomenclature ....................................................................................................... 6

Table 3. Pin Description — External Bus Signals ........................................................................................ 7

Table 4. Pin Description — Processor Control Signals, Test Signals and Power .....................................10

Table 5. Pin Description — Interrupt Unit Signals .....................................................................................11

Table 6. 132-Lead PGA Pi nout — In Signal Order ................. .................................................... ...............14

Table 7. 132-Lead PGA Pinout — In Pin Order .......... ........................................................................... ....15

Table 8. 132-Lead PQFP Pinout — In Signal Order .................................................................................. 17

Table 9. 132-Lead PQFP Pinout — In Pin Order ....................................................................................... 18

Table 10. 132-Lead PGA Package Thermal Characteristics ....................................................................... 19

Table 11. 132-Lead PQFP Package Thermal Characteristics .....................................................................20

Table 12. Maximum T

Table 13. 80960JD Operating Conditions ................... .................................................... ...................... .......22

Table 14. 80960JD DC Characteristics .............................. ......................................................... ................24

Table 15. 80960JD ICC Characteristics ......................................................................................................25

Table 16. 80960JD AC Characteristics ........... ......................................... ...................... .......... ........... .........26

Table 17. Note Definitions for Table 16, 80960JD AC Characteristics (pg. 26) ...........................................28

Table 18. Natural Boundaries for Load and Store Accesses ............................ ........... ...................... ..........47

Table 19. Summary of Byte Load and Store Accesses ................................................. .......... ........... .........47

Table 20. Summary of Short Word Load and Store Accesses ......................... ........... ...................... ..........47

Table 21. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4) ........... ...................... ..................48

Table 22. 80960JD66 Die and Stepping Reference .............................................. ...................... .......... ......51

Table 23. Fields of 80960JD Device ID ....................................................................................................... 52

Table 24. 80960JD Device ID Model Ty pes ............ ........... .......... ........... ...................... .......... ........... .........52

Table 25. Device ID Version Numbers for Different St eppings .......... ...................... .......... ........... ...............52

at Various Airflows in °C ......................................................................................... 21

A

v

80960JD

1.0 PURPOSE

This document contains preview information for the
80960JD microprocessor, including electrical
characteristics and package pinout information.

Detailed functional descriptions — other than
parametric performance — are published in the

i960® Jx Microprocessor User’s Guide

Throughout this data sheet, references to “80960Jx”
indicate features which appl y to all of the foll owing:

• 80960JA — 5V, 2 Kbyte instruction cach e, 1 Kbyte
data cache

• 80L960JA — 3.3V version of the 80960JA

• 80960JD — 5V, 4 Kbyte instruction ca che, 2Kbyte
data cache and clock doubling

• 80960JD — 3.3V, 5V Tolerant version of the
80960JD

• 80960JF — 5V, 4 Kbyte instruction c ache , 2 Kbyte
data cache

• 80L960JF — 3.3 V version of the 80960JF

(272483).

2.0 80960JD OVERVIEW

The 80960JD offers high performance to cost­sensitive 32-bit embedded applications. The
80960JD is object code compatible with the 80960
Core Architecture and is capable of sustained
execution at the rate of one instruction per clock.
This processor’s features include generous
instruction cache, data cache and data RAM. It also
boasts a fast interrupt mechanism, dual program­mable timer units and new instructions .

The 80960JD’s cloc k doub ler op era tes t he pr ocess or
core at twice the bus clock rate to improve execution
performance without increasing the complexity of
board designs.

Memory subsystems for cost-sensitive embedded
applications often impose substantial wait state
penalties. The 80960JD integrates considerable
storage resources on-chip to decouple CPU
execution from the external bus.

The 80960JD rapidly allocate s and deallocates local
register sets during contex t switches. The processor
needs to flush a register set to the stack only w hen it
saves more than seve n sets to its local register cache.

A 32-bit multiplexed burst bus provides a high-speed
interface to system memory and I/O. A full
complement of control signals simplifies the
connection of the 80960JD to external components.
The user programs physical and logical memory
attributes through memory-mapped control registers

(MMRs) — an extension not found on the i960 Kx,
Sx or Cx processors. Physica l and logical configu­ration registers enable the processor to operate with
all combinations of bus width and data object
alignment. The processor supports a homogeneous
byte ordering model.

This processor integrates two important peripherals:
a timer unit and an interrupt controller. These and
other hardware resources are programmed through
memory-mapped control registers, an extension to
the familiar 80960 architecture.

The timer unit (TU) offers two independent 32-bit
timers for use as real-time system clocks and
general-purpose system timing. These operate in
either single-shot or auto-reload mode and can
generate interrupts.

The interrupt controller unit (ICU) provides a flexible
means for requesting interrupts. The ICU provides
full programmability of up to 240 interrupt sources
into 31 priority levels. The ICU takes advantage of a
cached priority table and optional routine caching to
minimize interrupt latency. Clock doubling reduces
interrupt latency by 40% compared to the
80960JA/JF. Local registers may be dedicated to
high-priority interrupts to further reduce latency.
Acting independently from the core, the ICU
compares the priorities of posted interrupts with the
current process priori ty, off-loading this task from the
core. The ICU also supports the integrated timer
interrupts.

The 80960JD features a Halt mode designed to
support applications where low power consumption
is critical. The halt instruction shuts down instruction
execution, resulting in a power savings of up to 90
percent.

The 80960JD’s testability features, including ONCE
(On-Circuit Emulation) mode and Boundary Scan
(JTAG), provide a powerful environment for design
debug and fault di agnosis.

The

Solutions9 60®

of development tools which support the i960
processor family. Many of these tools are developed
by partner companies; some are developed by Intel,
such as profile-driven optimizing compilers. For
more information on these products, contact your
local Intel representative.

program features a wide variety

PRODUCT PREVI EW 1

80960JD

CLKIN

TAP

Local Register Cache

PLL, Clocks,
Power Mgmt

Boundary Scan

5

8-Set

128

Global / Local

Register File

SRC2 DESTSRC1

Controller

3 Independent 32-Bit SRC1, SRC2, and DEST Buses

4 K Byte Instruction Cache

Two-Way Se t Associative

Constants

and

Address

Unit

effective

address

SRC1

SRC2

Control

DEST

Multiply

Divide

Unit

SRC1

SRC2

Instruction Sequencer

Execution

Generation

DEST

Figure 2. 80960JD Block Diagram

Memory
Interface

Unit

32-bit Address

32-bit Data

SRC1

32-bit buses

address / data

DEST

Physical R egion

Configuration

Bus

Control Unit

Bus Request

Queues

Two 32-Bit

Timers

Programmable

Interrupt Controller

Memory-Mapped
Register Interface

1K byte

Data RAM

2 Kbyte Direct

Mapped Data

Cache

Control

21

Address/
Data Bus

32

Interrupt
Port

9

2.1 80960 Processor Core

The 80960Jx family is a sca l ar implementation of the
80960 Core Architecture. Intel designed this
processor core as a very high performance device
that is also cost-effec tive. Factors that contribute to

the core’s performance include:

• Core operates at twic e the bus speed (80960J D
only)

• Single-clock execution of most instructi ons

• Independent Multi ply/Divide Unit

• Efficient instruction pipeli ne mi nimizes pipelin e
break latency

• Register and resource sc oreboarding allow
overlapped instruction execution

• 128-bit register bus speeds local regi st er caching

• 4 Kbyte two-way set associative, integrated
instruction cache

2

• 2 Kbyte direct-mapped, integrated data c ache

• 1 Kbyte integrated data RAM delivers zero wait
state program data

2.2 Burst Bus

A 32-bit high-performance bus controller interfaces
the 80960JD to external memory and peripherals.
The BCU fetches instructions and transfers data at
the rate of up to four 32-bit words per six clock
cycles. The external address/data bus is multi­plexed.

Users may configure the 80960JD’s bus controller to
match an application’s fundamental memory organi­zation. Physical bus width is register-programmed
for up to eight regions. Byte ordering and data
caching are programmed through a group of logical
memory templates and a defaults regist er.

PRODUCT PREVIEW

80960JD

The BCU’s features include:

• Multiplexed external bus to minimize pin count

• 32-, 16- and 8-bit bus wi dths to simplify I/O
interfaces

• External ready control for address-to-data, data-to­data and data-to-next-addres s wai t state types

• Support for big or lit tle endian byte ordering to
facilitate the porting of existing program code

• Unaligned bus accesses performed transparently

• Three-deep load/store queue to decouple the bus
from the core

Upon reset, the 80960JD conducts an internal self
test. Then, before executing its first instruction, it
performs an external bus confidence test by
performing a checksum on the first words of the
initialization boot record (IBR).

The user may examine the contents of the caches at
any time by executing special cache control instruc­tions.

2.3 Timer Unit

The timer unit (TU) contains two independent 32-bit
timers which are capable of coun tin g at s evera l clo ck
rates and gener at ing in te rrup ts. Each is pr ogrammed
by use of the TU registers. These memory-mapped
registers are addressable on 32-bit boundaries. The
timers have a single-shot mode and auto-reload
capabilities for continuous operation. Each timer has
an independent interrupt request to the 80960JD’s
interrupt controller. The TU can generate a fault
when unauthorized writes from user mode are
detected. Clock prescaling is su pported.

• Interrupt vectors and interr upt han dler rou tines can
be reserved on-chip

• Register frames for high-priority interrupt handl ers
can be cached on-chi p

• The interrupt stack can be placed in cacheable
memory space

• Interrupt microcode executes at twice the bus
frequency

2.5 Instruction Set Summary

The 80960Jx adds several new instructions to the
i960 core archi tecture. The new ins tructions are:

• Conditional Move

• Conditional Add

• Conditional Subtract

•Byte Swap

•Halt

• Cache Control

• Interrupt Control

Table 1 identifies the instructions that the 80960Jx
supports. Refer to

Guide

(272483) for a detailed description of each

instruction.

i960® Jx Microprocessor User’s

2.6 Faults and Debugging

The 80960Jx employs a comprehensive fault model.
The processor responds to faults by making implicit
calls to a fault handling routine. Specific information
collected for each fault allows the fault handler to
diagnose exceptions and recover appropriately.

2.4 Priority Interrupt Controller

A programmable interrupt controller manages up to
240 external sources through an 8-bit external
interrupt port. Alternatively, the interrupt inputs may
be configured for individual edge- or level-triggered
inputs. The interrupt unit (IU) also accepts interrupts
from the two on-chip timer channels and a single
Non-Maskable Interrupt (NMI
servic ed accordin g to their prio rity levels rel ative to
the current proce ss pri ority.

Low interrupt latency is critical to many embedded
applications. As part of its highly flexible interrupt
mechanism, the 80960JD exploits several
techniques t o mi nimize latency:

) pin. Interrupts are

The processor also has buil t-in debug capabilities. In
software, the 80960Jx may be configured to detect
as many as seven different trace event types. Alter­natively, mark and fmark instructions can generate
trace events explicitly in the instruction stream.
Hardware breakpoint registers are also available to
trap on execution and data addresses.

2.7 Low Power Operation

Intel fabricates the 80960Jx using an advanced sub-

micron manufac turing process. The processor’s sub­micron topology provides the circuit density for
optimal cache size and high operating speeds while

PRODUCT PREVI EW 3

80960JD

dissipating modest power. The processor also uses
dynamic power management to turn off clocks to
unused circuits.

Users may program the 80960Jx to enter Halt mode
for maximum power savings. In Halt mode, the
processor core stops completely while the integrated
peripherals continue to function, reducing overall
power requirements up to 90 percent. Processor
execution resumes from internally or externally
generated int errupts.

2.8 Test Features

The 80960Jx incorporates numerous features which

enhance the user’s ability to test both the processor
and the system to which it is attached. These
features include ONCE (On-Circuit Emulation) mode
and Boundary Sc an (JTAG).

The 80960Jx provides test ability featu r es compatible
with IEEE Standard Test Access Port and Boundary
Scan Architec ture (IEEE Std. 1149.1).

One of the boundary scan instructions, HIGHZ,
forces the processor to float all its output pins
(ONCE mode). ONCE mode can also be initiated at
reset witho ut using the boundary scan mechanism.

ONCE mode is useful for board-level testing. This
feature allows a mounted 80960JD to electrically
“remove” itself from a circuit board. This allows for
system-level testin g where a remote tester — such
as an in-circuit emulator — can exercise the
processor system.

The provided test logic does not interfere with
component or circuit board behavior and ensures
that components function correctly, connections
between various components are correct, and
various components interact correctly on the printed
circuit board.

2.9 Memory-Mapped Control Registers

The 80960JD, though compliant with i960 series
processor core, has the added advantage of
memory-mapped, intern al control registers not found
on the i960 Kx, Sx or Cx processors. These give
software the interface to easily read and modify
internal control registers.

Each of these registers is accessed as a memory­mapped, 32-bit register. Access is accomplished
through regular memory-format instructions. The
processor ensures that these accesses do not
generate external bus cycles.

2.10 Data Types and Memory Addressing Modes

As with all i960 family processors, the 80960Jx
instruction set supports several data types and
formats:

•Bit

•Bit fields

• Integer (8-, 16-, 32-, 64-bit)

• Ordinal (8-, 16-, 32-, 64-bit unsigned i ntegers)

• Triple word (96 bits)

• Quad word (128 bits)

The 80960Jx prov ides a ful l set of addre ssin g modes
for C and assembly programming:

• Two Absolute modes

• Fiv e Re gi ster Indir e ct m od e s

• Index with displacement

• IP with displacement

The JTAG Boundary Scan feature is an attractive
alternative to conventional “bed-of-nails” testing. It
can examine connections which might otherwise be
inaccessible to a test system.

4

PRODUCT PREVIEW

80960JD

Table 1. 80960Jx Instruction Set

Data Movement Arithmetic Logical Bit, Bit Field and Byte

Load
Store
Move
*Conditional Select
Load Address

Comparison Branch Call/Ret urn Fault

Compare
Conditional Compare
Compare and

Increment
Compare and

Decrement
Test Condition Code
Check Bit

Debug

Modify Trace Controls
Mark
Force Mark

NOTES: Asterisk (*) denotes new 80960Jx instructions unavailable on 80960CA/CF, 80960KA/KB and 80960SA/SB
implementations.

Add
Subtract
Multiply
Divide
Remainder
Modulo
Shift
Extended Shi ft
Extended Multiply
Extended Divide
Add with Carry
Subtract with Carry
*Conditional Add
*Conditional Subtract
Rotate

Unconditional Branch
Conditional Branch
Compare and Branch

Processor

Management

Flush Local Registers
Modify Arithmetic

Controls
Modify Process

Controls
*Halt
System Control
*Cache Control
*Interrupt Control

And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Nor
Exclusive Nor
Not
Nand

Call
Call Extended
Call System
Return
Branch and Link

Atomic

Atomic Add
Atomic Modify

Set Bit
Clear Bit
Not Bit
Alter Bit
Scan For Bit
Span Over Bit
Extract
Modify
Scan Byte for Equal
*Byte Swap

Conditional Fault
Synchronize Faults

PRODUCT PREVI EW 5

80960JD

3.0 PACKAGE INFORMATION

The 80960JD is offered with three speeds and two
package types. The 132-pin Pin Grid Array (PGA)
device is specified for operation at V

over a case temperature range of 0° to 10 0°C :

=3.3V±5%

CC

• A80960JD-66 (66 MHz core, 33 MHz bus)

• A80960JD-50 (50 MHz core, 25 MHz bus)

• A80960JD-40 (40 MHz core, 20 MHz bus)
The 132-pin Plastic Quad Flatpack (PQFP) devices

will be specified for operation at V
over a case temperature range of 0° to 10 0°C :

= 3.3 V ± 5%

CC

• NG80960JD-66 (66 MHz core, 33 MHz bus)

• NG80960JD-50 (50 MHz core, 25 MHz bus)

• NG80960JD-40 (40 MHz core, 20 MHz bus)
For complete package specifications and infor-

mation, refer to Intel’s

Packaging Handbook

(240800).

3.1 Pin Descriptions

This section describes the pins for the 80960JD in
the 132-pin ceramic Pin Grid Array (PGA) package
and 132-lead Plastic Quad Flatpack Package
(PQFP).

Section 3.1.1, Functional Pin Definitions
describes pin function; Section 3.1.2, 80960Jx 132­Lead PGA Pinout and Section 3.1.3, 80960Jx
PQFP Pinout define the signal and pin locations for

the supported package types.

3.1.1 Functional Pin Definitions

Table 2 presents the legend for interpreting the pin
descriptions which follow. Pins associa ted with the
bus interface are described in Table 3. Pins
associated with basic control and test functions are
described in Table 4. Pins associated with the
Interrupt Unit are described in Table 5.

Table 2. Pin Description Nomenclature

Symbol Description

I Input pin only.

O Output pin only.

I/O Pin can be either an input or output.

– Pin must be connected as described.

S Synchronous. Inputs must meet setup

and hold times relative to CLKI N for
proper operation .

S(E) Edge sensi tive input
S(L) Level sensitive input

A (...) Asynchronous. Inputs may be

asynchronous relative to CLKIN.

A(E) Edge sensi tive input
A(L) Level sensitive input

R (...) While the processor’s R ESET

pin is

asserted, the pin:

R(1) is driven to V
R(0) is driven to V
R(Q) is a valid output

CC
SS

R(X) is driven to unknown state
R(H) is pulled up to V

CC

H (...) While the processor is in the hold state,

the pin:

H(1) is driven to V
H(0) is driven to V
H(Q) Maintain s previous state or

CC
SS

continues to be a valid output
H(Z) Floats

P (...) While the processor is halted, the pin:

P(1) is driven to V
P(0) is driven to V
P(Q) Maintains previous state or

CC
SS

continues to be a valid output

6

PRODUCT PREVIEW

Table 3. Pin Description — External Bus Signals (Sheet 1 of 4)

NAME TYPE DESCRIPTION

AD31:0 I/O

R(X)
H(Z)
P(Q)

ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data
to and from memory . D uring an address (

S(L)

address (bits 0- 1 i ndicate SIZE; see below). During a data (T

T

a

data is present on one or more contiguous bytes, comprising AD31:24, AD23:16,
AD15:8 and AD7:0. During write operations, unused pins are driven to determinate
values.

SIZE, which comprises bits 0-1 of th e AD l ines during a
number of data trans fers during the bus transaction.

AD1 AD0 Bus Transfers
0 0 1 Transfer

0 1 2 Transfers
1 0 3 Transfers
1 1 4 Transfers

When the processor enters Halt mode, if the previous bus operation was a:

• write — AD31:2 are driven with the last data value on the AD bus.

• read — AD31:4 are driven wi th the last address va lue on the AD bus; AD3:2 are
driven with the value of A3:2 from the last data cycle.

Typically, AD 1:0 reflect the SIZE information of the last bus transac ti on (either
instruction fetch or load/store) that was execut ed before enteri ng H alt mode.

ALE O

R(0)
H(Z)

ADDRESS LATCH ENABLE indicates the transfer of a physical addres s. ALE is
asserted during a
active HIGH and floats to a high impedance state during a hold cycle (T

T

cycle and deasserted before the beginning of the Td state. It is

a

P(0)

ALE

R(1)
H(Z)

ADDRESS LATCH ENABLE indicates the transfer of a phys ical addres s. ALE

O

inverted ver si on o f ALE . This sign al g iv es t he 80960J D a hig h de gree o f co mpat ibil i ty
with existing 80960Kx systems.

P(1)

ADS

R(1)
H(Z)

ADDRESS STROBE indicates a valid add ress and the start of a new bus access.

O

The processor assert s ADS
samples ADS

at the end of the cycle.

for the entire Ta cycle. Exter nal b us c ontrol logi c t ypic all y

P(1)

A3:2 O

R(X)
H(Z)
P(Q)

ADDRESS3:2 comprise a partial demultiplexed ad dress bus.

32-bit memory accesses:

the processor asse rts address bits A3:2 during Ta. The

partial word address increments with each assertion of RDYRCV

16-bit memory accesses:

driven on the
of RDYRCV

BE1 pin. The par tial short word addres s increme nts wit h each assert ion

during a burst.

8-bit memory accesses:

driven on BE1: 0
RDYRCV

. The partial byte address increments with each assertion of

during a burst.

the processor asse rts address bits A3:1 during Ta with A1

the processor as sert s addr es s bits A3 :0 duri ng Ta, with A1:0

80960JD

) cycle, bits 31:2 contain a physical word

) cycle, read or write

d

T

cycle, specifies the

a

).

h

is the

during a burst.

PRODUCT PREVI EW 7

80960JD

Table 3. Pin Description — External Bus Signals (Sheet 2 of 4)

NAME TYPE DESCRIPTION

BE3:0 O

R(1)
H(Z)
P(1)

BYTE ENABLES select which of up to four data bytes on the bus participate in the
current bus ac cess. Byte enabl e encoding is dependent on the bus width of the
memory region accessed:

32-bit bus:

enables data on AD31:24

BE3
BE2

enables data on AD23:16

BE1

enables data on AD15:8

BE0

enables data on AD7:0

16-bit bus:

BE3 becomes Byte High Enab l e (enables data on AD15:8)
BE2

is not used (state is high)

BE1

becomes Address Bit 1 (A1)

BE0

become s By t e Low Enabl e (e na b l es da t a on AD7:0)

8-bit bus:

BE3 is not used (state is high)
BE2

is not used (state is high)

BE1

becomes Address Bit 1 (A1)

BE0

becomes Address Bit 0 (A0)

The processor ass erts byte ena bles, byt e hig h en able and byt e low e nab le du ring
Since unaligned bus requests are sp lit into separate bus transactions, these signals
do not toggle during a burst. They remai n active through t he l ast T

For accesses to 8- and 16-bit memory, the processor asserts the address bits in
conjunction with A3:2 described above.

WIDTH/
HLTD1:0OR(0)

H(Z)
P(1)

WIDTH/HALTED signals denote the physical memory attribute s for a bus trans­action:

WIDTH/HLTD1 WIDTH/HLTD0
00 8 Bits Wide

0 1 16 Bits Wide
1 0 32 Bits Wide
1 1 Processor Hal ted

The processor floats the WIDTH/HLTD pins whenever it rel i nquishes the bus in
response to a HOLD request, regardless of prior operating state.

D/C

R(X)

H(Z)

P(Q)

W/R

R(0)
H(Z)

P(Q)

DT/R

R(0)
H(Z)

P(Q)

DATA/CODE indicates that a bus access is a data access (1) or an instruction

O

access (0). D/C

has the same timi ng as W/R.

0 = instruction access
1 = data access

WRITE/READ specifies, during a

O

read (0). It is l atched on-chip and r emai ns valid during T

T

cycle, whether the operation is a write (1) or

a

0 = read
1 = write

DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the

O

address/data bus. It is low during T
and T

/Td cycles for a write. DT/R never changes state when DEN is asserted.

w

and Tw/Td cycles for a read; it is high duri ng Ta

a

0 = receive
1 = transmit

cycles.

d

cycle.

d

T

.

a

8

PRODUCT PREVIEW

Table 3. Pin Description — External Bus Signals (Sheet 3 of 4)

NAME TYPE DESCRIPTION

DEN O

BLAST

RDYRCV

LOCK
ONCE

HOLD I

R(1)
H(Z)

R(1)
H(Z)

/

R(H)
H(Z)

DATA ENABLE indicates data transf er cycles during a bus access. DEN
at the start of the first data cycle in a bus access and deasserted at the end of the
last data cycle. DEN

P(1)

connected to the data bus.
0 = data cycle

1 = not data cycle

BURST LAST indicates the last trans fe r in a bus access. BLA ST

O

last data transfer of burst and non-burst accesses . BLAST
wait states are inserted via the RDYRCV

P(1)

data transfer in a bus cycle.
0 = last dat a tr an sfer

1 = not last data transfer

I

READY/RECOVER indicates that data on AD lines can be sampled or removed. If

S(L)

RDYRCV
by inserting a wa it state (T

0 = sample data

1 = don’t sample data
The RDYRCV

continues to insert additional recovery st ates until it sampl es the pin HIGH. T hi s
function gives slow external devi ces more time to float their buffers before the
processor beg i ns to drive address ag ain.

0 = insert wait states
1 = recovery complete

BUS LOCK indicates that an atomic read-modify-write operation is in progress. The

I/O

LOCK

S(L)

the last data transfer of the sequence. The processor does not grant HOLDA while it
is asserting LOCK

P(1)

in semaphore operations.
0 = Atomic read-modify-write in progress

1 = Atomic read-modify-write not in progress
ONCE MODE: The processor samples the ONCE

LOW at the end of reset, the processor enters ONCE mode. In ONCE mode, the
processor stops all clocks and floats all output pins. The pin has a weak internal
pullup which is active during reset to ensure normal operation when the pin is l eft
unconnected.

0 = ONCE mode enabled
1 = ONCE mode not enabled

HOLD: A request from an ext ernal bus master to acq uire the bus. When the

S(L)

processor receiv es HOLD and grants bus control to another master, i t as serts
HOLDA, floats the address/d ata and control lines and enters the T
HOLD is deasserted, the processor deasserts HOLDA and enters either the T
state, resuming control of the address/data and control lines.

0 = no hold request
1 = hold request

is not asserte d du ring a Td cycle, th e Td cycle is extended to the next cycle

output is asserted in the first cl ock of an atomic operation and deasserted in

is used with DT/R to provide control for data transceivers

pin. BLAST become s in acti ve afte r th e f inal

).

w

pin has another func ti on duri ng th e recov ery (Tr) state. The processor

. This prevents external agents from accessing memory i nvolved

80960JD

is asserted

is asserted in the

remains active as long as

input during r eset. If it is asserted

state. When

h

or Ta

i

PRODUCT PREVI EW 9

80960JD

Table 3. Pin Description — External Bus Signals (Sheet 4 of 4)

NAME TYPE DESCRIPTION

HOLDA O

R(Q)

H(1)

P(Q)

BSTAT O

R(0)

H(Q)

P(0)

Table 4. Pin Description — Processor C ontrol Signals, Test Signals and Power (Sheet 1 of 2)

NAME TYPE DESCRIPTION

CLKIN I CLOCK INPUT provides the processor’s fundamental time base; bot h the processor

RESET

A(L)

STEST I

S(L)

FAIL

R(0)

H(Q)

P(1)

TCK I TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1

TDI I

S(L)

HOLD ACKNOWLEDGE indicates to an external bus master that the processor has
relinquished control of the bus. T he processor can grant HOLD requests and enter
the T

state during reset and while halted as well as during regular operat i on.

h

0 = hold not acknowledged
1 = hold acknowledged

BUS STATUS indicates that th e processor may soon stall unless it has suffi cient
access to the bus; see
logic can examine this signal to determine when an external bus master should
acquire/relinquish the bus.

0 = no potential st all
1 = potential stall

core and the external bus run at the CLKIN rate. All input and output timings are
specified rel ative to a rising CLKIN edge.

I

RESET initializes the processor and clears its internal logic. During reset, the

processor places the address/data bus and control output pins in their idle (inactive)
states.

During reset, the input pins are ignored with the exception of LOCK
and HOLD.

The RESET
ization during po w e r up , RE SET
cycles with V
a minimum of 15 cycles.

SELF TEST enables or disables the processor’s i nternal self-te st feature at init i al­ization. STE ST is examined at the end of reset. When STEST is asserted, the
processor performs its internal self-test and t he external bus conf i dence test. When
STEST is deasserted, the processor performs only the ex ternal bus confidence test.

0 = self test disabled
1 = self test enabl ed

FAIL indicates a failure of the processor’s built-in self-tes t performed during ini tial-

O

ization. FAIL
indicate the status of indiv idual tests:

• When self-test passes, the processor deass erts FAIL
user code.

• When self-test fails, the processor asserts FAIL

0 = self test failed
1 = self test passed

Boundary Scan Tes ting (JTAG). State i nformation and data are clocked into the
processor on the ris ing edg e; data is cl ocked out of the pro cesso r on the f alling edge .

TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising
edge of TCK, during the SHIFT-IR and SHIFT-DR states of the T est Access Port.

pin has an internal synchro nizer . To ens ure pred ictab le pro cesso r ini tial -

CC

is asserted immediately upon reset and toggles during self-test to

i960® Jx Microprocessor User’s Guide

must be asserted a mini mum of 10,000 CLKIN

and CLKIN stable. On a warm reset, RESET should be asserted for

and then stops executing.

(272483). Arbitration

/ONCE, STEST

and begins opera tion from

10

PRODUCT PREVIEW

Table 4. Pin Description — Processor C ontrol Signals, Test Signals and Power (Sheet 2 of 2)

NAME TYPE DESCRIPTION

TDO O

R(Q)

TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling
edge of TCK during the SHIFT-IR and SH IFT-DR states of the Test Access Port. At
other times, TDO fl oats. TDO does not float during ONCE mode.

HQ)

P(Q)

TRST

TMS I

V

CC

V

CCPLL

I

TEST RESET asynchronously resets the Test Access Port (TAP) c ontroller functi on

A(L)

of IEEE 1149.1 Boundary Scan testing (JTAG). When u sing the Boundary Scan
feature, conn ect a pulldown resistor between this pin and V
this pin must be conne cted to V
Connection Recommendations (pg. 22).

; however, no re si stor is r equi red. Se e Se ction 4. 3,

SS

. If TAP is not used,

SS

TEST MODE SELECT is sampled at the rising edge of T CK to selec t the oper ation of

S(L)

the test logi c for IEEE 1149.1 Boundary Scan testi ng.

– POWER pins intended for external connection to a VCC board plane.
– PLL POWER is a separate VCC supply pin for the phase lock l oop clock generator. It

is intended f o r external connection to the V
add a simple bypass filter circuit to reduce noise-i nduced clock jitter and its effects

board plane. In noi sy environmen ts,

CC

on timing rela ti on sh ip s.

V

CC5

– 5 V REFERENCE VOLTAGE input is the ref erence voltage for the 5 V-tolerant I/O

buffers. This signal should be connected to +5 V for use with inputs wh i ch exceed

3.3 V. If all inputs are from 3.3V components, thi s pin should be connected to 3.3 V.

V

SS

– GROUND pins intende d for external connection to a VSS board plane.

NC – NO CONNECT pins. Do not make any system connections to these pins.

80960JD

Table 5. Pin Description — Interrupt Unit Signals

NAME TYPE DESCRIPTION

XINT7:0

I

A(E/L)

EXTERNAL INTERRUPT pins are used to reques t interrupt service. The XINT7:0
pins can be confi gured in three modes:

Dedicated Mode: Each pin is assigned a dedicated interrupt level. Dedicated inpu ts

can be programmed to be le vel (low) or edge (fall i ng) sensitive.

Expanded Mode: All eight pins ac t as a vect or ed in te rrupt s ou rce. The i nter rupt pin s

are level sensitive in this mode.

Mixed Mode:

The XINT7:5 pins act as dedic ated sources and the XINT4:0 pins
act as the five most signific ant bits of a vectored source. The least

NMI

I

A(E)

significant bits of the vectored source are set to 010

Unused external interrupt pins should be connected to V

CC

.

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.
NMI

is the highest priority interrupt source and is falling edge-triggered. If NMI is

unused, it should be connected to V

CC

.

internally.

2

PRODUCT PREVI EW 11

80960JD

3.1.2 80960Jx 132-Lead PGA Pinout

1413121110987654321

P

AD25

AD18AD19AD22

CC

CC

CC

CC

CC

CC

AD13V

CC

AD6AD11

V

V

V

V

V

V

N

V

AD20AD24AD26AD27

SS

SS

SS

SS

SS

SS

SS

AD3AD7AD10

V

V

V

V

V

V

M

AD29AD30 NC

AD21AD23

AD14AD15AD16AD17

L

BE3

BE2

K

V

CC

AD28

V

AD31

SS

J

V

CC

H

G

F

E

D

C

B

V

CC

CC

V

CC

V

CC

V

CC

LOCK/
ONCE

A

SS

V

SS

V

V

V

SS

HOLDA

WIDTH/ADS

HLTD1

SS

SS

SS

BE1V

BE0

ALEV

BSTAT

DEN

DT/RV

A2

A3 XINT1

BLAST

HLTD0

NCTDOWIDTH/D/CW/R XINT4

NCNCALE

CC5

V

V

SS

SS

V

V

CC

CC

V

SS

SS

V

CC

CC

AD9AD12

AD8

AD5

AD2

NC

V

CCPLL

NC

RDYRCV

RESET

TDI

XINT0

XINT6V

XINT5XINT7NMIV

AD4

AD1

V

V

V

V

V

V

TCKXINT3

AD0

V

CC

V

CC

SS

V

CC

SS

CLKINV

SS

V

CC

SS

V

CC

SS

V

CC

SS

V

CC

SS

NCSTESTTRSTHOLDNCFAIL V

NC

TMSXINT2

P

N

M

L

K

J

H

G

F

E

D

C

B

A

12

1413121110987654321

Figure 3. 132-Lead Pin Grid Array Bottom View - Pins Facing Up

PRODUCT PREVIEW