Intel Corporation N87C196NT, N80C196NT Datasheet

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

September 1994COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 272267-004

8XC196NT

CHMOS MICROCONTROLLER WITH

1 MBYTE LINEAR ADDRESS SPACE

Y

20 MHz Operation

Y

High Performance CHMOS 16-Bit CPU

Y

Up to 32 Kbytes of On-Chip OTPROM

Y

Up to 1 Kbyte of On-Chip Register RAM

Y

Up to 512 Bytes of Internal RAM

Y

Register-Register Architecture

Y

4 Channel/10-Bit A/D with Sample/Hold

Y

37 Prioritized Interrupt Sources

Y

Up to Seven 8-Bit (56) I/O Ports

Y

Full Duplex Serial I/O Port

Y

Dedicated Baud Rate Generator

Y

Interprocessor Communication Slave
Port

Y

Selectable Bus Timing Modes for
Flexible External Memory Interfacing

Y

Oscillator Fail Detection Circuitry

Y

High Speed Peripheral Transaction
Server (PTS)

Y

Two Dedicated 16-Bit High-Speed
Compare Registers

Y

10 High Speed Capture/Compare (EPA)

Y

Full Duplex Synchronous Serial I/O
Port (SSIO)

Y

Two Flexible 16-Bit Timer/Counters

Y

Quadrature Counting Inputs

Y

Flexible 8-/16-Bit External Bus
(Programmable)

Y

Programmable Bus (HOLD/HLDA)

Y

1.4 ms 16 x 16 Multiply

Y

2.4 ms 32/16 Divide

Y

68-Pin Package

Device Pins/Package OTPROM

Reg Code Address

I/O EPA A/D

RAM RAM Space

8XC196NT 68P PLCC 32K 1K 512 1 Mbyte 56 10 4

Xe7 OTPROM Device
X

e

0 ROMLESS

The 8XC196NT 16-bit microcontroller is a high performance member of the MCSÉ96 microcontroller family.
The 8XC196NT is an enhanced 8XC196KR device with 1 Mbyte of linear address space, 1000 bytes of
register RAM, 512 bytes of internal RAM, 20 MHz operation and an optional 32 Kbytes of OTPROM. Intel’s
CHMOS III-E process provides a high performance processor along with low power consumption.

Ten high-speed capture/compare modules are provided. As capture modules event times with 200 ns resolu­tion can be recorded and generate interrupts. As compare modules events such as toggling of a port pin,
starting an A/D conversion, pulse width modulation, and software timers can be generated. Events can be
based on the timer or up/down counter.

8XC196NT

272267– 1

Figure 1. 8XC196NT Block Diagram

PROCESS INFORMATION

This device is manufactured on P629.5, a CHMOS
III-E process. Additional process and reliability infor­mation is available in Intel’s

Components Quality

and Reliability Handbook

, Order Number 210997.

Table 1. Thermal Characteristics

Package

i

JA

i

JC

Type

PLCC 36.5§C/W 13§C/W

All thermal impedance data is approximate for static
air conditions at 1W of power dissipation. Values will
change depending on operation conditions and ap­plication. See the Intel

Packaging Handbook

(order
number 240800) for a description of Intel’s thermal
impedance test methodology.

272267– 2

EXAMPLE: N87C196NT is 68-Lead PLCC OTPROM.
For complete package dimensional data, refer to the Intel Packaging Handbook (Order Number 240800).

Figure 2. The 8XC186NT Familiy Nomenclature

2

8XC196NT

8XC196NT Memory Map

Address

Description

(Note 7)

FFFFFFH

External Memory

FFA000H

FF9FFFH Internal OTPROM or External Memory (Determined by EA Pin)
FF2080H RESET at FF2080H

FF207FH Reserved Memory (Internal OTPROM or External Memory)
FF2000H (Determined by EA

Pin)

FF1FFFH

External Memory

FF0600H

FF05FFH

Internal RAM (Identically Mapped into 00400H–005FFH)

FF0400H

FF03FFH

External Memory

FF0100H

FF00FFH

Reserved for ICE

FF0000H

FEFFFFH

External Memory for future devices

100000H

FFFFFH

984 Kbytes External Memory

00A000H

009FFFH

Internal OTPROM or External Memory (Note 1)

002080H

00207FH Reserved Memory (Internal OTPROM or External Memory)
002000H (Notes 1, 3, and 6)

001FFFH

Memory Mapped Special Function Registers (SFR’s)

001FE0H

001FDFH

Internal Special Function Registers (SFR’s) (Note 5)

001F00H

001EFFH

External Memory

000600H

0005FFH Internal RAM
000400H (Address with Indirect or Indexed Modes)

0003FFH

Upper Register File (Address with Indirect or

Register RAM

Indexed Modes or through Windows.) (Note 2)

000100H

*

0000FFH

Register RAM

Lower Register File

000018H (Address with Direct,

000017H

CPU SFR’s

Indirect, or Indexed

000000H *

Modes.) (Notes 2, 4)

NOTES:

1. These areas are mapped internal OTPROM if the REMAP bit (CCB2.2) is set and EA

e

5V. Otherwise they are external

memory.

2. Code executed in locations 00000H to 003FFH will be forced external.

3. Reserved memory locations must contain 0FFH unless noted.

4. Reserved SFR bit locations must be written with 0.

5. Refer to 8XC196NT User’s Guide and Quick Reference for SFR descriptions.

6. WARNING: The contents or functions of reserved memory locations may change with future revisions of the device.
Therefore, a program that relies on one or more of these locations may not function properly.

7. The 8XC196NT internally uses 24 bit address, but only 20 address lines are bonded out allowing 1 Mbyte external
address space.

3

8XC196NT

272267– 3

Figure 3. 68-Pin PLCC Package Diagram

4

8XC196NT

PIN DESCRIPTIONS

Symbol Name and Function

V

CC

Main supply voltage (a5V).

VSS,V

SS1,VSS1

Digital circuit ground (0V). There are multiple VSSpins, all of which MUST be
connected.

V

REF

Reference for the A/D converter (a5V). V

REF

is also the supply voltage to the
analog portion of the A/D converter and the logic used to read Port 0. Must be
connected for A/D and Port 0 to function.

V

PP

Programming voltage for the OTPROM parts. It should bea12.5V for programming.
It is also the timing pin for the return from powerdown circuit. Connect to V

CC

if

powerdown not being used.

ANGND Reference ground for the A/D converter. Must be held at nominally the same

potential as V

SS

.

XTAL1 Input of the oscillator inverter and the internal clock generator.

XTAL2 Output of the oscillator inverter.

P2.7/CLKOUT Output of the internal clock generator. The frequency is (/2 the oscillator frequency.

It has a 50% duty cycle. Also LSIO pin.

RESET Reset input to and open-drain output from the chip. RESET has an internal pullup.

P5.7/BUSWIDTH Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin

dyamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low,
an 8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is ‘‘0’’
and CCR1 bit 2 is ‘‘1’’, all bus cycles are 8-bit, if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is
‘‘0’’, all bus cycles are 16-bit. CCR bit 1

e

‘‘0’’ and CCR1 bit 2e‘‘0’’ is illegal. Also

an LSIO pin when not used as BUSWIDTH.

NMI A positive transition causes a non maskable interrupt vector through memory

location 203EH.

P5.1/INST/SLPCS Output high during an external memory read indicates the read is an instruction

fetch. INST is valid throughout the bus cycle. INST is active only during external
memory fetches, during internal OTPROM fetches INST is held low. Also LSIO when
not INST. SLPCS

is the Slave Port Chip Select.

EA Input for memory select (External Access). EA equal to a high causes memory

accesses to locations 0FF2000H through 0FF9FFFH to be directed to on-chip
OTPROM. EA

equal to a low causes accesses to these locations to be directed to

off-chip memory. EA

ea

12.5V causes execution to begin in the Programming

Mode. EA

is latched at reset.

HOLD Bus Hold Input requesting control of the bus.

HLDA Bus Hold acknowledge output indicating release of the bus.

BREQ Bus Request output activated when the bus controller has a pending external

memory cycle.

P5.0/ALE/ADV/ Address Latch Enable or Address Valid output, as selected by CCR. Both pin

options provide a latch to demultiplex the address from the address/data bus. When

SLPADDR/

the pin is ADV

, it goes inactive (high) at the end of the bus cycle. ADV can be used

SLPALE

as a chip select for external memory. ALE/ADV

is active only during external
memory accesses. Also LSIO when not used as ALE. SLPADDR is the Slave Port
Address Control Input and SLPALE is the Slave Port Address Latch Enable Input.

P5.3/RD/SLPRD Read signal output to external memory. RD is active only during external memory

reads or LSIO when not used as RD. SLPRD is the Slave Port Read Control Input.

5

8XC196NT

PIN DESCRIPTIONS (Continued)

Symbol Name and Function

P5.2/WR/WRL/SLPWR Write and Write Low output to external memory, as selected by the CCR, WR

will go low for every external write, while WRL will go low only for external
writes where an even byte is being written. WR

/WRL is active during external

memory writes. Also an LSIO pin when not used as WR

/WRL. SLPWR is the

Slave Port Write Control Input

P5.5/BHE/WRH Byte High Enable or Write High output, as selected by the CCR. BHEe0

selects the bank of memory that is connected to the high byte of the data bus.
A0

e

0 selects that bank of memory that is connected to the low byte. Thus

accesses to a 16-bit wide memory can be to the low byte only (A0

e

0,

BHE

e

1), to the high byte only (A0e1, BHEe0) or both bytes (A0e0,

BHE

e

0). If the WRH function is selected, the pin will go low if the bus cycle is

writing to an odd memory location. BHE

/WRH is only valid during 16-bit

external memory read/write cycles. Also an LSIO pin when not BHE/WRH

.

P5.6/READY Ready input to lengthen external memory cycles, for interfacing with slow or

dynamic memory, or for bus sharing. If the pin is high, CPU operation continues
in a normal manner. If the pin is low prior to the falling edge of CLKOUT, the
memory controller goes into a wait state mode until the next positive transition
in CLKOUT occurs with READY high. When external memory is not used,
READY has no effect. The max number of wait states inserted into the bus
cycle is controlled by the CCR/CCR1. Also an LSIO pin when READY is not
selected.

P5.4/SLPINT Dual function I/O pin. As a bidirectional port pin or as a system function. The

system function is a Slave Port Interrupt Output Pin.

P6.2/T1CLK Dual function I/O pin. Primary function is that of a bidirectional I/O pin,

however, it may also be used as a TIMER1 Clock input. The TIMER1 will
increment or decrement on both positive and negative edges of this pin.

P6.3/T1DIR Dual function I/O pin. Primary function is that of a bidirectional I/O pin,

however, it may also be used as a TIMER1 Direction input. The TIMER1 will
increment when this pin is high and decrements when this pin is low.

PORT1/EPA0– 7 Dual function I/O port pins. Primary function is that of bidirectional I/O. System

function is that of High Speed capture and compare. EPA0 and EPA2 have yet

P6.0– 6.1/EPA8 – 9

another function of T2CLK and T2DIR of the TIMER2 timer/counter.

PORT 0/ACH4 –7 4-bit high impedance input-only port. These pins can be used as digital inputs

and/or as analog inputs to the on-chip A/D converter. These pins are also
used as inputs to OTPROM parts to select the Programming Mode.

P6.3– 6.7/SSIO Dual function I/O ports that have a system function as Synchronous Serial I/O.

Two pins are clocks and two pins are data, providing full duplex capability.

PORT 2 8-bit multi-functional port. All of its pins are shared with other functions.

PORT 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared

with the multiplexed address/data bus which has strong internal pullups.

EPORT 8-bit bidirectional standard and I/O port. These bits are shared with the

extended address bus, A16 – A19. Pin function is selected on a per pin basis.

INTOUT Interrupt Output. This active-low output indicates that a pending interrupt

requires use of the external bus.

SLP0– SLP7 Slave Port Address/Data Bus

6

8XC196NT

ABSOLUTE MAXIMUM RATINGS*

Storage Temperature ААААААААААb60§Ctoa150§C

Voltage from VPPor EA to

V

SS

or ANGND ААААААААААААААb0.5V toa13.0V

Voltage from Any Other Pin

to V

SS

or ANGND ААААААААААААААb0.5 toa7.0V

This includes VPPon ROM and CPU devices

.

Power DissipationАААААААААААААААААААААААААА0.5W

NOTICE: This data sheet contains information on
products in the sampling and initial production phases
of development. The specifications are subject to
change without notice. Verify with your local Intel
Sales office that you have the latest data sheet be­fore finalizing a design.

*

WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex­tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.

OPERATING CONDITIONS

Symbol Parameter Min Max Units

T

A

Ambient Temperature Under Bias 0

a

70

§

C

V

CC

Digital Supply Voltage 4.50 5.50 V

V

REF

Analog Supply Voltage 4.50 5.50 V

F

OSC

Oscillator Frequency 4 20 MHz (Note 4)

NOTE:

ANGND and V

SS

should be nominally at the same potential.

DC CHARACTERISTICS (Under Listed Operating Conditions)

Symbol Parameter Min Typ Max Units Test Conditions

I

CC

VCCSupply Current 90 mA XTAL1e20 MHz,

V

CC

e

V

PP

e

V

REF

e

5.5V

I

REF

A/D Reference Supply Current 5 mA

(While device in Reset)

I

IDLE

Idle Mode Current 40 mA XTAL1e20 MHz,

V

CC

e

V

PP

e

V

REF

e

5.5V

I

PD

Powerdown Mode Current

(6)

50 75 mAV

CC

e

V

PP

e

V

REF

e

5.5V

(11)

V

IL

Input Low Voltage (all pins)

b

0.5V 0.3 V

CC

V For PORT0

(10)

V

IH

Input High Voltage 0.7 V

CC

V

CC

a

0.5 V For PORT0

(10)

V

IH1

Input High Voltage XTAL1 0.7 V

CC

V

CC

a

0.5 V XTAL1 Input Pin Only

(1)

V

IH2

Input High Voltage on RESET 0.7 V

CC

V

CC

a

0.5 V RESET input pin only

V

OL

Output Low Voltage 0.3 V I

OL

e

200 mA

(3,5)

(Outputs Configured as 0.45 V I

OL

e

3.2 mA

Complementary) 1.5 V I

OL

e

7.0 mA

V

OH

Output High Voltage V

CC

b

0.3 V I

OH

eb

200mA

(3,5)

(Outputs Configured as V

CC

b

0.7 V I

OH

eb

3.2 mA

Complementary) V

CC

b

1.5 V I

OH

eb

7.0 mA

I

LI

Input Leakage Current (Std. Inputs)

g

10 mAV

SS

k

V

IN

k

V

CC

I

LI1

Input Leakage Current (Port 0)

g

3 mAV

CC

k

V

IN

k

V

REF

I

IL

Logical 0 Input Current

b

70 mAV

IN

e

0.45V

(1)

7

8XC196NT

DC CHARACTERISTICS (Under Listed Operating Conditions) (Continued)

Symbol Parameter Min Typ Max Units Test Conditions

V

OL1

Output Low Voltage in RESET 0.8 V (Note 7)

V

OH1

SLPINT (P5.4) and HLDA (P2.6) 2.0 V I

OH

e

0.8 mA

(7)

Output High Voltage in RESET

V

OH2

Output High Voltage in RESET V

CC

b

1V V I

OH

eb

6mA

(1)

C

S

Pin Capacitance (Any pin to VSS)10pFf

test

e

1.0 MHz

R

WPU

Weak Pullup Resistance 150K X (Note 6)

R

RST

Reset Pullup 65K 180K X

NOTES:

1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to their not being weakly
pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5, Port6 and EPORT except SPLINT (P5.4) and HLDA
(P2.6).

2. Standard input pins include XTAL1, EA

, RESET, and Port 1/2/5/6 and EPORT when setup as inputs.

3. All bidirectional I/O pins when configured as Outputs (Push/Pull).

4. Device is static and should operate below 1 Hz, but only tested down to 4 MHz.

5. Maximum I

OL/IOH

currents per pin will be characterized and published at a later date.

6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
V

REF

e

V

CC

e

5.5V.

7. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6).

8. TBD

e

To Be Determined.

9. Pullup present during return from powerdown condition.

10. When P0 is used as analog inputs, refer to A/D specifications.

11. For temperatures

k

100§C typical is 10 mA.

8

8XC196NT

8XC196NT ADDITIONAL BUS TIMING MODES

The 8XC196NT device has 3 additional bus timing
modes for external memory interfacing.

MODE 3:

Mode 3 is the standard timing mode. Use this mode
for systems that emulate the 8XC196KR bus tim­ings.

MODE 0:

Mode 0 is the standard timing mode, but 1 (mini­mum) wait state is always inserted in external bus
cycles.

MODE 1:

Mode 1 is the long R/W mode. This mode advances
RD

and WR signals by 1 T

OSC

creatinga2T

OSC

RD/WR low time. ALE is also advanced by 0.5 T

OSC

but ALE high time remains 1 T

OSC

.

MODE 2:

Mode 2 is the long R/W mode with Early Address.
Mode 2 is similar to Mode 1 with respect to RD

,WR,
and ALE signals. Additionally, the address is output
on the bus 0.5 T

OSC

earlier in the bus cycle.

272267– 4

Figure 4. Detailed MODE 1, 2, 3, Comparison

9

8XC196NT

EXPLANATION OF AC SYMBOLS

Each symbol is two pairs of letters prefixed by ‘‘T’’
for time. The characters in a pair indicate a signal
and its condition, respectively. Symbols represent
the time between the two signal/condition points.

Conditions: Signals:

HÐHigh AÐAddress HAÐHLDA
LÐLow BÐBHE LÐALE/ADV
VÐValid BRÐBREQ QÐData Out
XÐNo Longer CÐCLKOUT RDÐRD

Valid DÐDATA WÐWR/WRH/WRI

ZÐFloating GÐBuswidth XÐXTAL1

HÐHOLD

YÐREADY

BUS MODE 0 and 3ÐAC CHARACTERISTICS (Over Specified Operating Conditions)

Test Conditions: Capacitance Load on All Pins

e

100 pF, Rise and Fall Timese10 ns.

The system must meet these specifications to work with the 8XC196NT.

Symbol Parameter Min Max Units

T

AVYV

Address Valid to Ready Setup 2 T

OSC

b

75 ns

(3)

T

YLYH

Non READY Time No Upper Limit ns

T

CLYX

READY Hold after CLKOUT Low 0 T

OSC

b

30 ns

(1)

T

AVGV

Address Valid to BUSWIDTH Setup 2 T

OSC

b

75 ns

(2, 3)

T

LLGV

ALE Low to BUSWIDTH Setup T

OSC

b

60 ns

(2, 3)

T

CLGX

BUSWIDTH Hold after CLKOUT Low 0 ns

T

AVDV

Address Valid to Input Data Valid 3 T

OSC

b

55 ns

(2)

T

RLDV

RD active to input Data Valid T

OSC

b

30 ns

(2)

T

CLDV

CLKOUT Low to Input Data Valid T

OSC

b

60 ns

T

RHDZ

End of RD to Input Data Float T

OSC

ns

T

RHDX

Data Hold after RD High 0 ns

NOTES:

1. If Max is exceeded, additional wait states will occur.

2. If wait states are used, add 2 T

OSC

c

n, where nenumber of wait states.

3. If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2 T

OSC

to the

specification.

10