Intel Corporation N87C196KT, N87C196KS Datasheet

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

November 1995

COPYRIGHT

©

INTEL CORPORATION, 1995

Order Number: 270999-007

87C196KT/87C196KS

ADVANCED 16-BIT CHMOS MICROCONTROLLER

Automotive

(b40§Ctoa125§C Ambient)

Y

High Performance CHMOS 16-Bit CPU

Y

Up to 32 Kbytes of On-Chip EPROM

Y

Up to 1 Kbyte of On-Chip Register RAM

Y

Up to 512 Bytes of Additional RAM
(Code RAM)

Y

Register-Register Architecture

Y

8 Channel/10-Bit A/D with Sample/Hold

Y

37 Prioritized Interrupt Sources

Y

Up to Seven 8-Bit (56) I/O Ports

Y

Full Duplex Serial I/O Port

Y

Dedicated Baud Rate Generator

Y

Interprocessor Communication Slave
Port

Y

Selectable Bus Timing Modes for
Flexible Interfacing

Y

Oscillator Fail Detection Circuitry

Y

High Speed Peripheral Transaction
Server (PTS)

Y

Two Dedicated 16-Bit High-Speed
Compare Registers

Y

10 High Speed Capture/Compare (EPA)

Y

Full Duplex Synchronous Serial I/O
Port (SSIO)

Y

Two Flexible 16-Bit Timer/Counters

Y

Quadrature Counting Inputs

Y

Flexible 8-/16-Bit External Bus
(Programmable)

Y

Programmable Bus (HLD/HLDA)

Y

1.75 ms 16 x 16 Multiply

Y

3 ms 32/16 Divide

Y

68-Pin PLCC Package

The 87C196Kx devices represents the 4th generation of MCSÉ96 microcontroller products implemented on
Intel’s advanced 1 micron process technology. These products are based on the 80C196KB device with
enhancements ideal for automotive applications. The instruction set is a true super set of the 80C196KB with a
few new instructions.

The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-bit CPU. The
87C196KT is composed of the high speed (16 MHz) KX macrocore as well as the following peripherals: Up to
32 Kbytes of Program EPROM, up to 1 Kbytes of Register RAM (00-3FFH including SFRs), up to 512 bytes of
code RAM (16-bit addressing modes) with the ability to execute from this RAM space, an eight channel-10 Bit

g

3LSB analog to digital converter with programmable S/H times with conversion timesk20 ms at 16 MHz, an
asynchronous/synchronous serial I/O port (8096 compatable) with a dedicated 16-bit baud rate generator, an
additional synchronous serial I/O port with full duplex master/slave transceivers, a flexible timer/counter
structure with prescaler, cascading, and quadrature capabilities, 10 modularized multiplexed high speed I/O
for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs,
and a sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS). The
PTS has several channel modes, including single/burst block transfers from any memory location to any
memory location, a PWM and PWM toggle mode to be used in conjunction with the EPA, and an A/D scan
mode.

Additional SFR space is allocated for the EPA and can be ‘‘windowed’’ into the lower Register RAM area.

NOTICE:

This datasheet contains information on products in production. The specifications are subject to change
without notice. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a
design.

1

87C196KT/87C196KS

Device Pins/Package EPROM Reg RAM Code RAM I/O EPA SIO SSIO A/D

87C196KT 68-Pin PLCC 32K 1K 512b 56 10 Y Y 8

87C196KS 68-Pin PLCC 24K 1K 256b 56 10 Y Y 8

NOTE:

This is a PRODUCT PREVIEW DATA SHEET. The AC and DC parameters contained within this data sheet may change
after full automotive temperature characterization of the device has been performed. Contact your local sales office before
finalizing the Timing and D.C. characteristics of a design to verify you have the latest information.

ARCHITECTURE

The KT/KS are new members of the MCS-96 family
having the same architecture and use the same in­struction set as the 80C196KB. Many new features
have been added including:

CPU FEATURES

Y

Powerdown and Idle Modes

Y

16 MHz Operating Frequency

Y

A High Performance Peripheral
Transaction Server (PTS)

Y

37 Interrupt Vectors

Y

Up to 512 Bytes of Additional Code
RAM

Y

Up to 1 Kbyte of Additional Register
RAM

Y

‘‘Windowing’’ Allows 8-Bit Addressing
to some 16-Bit Addresses

Y

1.75 ms 16 x 16 Multiply

Y

3 ms 32/16 Divide

Y

Oscillator Fail Detect Circuitry

PERIPHERAL FEATURES

Ð Programmable A/D Conversion and S/H Times

Ð 10 Capture/Compare I/O with 2 Flexible Timers

(250 ns Resolution and Double Buffered Inputs)

Ð Synchronous Serial I/O Port for Full Duplex Seri-

al I/O

Ð Synchronous/Asynchronous Serial I/O Port

(with Dedicated 16-Bit Baud Rate Generator)

Ð Total Utilization of ALL Available Pins (I/O Mux’d

with Control)

Ð (2) 16-Bit Timers with Prescale, Cascading, and

Quadrature Counting Capabilities

Ð Up to 12 Externally Triggered Interrupts

NEW INSTRUCTIONS

XCH/XCHB Exchange the contents of two loca-

tions, either Word or Byte is support­ed.

BMOVI Interruptable Block Move Instruction,

allows the user to be interrupted dur­ing long executing Block Moves.

TIJMP Table Indirect JUMP. This instruction

incorportes a way to do complex
CASE level branches through one in­struction. An example of such code
savings: several interrupt sources and
only one interrupt vector. The TIJMP
instruction will sort through the sourc­es and branch to the appropriate sub­code level in one instruction. This in­struction was added especially for the
EPA structure, but has other code sav­ing advantages.

EPTS/DPTS Enable and Disable Interrupts (Works

like EI and DI).

SFR OPERATION

A total of 1 Kbyte of Register RAM is implemented
on the 87C196KT/KS devices. These locations sup­port the on-chip peripherals that the 87C196KT/KS
has (SFR’s), as well as offering a data storage area.
These locations are all 8-bit directly addressable by
use of the windowing technique. Any 32-, 64- or 128­byte section can be relocated into the upper 32-, 64­or 128-byte area of the Register RAM area 080H –
0FFH.

2

2

87C196KT/87C196KS

87C196KT Block Diagram

270999– 1

270999– 2

3

3

87C196KT/87C196KS

PIN DESCRIPTIONS

Symbol Name and Function

V

CC

Main supply voltage (a5V).

VSS,V

SSI,VSSI

Digital circuit ground (0V). There are three VSSpins, all of which MUST be connected.

V

REF

Reference for the A/D converter (a5V). V

REF

is also the supply voltage to the analog
portion of the A/D converter and the logic used to read Port 0. Must be connected for
A/D and Port 0 to function.

V

PP

Programming voltage for the EPROM parts. It should bea12.5V for programming. It
is also the timing pin for the return from powerdown circuit. Connect this pin with a
1 mF capacitor to V

SS

anda1MXresistor to VCC. If this function is not used, V

PP

may be tied to VCC.

ANGND Reference ground for the A/D converter. Must be held at nominally the same

potential as V

SS

.

XTAL1 Input of the oscillator inverter and the internal clock generator.

XTAL2 Output of the oscillator inverter.

P2.7/CLKOUT Output of the internal clock generator. The frequency is (/2 the oscillator frequency. It

has a 50% duty cycle. Also LSIO pin.

RESET Reset input to the chip. Input low for at least 16 state times will reset the chip. The

subsequent low to high transition resynchronizes CLKOUT and commences a 10­state time sequence in which the PSW is cleared, bytes are read from 2018H and
201AH loading the CCBs, and a jump to location 2080H is executed. Input high for
normal operation. RESET

has an internal pullup.

P5.7/BUSWIDTH Input for bus width selection. If CCR bit 1 is a one and CCR1 bit 2 is a one, this pin

dyamically controls the Buswidth of the bus cycle in progress. If BUSWIDTH is low, an
8-bit cycle occurs, if BUSWIDTH is high, a 16-bit cycle occurs. If CCR bit 1 is ‘‘0’’ and
CCR1 bit 2 is ‘‘1’’, all bus cycles are 8-bit, if CCR bit 1 is ‘‘1’’ and CCR1 bit 2 is ‘‘0’’, all
bus cycles are 16-bit. CCR bit 1e‘‘0’’ and CCR1 bit 2e‘‘0’’ is illegal. Also an LSIO
pin when not used as BUSWIDTH.

NMI A positive transition causes a non maskable interrupt vector through memory location

203EH.

P5.1/INST Output high during an external memory read indicates the read is an instruction fetch.

INST is valid throughout the bus cycle. INST is active only during external memory
fetches, during internal EPROM fetches INST is held low. Also LSIO when not INST.

EA Input for memory select (External Access). EA equal to a high causes memory

accesses to locations 2000H through 9FFFH to be directed to on-chip EPROM/ROM.
EA

equal to a low causes accesses to these locations to be directed to off-chip

memory. EA

ea

12.5V causes execution to begin in the Programming Mode. EA is

latched at reset.

P5.0/ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options

provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV, it goes inactive (high) at the end of the bus cycle. ADV can be used as a chip
select for external memory. ALE/ADV

is active only during external memory

accesses. Also LSIO when not used as ALE.

P5.3/RD Read signal output to external memory. RD is active only during external memory

reads or LSIO when not used as RD

.

P5.2/WR/WRL Write and Write Low output to external memory, as selected by the CCR, WR will go

low for every external write, while WRL

will go low only for external writes where an
even byte is being written. WR/WRL is active during external memory writes. Also an
LSIO pin when not used as WR

/WRL.

4

4

87C196KT/87C196KS

PIN DESCRIPTIONS (Continued)

Symbol Name and Function

P5.5/BHE/WRH Byte High Enable or Write High output, as selected by the CCR. BHEe0 selects the

bank of memory that is connected to the high byte of the data bus. A0

e

0 selects
that bank of memory that is connected to the low byte. Thus accesses to a 16-bit
wide memory can be to the low byte only (A0

e

0, BHEe1), to the high byte only

(A0

e

1, BHEe0) or both bytes (A0e0, BHEe0). If the WRH function is selected,

the pin will go low if the bus cycle is writing to an odd memory location. BHE

/WRH is
only valid during 16-bit external memory write cycles. Also an LSIO pin when not
BHE/WRH

.

P5.6/READY Ready input to lengthen external memory cycles, for interfacing with slow or

dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in a
normal manner. If the pin is low prior to the falling edge of CLKOUT, the memory
controller goes into a wait state mode until the next positive transition in CLKOUT
occurs with READY high. When external memory is not used, READY has no effect.
The max number of wait states inserted into the bus cycle is controlled by the CCR/
CCR1. Also an LSIO pin when READY is not selected.

P5.4/SLPINT Dual function I/O pin. As a bidirectional port pin or as a system function. The system

function is a Slave Port Interrupt Output Pin.

P6.2/T1CLK Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it

may also be used as a TIMER1 Clock input. The TIMER1 will increment or
decrement on both positive and negative edges of this pin.

P6.3/T1DIR Dual function I/O pin. Primary function is that of a bidirectional I/O pin, however, it

may also be used as a TIMER1 Direction input. The TIMER1 will increment when
this pin is high and decrements when this pin is low.

PORT1/EPA0–7 Dual function I/O port pins. Primary function is that of bidirectional I/O. System

function is that of High Speed capture and compare. EPA0 and EPA2 have yet

P6.0–6.1/EPA8– 9

another function of T2CLK and T2DIR of the TIMER2 timer/counter.

PORT 0/ACH0 – 7 8-bit high impedance input-only port. These pins can be used as digital inputs and/or

as analog inputs to the on-chip A/D converter. These pins are also used as inputs to
EPROM parts to select the Programming Mode.

P6.3–6.7/SSIO Dual function I/O ports that have a system function as Synchronous Serial I/O. Two

pins are clocks and two pins are data, providing full duplex capability.

PORT 2 8-bit multi-functional port. All of its pins are shared with other functions.

PORT 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the

multiplexed address/data bus which has strong internal pullups.

5

5

87C196KT/87C196KS

CCB (2018H : Byte)

0PDe‘‘1’’ Enables Powerdown

1 BW0

e

See Table

2WRe‘‘1’’eWR/BHE - ‘‘0’’eWRL/WRH

3 ALE

e

‘‘1’’eALE - ‘‘0’’eADV

4 IRC0

e

See Table

5 IRC1

e

(

6 LOC0

e

See Table

7 LOC1

e

(

CCB1 (201AH : Byte)

00eReserved Must Be ‘‘0’’

1 IRC2

e

See Table

2 BW1

e

See Table

3 WDE

e

‘‘0’’eAlways Enabled

41

e

Reserved Must Be ‘‘01’’

50

e

(

6 MSEL0

e

See Table

7 MSEL1

e

(

LOC1 LOC0 Function

0 0 Read and Write Protected
0 1 Write Protected Only
1 0 Read Protected Only
1 1 No Protection

IRC2 IRC1 IRC0 Max Wait States

0 0 0 Zero Wait States
1 0 0 1 Wait State
1 0 1 2 Wait States
1 1 0 3 Wait States
1 1 1 INFINITE

MSEL1 MSEL0 Bus Timing Mode

0 0 Mode 0 (1-Wait KR)
0 1 Mode 1
1 0 Mode 2
1 1 Mode 3 (KR)

BW1 BW0 Bus Width

0 0 ILLEGAL
0 1 16-Bit Only
1 0 8-Bit Only
1 1 BW Pin Controlled

Mode 0 Designed to be similar to the 87C196KR bus
(1-Wait KR): timing with 1 automatic wait state.

See AC Timings section for actual timings data.

Mode 1: RD,WR, advanced 1 T

OSC

ALE advanced 0.5 T

OSC

ALE pulse width remains 1 T

OSC

Mode 2: RD,WR, advanced 1 T

OSC

ALE advanced 0.5 T

OSC

ALE pulse width remains 1 T

OSC

Address advanced 0.5 T

OSC

Mode 3 (KR): Designed to be similar to the 87C196KR bus

timing.

See AC Timings section for actual timings data.

6

6

87C196KT/87C196KS

ABSOLUTE MAXIMUM RATINGS*

Storage Temperature ААААААААААb60§Ctoa150§C

Voltage from VPPor EA to

V

SS

or ANGND ААААААААААААААb0.5V toa13.0V

Voltage from Any Other Pin

to V

SS

or ANGND ААААААААААААААb0.5 toa7.0V

This includes VPPon ROM and CPU devices

.

Power DissipationАААААААААААААААААААААААААА0.5W

NOTICE: This is a production data sheet. The specifi­cations are subject to change without notice.

*

WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and ex­tended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.

OPERATING CONDITIONS

Symbol Parameter Min Max Units

T

A

Ambient Temperature Under Bias

b

40

a

125

§

C

V

CC

Digital Supply Voltage 4.50 5.50 V

V

REF

Analog Supply Voltage 4.50 5.50 V

F

OSC

Oscillator Frequency 4 16 MHz (Note 4)

NOTE:

ANGND and V

SS

should be nominally at the same potential.

DC CHARACTERISTICS (Under Listed Operating Conditions)

Symbol Parameter Test Conditions Min Typ Max Units

I

CC

VCCSupply Current XTAL1e16 MHz, 82 mA
(

b

40§Ctoa125§C Ambient) V

CC

e

V

PP

e

V

REF

e

5.5V

I

REF

A/D Reference Supply Current

(While device in Reset)

5mA

I

IDLE

Idle Mode Current XTAL1e16 MHz, 40 mA

V

CC

e

V

PP

e

V

REF

e

5.5V

I

PD

Powerdown Mode Current V

CC

e

V

PP

e

V

REF

e

5.5V

(6, 9)

50 TBD mA

V

IL

Input Low Voltage (all pins) For PORT0

(8)

b

0.5V 0.3 V

CC

V

V

IH

Input High Voltage For PORT0

(8)

0.7 V

CC

V

CC

a

0.5 V

V

IH1

Input High Voltage XTAL1 XTAL1 Input Pin Only

(1)

0.7 V

CC

V

CC

a

0.5 V

V

IH2

Input High Voltage on RESET RESET input pin only 0.7 V

CC

V

CC

a

0.5 V

7

7

87C196KT/87C196KS

DC CHARACTERISTICS (Under Listed Operating Conditions) (Continued)

Symbol Parameter Test Conditions Min Typ Max Units

V

OL

Output Low Voltage I

OL

e

200 mA

(3,5)

0.3 V

(Outputs Configured as I

OL

e

3.2 mA 0.45 V

Complementary) I

OL

e

7.0 mA 1.5 V

V

OH

Output High Voltage I

OH

eb

200 mA

(3,5)

V

CC

b

0.3 V

(Outputs Configured as I

OH

eb

3.2 mA V

CC

b

0.7 V

Complementary) I

OH

eb

7.0 mA V

CC

b

1.5 V

I

LI

Input Leakage Current (Std. Inputs) V

SS

k

V

IN

k

V

CC

g

10 mA

I

LI1

Input Leakage Current (Port 0) V

SS

k

V

IN

k

V

REF

g

1.5 mA

V

OH1

SLPINT (P5.4) and HLDA (P2.6) I

OH

e

0.8 mA

(7)

2.0 V

Output High Voltage in RESET

V

OH2

Output High Voltage in RESET I

OH

eb

15 mA

(1,8)

V

CC

b

1V V

I

OH2

Output High Current in RESET V

OH2

e

V

CC

b

1.0V

b

30

b

120 mA

V

OH2

e

V

CC

b

2.5V

b

75

b

240 mA

V

OH2

e

V

CC

b

4.0V

b

90

b

280 mA

C

S

Pin Capacitance (Any pin to VSS)f

test

e

1.0 MHz

(6)

10 pF

V

OL3

Output Low Voltage in RESET I

OL3

e

4mA

(10)

0.3

(RESET Pin Only) I

OL3

e

6 mA 0.5 V

I

OL3

e

8 mA 0.8

R

WPU

Weak Pullup Resistance (Note 6) 150K X

R

RST

Reset Pullup Resistor 65K 180K X

NOTES:

1. All BD (bidirectional) pins except INST and CLKOUT. INST and CLKOUT are excluded due to their not being weakly
pulled high in reset. BD pins include Port1, Port2, Port3, Port4, Port5 and Port6 except SPLINT (P5.4) and HLDA (P2.6).

2. Standard input pins include XTAL1, EA

, RESET, and Port 1/2/5/6 when setup as inputs.

3. All bidirectional I/O pins when configured as Outputs (Push/Pull).

4. Device is static and should operate below 1 Hz, but only tested down to 4 MHz.

5. Maximum I

OL/IOH

currents per pin will be characterized and published at a later date.

6. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and
V

REF

e

V

CC

e

5.0V.

7. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6).

8. When P0 is used as analog inputs, refer to A/D specifications for this characteristic.

9. For temperatures

k

100§C typical is 10 mA.

10. This specification is not tested in production and is based upon theoretical estimates and/or product characterization.

ICCvs Frequency

270999– 24

NOTES:

ICCMaxe3.25cFreqa30
I

IDLE

Maxe1.25cFreqa20

8

8

87C196KT/87C196KS

AC CHARACTERISTICS (Over Specified Operating Conditions)

Test Conditions: Capacitance Load on All Pins

e

100 pF, Rise and Fall Timese10 ns.

The 87C196KT will meet these specifications

Symbol Parameter Min Max Units

F

XTAL

Frequency on XTAL1 4.0 16.0 MHz

(1)

T

OSC

XTAL1 Period (1/F

XTAL

) 62.5 250 ns

T

XHCH

XTAL1 High to CLKOUT High or Low

a

20 110 ns

T

OFD

Clock Failure to Reset Pulled Low

(6)

440ms

T

CLCL

CLKOUT Period 2 T

OSC

ns

T

CHCL

CLKOUT High Period T

OSC

b

10 T

OSC

a

30 ns

T

CLLH

CLKOUT Low to ALE/ADV High

b

10

a

15 ns

T

LLCH

ALE/ADV Low to CLKOUT High

b

25

a

15 ns

T

LHLH

ALE/ADV Cycle Time 4 T

OSC

ns

(5)

T

LHLL

ALE/ADV High Time T

OSC

b

10 T

OSC

a

10 ns

T

AVLL

Address Valid to ALE Low T

OSC

b

15 ns

T

LLAX

Address Hold After ALE/ADV Low T

OSC

b

40 ns

T

LLRL

ALE/ADV Low to RD Low T

OSC

b

40 ns

T

RLCL

RD Low to CLKOUT Low

b

5

a

35 ns

T

RLRH

RD Low Period T

OSC

b

5ns

(5)

T

RHLH

RD High to ALE/ADV High T

OSC

T

OSC

a

25 ns

(3)

T

RLAZ

RD Low to Address Float

a

5ns

T

LLWL

ALE/ADV Low to WR Low T

OSC

b

10 ns

T

CLWL

CLKOUT Low to WR Low

b

10

a

25 ns

T

QVWH

Data Valid before WR High T

OSC

b

23 ns

T

CHWH

CLKOUT High to WR High

b

10

a

15 ns

T

WLWH

WR Low Period T

OSC

b

30 ns

(5)

T

WHQX

Data Hold after WR High T

OSC

b

30 ns

T

WHLH

WR High to ALE/ADV High T

OSC

b

10 T

OSC

a

15 ns

(3)

T

WHBX

BHE, INST Hold after WR High T

OSC

b

10 ns

T

WHAX

AD8–15 Hold after WR High T

OSC

b

30 ns

(4)

T

RHBX

BHE, INST Hold after RD High T

OSC

b

10 ns

T

RHAX

AD8–15 Hold after RD High T

OSC

b

30 ns

(4)

NOTES:

1. Testing performed at 4.0 MHz, however, the device is static by design and will typically operate below 1 Hz.

2. Typical specifications, not guaranteed.

3. Assuming back-to-back bus cycles.

4. 8-bit bus only.

5. If wait states are used, add 2 Tosc

c

n, where nenumber of wait states. If mode 0 (1 automatic wait state added)

operation is selected, add 2 T

OSC

to specification.

6. T

OFD

is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. The OFD circuitry is enabled by
programming the UPROM location 0778H with the value 0004H. KT/KS customer QROM codes need to equate location
2016H to the value 0CDEH if the oscillator fail detect (OFD) function is desired. Intel manufacturing uses location 2016H
as a flag to determine whether or not to program the Clock Detect Enable (CDE) bit. Programming the CDE bit
enables oscillator fail detection.

9

9

87C196KT/87C196KS

AC CHARACTERISTICS (Over Specified Operating Conditions)

Test Conditions: Capacitance Load on All Pins

e

100 pF, Rise anf Fall Timese10 ns.

The system must meet these specifications to work with the 87C196KT.

Symbol Parameter Min Max Units

T

AVYV

Address Valid to Ready Setup 2 T

OSC

b

75 ns

(3)

T

LLYV

ALE Low to READY Setup T

OSC

b

70 ns

(3)

T

YLYH

Non READY Time No Upper Limit ns

T

CLYX

READY Hold after CLKOUT Low 0 T

OSC

b

30 ns

(1)

T

AVGV

Address Valid to BUSWIDTH Setup 2 T

OSC

b

75 ns

(2, 3)

T

LLGV

ALE Low to BUSWIDTH Setup T

OSC

b

60 ns

(2, 3)

T

CLGX

BUSWIDTH Hold after CLKOUT Low 0 ns

T

AVDV

Address Valid to Input Data Valid 3 T

OSC

b

55 ns

(2)

T

RLDV

RD active to input Data Valid T

OSC

b

30 ns

(2)

T

CLDV

CLKOUT Low to Input Data Valid T

OSC

b

60 ns

T

RHDZ

End of RD to Input Data Float T

OSC

ns

T

RHDX

Data Hold after RD High 0 ns

NOTES:

1. If Max is exceeded, additional wait states will occur.

2. If wait states are used, add 2 Tosc

c

n, where nenumber of wait states.

3. If mode 0 is selected, one wait state minimum is always added. If additional wait states are required, add 2 Tosc to the
specification.

10

10

87C196KT/87C196KS

87C196KT SYSTEM BUS TIMING

270999– 4

* If mode 0 operation is selected, add 2 Tosc to this time.

11

11