Intel Corporation N80C452 Datasheet

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
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changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

November 1994COPYRIGHT©INTEL CORPORATION, 1996 Order Number: 231428-006

UPI-452

CHMOS PROGRAMMABLE I/O PROCESSOR

83C452 - 8Kc8 Mask Programmable Internal ROM

80C452 - External ROM/EPROM

Y

83C452/80C452:3.5 to 14 MHz Clock
Rate

Y

Software Compatible with the MCS-51
Family

Y

128-Byte Bi-Directional FIFO Slave
Interface

Y

Two DMA Channels

Y

256c8-Bit Internal RAM

Y

34 Additional Special Function
Registers

Y

40 Programmable I/O Lines

Y

Two 16-Bit Timer/Counters

Y

Boolean Processor

Y

Bit Addressable RAM

Y

8 Interrupt Sources

Y

Programmable Full Duplex Serial
Channel

Y

64K Program Memory Space

Y

64K Data Memory Space

Y

68-Pin PGA and PLCC

(See Packaging Spec., Order:Ý231369)

The Intel UPI-452 (Universal Peripheral Interface) is a 68 pin CHMOS Slave I/O Processor with a sophisticated
bi-directional FIFO buffer interface on the slave bus and a two channel DMA processor on-chip. The UPI-452
is the newest member of Intel’s UPI family of products. It is a general-purpose slave I/O Processor that allows
the designer to grow a customized interface solution.

The UPI-452 contains a complete 80C51 with twice the on-chip data and program memory. The sophisticated
slave FIFO module acts as a buffer between the UPI-452 internal CPU and the external host CPU. To both the
external host and the internal CPU, the FIFO module looks like a bi-directional bottomless buffer that can both
read and write data. The FIFO manages the transfer of data independent of the UPI-452 core CPU and
generates an interrupt or DMA request to either CPU, host or internal, as a FIFO service request.

The FIFO consists of two channels:the Input FIFO and the Output FIFO. The division of the FIFO module
array, 128 bytes, between Input channel and Output channel is programmable by the user. Each FIFO byte
has an additional logical ninth bit to distinguish between a data byte and a Data Stream Command byte.
Additionally, Immediate Commands allow direct, interrupt driven, bi-directional communication between the
UPI-452 internal CPU and external host CPU, bypassing the FIFO.

The on-chip DMA processor allows high speed data transfers from one writeable memory space to another.
As many as 64K bytes can be transferred in a single DMA operation. Three distinct memory spaces may be
used in DMA operations; Internal Data Memory, External Data Memory, and the Special Function Registers
(including the FIFO IN, FIFO OUT, and Serial Channel Special Functions Registers).

UPI-452

231428– 1

Figure 1. Architectural Block Diagram

2

UPI-452

231428– 2

Figure 1. Architectural Block Diagram (Continued)

3

UPI-452

TABLE OF CONTENTS

CONTENTS PAGE

Introduction

АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 1

Table of Contents АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 4
List of Tables and Figures АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 5
Pin Description ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 7
Architectural Overview АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 10

Introduction АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 10
FIFO Buffer Interface ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 10
FIFO Programmable Features АААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 11
Immediate Commands ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 12
DMA ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 12

FIFO/Slave Interface Functional Description ААААААААААААААААААААААААААААААААААААААААААААААА 12

Overview АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 12
Input FIFO Channel АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 13
Output FIFO Channel АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 14
Immediate Commands ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 16
Host & Slave Interface Special Function Registers АААААААААААААААААААААААААААААААААААААА 18

Slave Interface Special Function Registers АААААААААААААААААААААААААААААААААААААААААА 18
External Host Interface Special Function Registers АААААААААААААААААААААААААААААААААА 20

FIFO ModuleÐExternal Host Interface ААААААААААААААААААААААААААААААААААААААААААААААААА 22

Overview ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 22
Slave Interface Address Decoding ААААААААААААААААААААААААААААААААААААААААААААААААААА 22
Interrupts to the Host АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 22
DMA Requests to the Host АААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 24

FIFO ModuleÐInternal CPU Interface АААААААААААААААААААААААААААААААААААААААААААААААААА 24

Overview ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 24
Internal CPU Access to FIFO via Software Instructions ААААААААААААААААААААААААААААААА 24

General Purpose DMA Channels АААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 25

Overview АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 25
Architecture АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 25
DMA Special Function Registers ААААААААААААААААААААААААААААААААААААААААААААААААААААААА 26
DMA Transfer Modes АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 27
External Memory DMA ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 29
Latency АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 29
DMA Interrupt Vectors ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 29
Interrupts When DMA is Active ААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 30
DMA Arbitration АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 30

Interrupts ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 32

Overview АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 32
FIFO Module Interrupts to Internal CPU ААААААААААААААААААААААААААААААААААААААААААААААААА 32
Interrupt Enabling and Priority АААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 33

FIFOÐExternal Host Interface FIFO DMA Freeze Mode ААААААААААААААААААААААААААААААААААА 35

Overview АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 35
Initialization АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 35
Invoking FIFO DMA Freeze Mode During Normal Operation ААААААААААААААААААААААААААААА 36
FIFO Module Special Function Register Operation During FIFO DMA Freeze Mode АААААА 37
Internal CPU Read & Write of the FIFO During FIFO DMA Freeze Mode ААААААААААААААААА 41

Memory Organization АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 41
Accessing External Memory АААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 41
Miscellaneous Special Function Register Descriptions АААААААААААААААААААААААААААААААААА 43

4

UPI-452

LIST OF TABLES AND FIGURES

Figures:

1. Architectural Block Diagram АААААААААААААААААААААААААААААААААААААААААААААААААААААААА 2

2. UPI 452 68-Pin PLCC Pinout Diagram АААААААААААААААААААААААААААААААААААААААААААААА 6

3. UPI-452 Conceptual Block Diagram ААААААААААААААААААААААААААААААААААААААААААААААА 10

4. UPI-452 Functional Block Diagram АААААААААААААААААААААААААААААААААААААААААААААААА 11

5. Input FIFO Channel Functional Block Diagram ААААААААААААААААААААААААААААААААААААА 13

6. Output FIFO Channel Functional Block Diagram ААААААААААААААААААААААААААААААААААА 15
7a. Handshake Mechanisms for Handling Immediate Command IN Flowchart АААААААААА 17
7b. Handshake Mechanisms for Handling Immediate Command OUT Flowchart ААААААА 17

8. DMA Transfer from: External to External Memory АААААААААААААААААААААААААААААААААА 31

9. DMA Transfer from: External to Internal Memory ААААААААААААААААААААААААААААААААААА 31

10. DMA Transfer from: Internal to External Memory АААААААААААААААААААААААААААААААААА 31

11. DMA Transfer Waveform: Internal to Internal Memory ААААААААААААААААААААААААААААА 32

12. Disabling FIFO to Host Slave Interface Timing Diagram АААААААААААААААААААААААААААА 36

Tables:

1. Input FIFO Channel Registers ААААААААААААААААААААААААААААААААААААААААААААААААААААА 13

2. Output FIFO Channel Registers ААААААААААААААААААААААААААААААААААААААААААААААААААА 15

3. UPI-452 Address Decoding ААААААААААААААААААААААААААААААААААААААААААААААААААААААА 23

4. DMA Accessible Special Function Registers ААААААААААААААААААААААААААААААААААААААА 26

5. DMA Mode Control - PCON SFR АААААААААААААААААААААААААААААААААААААААААААААААААА 29

6. Interrupt Priority ААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААААА 32

7. Interrupt Vector Addresses АААААААААААААААААААААААААААААААААААААААААААААААААААААААА 32

8. Slave Bus Interface Status During FIFO DMA Freeze Mode АААААААААААААААААААААААА 35

9. FIFO SFR’s Characteristics During FIFO DMA Freeze Mode ААААААААААААААААААААААА 38

10. Threshold SFRs Range of Values and Number of Bytes to be Transferred АААААААААА 39
11a. Internal Memory Addressing АААААААААААААААААААААААААААААААААААААААААААААААААААААА 41
11b. 80C51 Special Function Registers АААААААААААААААААААААААААААААААААААААААААААААААА 42
11c. UPI-452 Additional Special Function Registers АААААААААААААААААААААААААААААААААААА 42

12. Program Status Word (PSW) АААААААААААААААААААААААААААААААААААААААААААААААААААААА 44

13. PCON Special Function Register АААААААААААААААААААААААААААААААААААААААААААААААААА 44

5

UPI-452

P.C. Board ViewÐAs Viewed from the Component Side of the P.C. Board

(Underside of Socket)

231428– 32

Figure 2. UPI 452 68-Pin PLCC Pinout Diagram

6

UPI-452

UPI MICROCONTROLLER FAMILY

The UPI-452 joins the current members of the UPI
microcontroller family. UPI’s are derivatives of the
MCS

TM

family of microcontrollers. Because of their
on-chip system bus interface, UPI’s are designed to
be system bus ‘‘slaves’’, while their microcontroller
counterparts are intended as system bus ‘‘masters’’.

These UPI Microcontrollers are fully supported by
Intel’s development tools (ICE, ASM and PLM).

Packaging

The 80C452/83C452 is available in a 68-pin PLCC
package.

UPI Family MCS Family

RAM ROM

(Slave (Master Speed

(Bytes) (Bytes)

Configuration) Configuration)

80C452 80C51 12 MHz 256 Ð

83C452 80C51 12 MHz 256 8K

80C452-1 80C51 14 MHz 256 Ð

83C452-1 80C51 14 MHz 256 8K

UPI-452 PIN DESCRIPTIONS

Symbol Pin

Ý

Type Name and Function

V

SS

9/43 I Circuit Ground.

V

CC

60 I

a

5V power supply during normal and idle mode operation. It is also

the standby power pin for power down mode.

XTAL1 38 I Input to the oscillator’s high gain amplifier. A crystal or external

source can be used.
XTAL2 39 O Output from the high gain amplifier.
Port 0 I/O Port 0 is an 8-bit open drain bi-directional I/O port. Port 0 can sink

(AD0–AD7)

eight LS TTL inputs. It is also the multiplexed low-order address and
P0.0 8

data local expansion bus during accesses to external memory.

.1 10
.2 11
.3 12
.4 13
.5 14
.6 15

P0.7 16

7

UPI-452

UPI-452 PIN DESCRIPTIONS (Continued)

Symbol Pin

Ý

Type Name and Function

Port 1 I/O Port 1 is an 8-bit quasi-bi-directional I/O port. Port 1 can sink four
(A0–A7)

LS TTL inputs. The alternate functions can only be activated if the
(HLD

, HLDA)

corresponding bit latch in the port SFR contains a 1. Otherwise, the
P1.0 7

port pin is stuck at 0. Pins P1.5 and P1.6 are multiplexed with HLD

and HLDA respectively whose functions are defined as below:

.1 6 Port Pin Alternate Function
.2 5 P1.5 HLD ÐLocal bus hold
.3 4 input/output signal
.4 3 P1.6 HLDA

ÐLocal bus hold
.5 2 acknowledge input
.6 1

P1.7 68
Port 2 I/O Port 2 is an 8-bit quasi-bi-directional I/O port. It also emits the high-

(A8–A15)

order 8 bits of address when accessing local expansion bus

P2.0 29

external memory. Port 2 can sink four LS TTL inputs.
.1 28
.2 27
.3 25
.4 24
.5 23
.6 22
.7 21

Port 3 I/O Port 3 is an 8-bit quasi-bi-directional I/O port. It is also multiplexed
P3.0 67

with the interrupt, timer, local serial channel, RD/ and WR/
.1 66

functions that are used by various options. The alternate functions
.2 65

can only be activated if the corresponding bit latch in the port SFR
.3 64

contains a 1. Otherwise, the port pin is stuck at 0. Port 3 can sink
.4 63

four LS TTL inputs. The alternate functions assigned to the pins of
.5 62

Port 3 are as follows:
.6 61

Port Pin Alternate Function

P3.7 59

P3.0 RxD Ð Serial input port

P3.1 TxD Ð Serial output port

P3.2 INT0 Ð Interrupt 0 Input

P3.3 INT1 Ð Interrupt 1 Input

P3.4 T0 Ð Input to counter 0

P3.5 T1 Ð Input to counter 1

P3.6 WR/ Ð The write control signal latches the

data from Port 0 outputs into the
External Data Memory on the
local bus.

P3.7 RD/ Ð The read control signal latches the

data from Port 0 outputs on the
local bus.

8

UPI-452

UPI-452 PIN DESCRIPTIONS (Continued)

Symbol Pin

Ý

Type Name and Function

Port 4 I/O Port 4 is an 8-bit quasi-bi-directional I/O port. Port 4 can sink/
P4.0 30

source four TTL inputs.
.1
.2 32
.3 33
.4 34
.5 35
.6 36
.7 37

RST 20 I A high level on this pin for two machine cycles while the oscillator is

running resets the device. An internal pulldown resistor permits

Power-on reset using only a capacitor connected to V

CC

.
This pin does not receive the power down voltage as is the case for
HMOS MCS-51 family members. This function has been transferred
to the VCCpin.

ALE 18 O Provides Address Latch Enable output used for latching the

address into external memory during normal operation. ALE can
sink/source eight LS TTL inputs.

PSEN 19 O The Program Store Enable output is a control signal that enables

the external Program Memory to the bus during normal fetch
operation. PSEN

can sink/source eight LS TTL inputs.

EA 17 I When held at TTL high level, the UPI-452 executes instructions

from the internal ROM when the PC is less than 8192 (8K, 2000H).
When held at a TTL low level, the UPI-452 fetches all instructions
from external Program Memory.

DB0 58 I/O Host Bus Interface is an 8-bit bi-directional bus. It is used to transfer
DB1 57

data and commands between the UPI-452 and the host processor.

DB2 56

This bus can sink/source eight LS TTL inputs.

DB3 55
DB4 54
DB5 53
DB6 52
DB7 51

CS 44 I This pin is the Chip Select of the UPI-452.
A0 40 I These three address lines are used to interface with the host

A1 41

system. They define the UPI-452 operations. The interface is

A2 42

compatible with the Intel microprocessors and the MULTIBUS.

READ 46 I This pin is the read strobe from the host CPU. Activating this pin

causes the UPI-452 to place the contents of the Output FIFO (either
a command or data) or the Host Status/Control Special Function
Register on the Slave Data Bus.

WRITE 47 I This pin is the write strobe from the host. Activating this pin will

cause the value on the Slave Data Bus to be written into the register
specified by A0 – A2.

DRQIN/ 49 O This pin requests an input transfer from the host system whenever
INTRQIN

the Input Channel requires data.

DRQOUT/ 48 O This output pin requests an output transfer whenever the Output
INTRQOUT

Channel requires service. If the external host to UPI-452 DMA is
enabled, and a Data Stream Command is at the Output FIFO,
DRQOUT is deactivated and INTRQ is activated (see ‘GENERAL
PURPOSE DMA CHANNELS’ section).

9

UPI-452

UPI-452 PIN DESCRIPTIONS (Continued)

Symbol Pin

Ý

Type Name and Function

INTRQ 50 O This output pin is used to interrupt the host processor when an

Immediate Command Out or an error condition is encountered. It is
also used to interrupt the host processor when the FIFO requests
service if the DMA is disabled and INTRQIN and INTRQOUT are
not used.

DACK 45 I This pin is the DMA acknowledge for the host bus interface Input

and Output Channels. When activated, a write command will cause
the data on the Slave Data Bus to be written as data to the Input
Channel (to the Input FIFO). A read command will cause the Output
Channel to output data (from the Output FIFO) on to the Slave Data
Bus. This pin should be driven high (

a

5V) in systems which do not

have a DMA controller (see Address Decoding).

V

CC

26 I

a

5V power supply during operation.

ARCHITECTURAL OVERVIEW

Introduction

The UPI-452 slave microcontroller incorporates an
80C51 with double the program and data memory, a
slave interface which allows it to be connected di­rectly to the host system bus as a peripheral, a FIFO
buffer module, a two channel DMA processor, and a
fifth I/O port (Figure 3). The UPI-452 retains all of
the 80C51 architecture, and is fully compatible with
the MCS-51 instruction set.

The Special Function Register (SFR) interface con­cept introduced in the MCS-51 family of microcon­trollers has been expanded in the UPI-452. To the
20 Special Function Registers of the MCS-51, the
UPI-452 adds 34 more. These additional Special
Function Registers, like those of the MCS-51, pro­vide access to the UPI-452 functional elements in­cluding the FIFO, DMA and added interrupt capabili­ties. Several of the 80C51 core Special Function
Registers have also been expanded to support add­ed features of the UPI-452.

This data sheet describes the unique features of the
UPI-452. Refer to the 80C51 data sheet for a de-

scription of the UPI-452’s core CPU functional
blocks including;

Ð Timers/Counters

Ð I/O Ports

Ð Interrupt timing and control (other than FIFO and

DMA interrupts)

Ð Serial Channel

Ð Local Expansion Bus

Ð Program/Data Memory structure

Ð Power-Saving Modes of Operation

Ð CHMOS Features

Ð Instruction Set

Figure 3 contains a conceptual block diagram of the
UPI-452. Figure 4 provides a functional block dia­gram.

FIFO Buffer Interface

A unique feature of the UPI-452 is the incorporation
of a 128 byte FIFO array at the host-slave interface.
The FIFO allows asynchronous bi-directional trans­fers between the host CPU and the internal CPU.

231428– 7

Figure 3. UPI-452 Conceptual Block Diagram

10

UPI-452

231428– 8

Figure 4. UPI-452 Functional Block Diagram

The division of the 128 bytes between Input and
Output channels is user programmable allowing
maximum flexibility. If the entire 128 byte FIFO is
allocated to the Input channel, a high performance
Host can transfer up to 128 bytes at one time, then
dedicate its resources to other functions while the
internal CPU processes the data in the FIFO. Vari­ous handshake signals allow the external Host to
operate independently and without frequent monitor­ing of the UPI-452 internal CPU. The FIFO Buffer
insures that the slave processor receives data in the
same order that it was sent by the host without the
need to keep track of addresses. Three slave bus
interface handshake methods are supported by the
UPI-452: DMA, Interrupt and Polled.

The FIFO is nine bits wide. The ninth bit acts as a
command/data flag. Commands written to the FIFO
by either the host or internal CPU are called Data
Stream Commands or DSCs. DSCs are written to
the input FIFO by the Host via a unique external
address. DSCs are written to the output FIFO by the
internal CPU via the COMMAND OUT Special Func­tion Register (SFR). When encountered by the host
or internal CPU a Data Stream Command can be
used as an address vector to user defined service
routines. DSCs provide synchronization of data and
commands between the Host and internal CPU.

FIFO PROGRAMMABLE FEATURES

Size of Input/Output Channels

The 128 bytes of FIFO space can be allocated be­tween the Input and Output channels via the Chan-

nel Boundary Pointer (CBP) SFR. This register con­tains the number of address locations assigned to
the Input channel. The remaining address locations
are automatically assigned to the Output FIFO. The
CBP SFR can only be programmed by the internal
CPU during FIFO DMA Freeze Mode (See FIFO-Ex­ternal Host Interface FIFO DMA Freeze Mode de­scription). The CBP is initialized to 40H (64 bytes)
upon reset.

The number in the Channel Boundary Pointer SFR is
actually the first address location of the Output
FIFO. Writing to the CBP SFR reassigns the Input
and Output FIFO address space. Whenever the CBP
is written, the Input FIFO pointers are reset to zero
and the Output FIFO pointers are set to the value in
the CBP SFR.

All of the FIFO space may be assigned to one chan­nel. In such a situation the other channel’s data path
consists of a single SFR (FIFO IN/COMMAND IN or
FIFO OUT/COMMAND OUT SFR) location.

CBP Input FIFO Output FIFO

Register Size Size

0 1 128
1 1 128
2 2 126
3 3 125
4 4 124

## #

7B 123 5
7C 124 4
7D 125 3
7E 128 1
7F 128 1

11

UPI-452

FIFO Read/Write Pointers

These normally operate in auto-increment (and auto­rollover) mode, but can be reassigned by the internal
CPU during FIFO DMA Freeze Mode (See FIFO-Ex­ternal Host Interface FIFO DMA Freeze Mode de­scription).

Threshold Register

The Input FIFO Threshold SFR contains the number
of empty bytes that must be available in the Input
FIFO to generate a Host interrupt. The Output FIFO
Threshold SFR contains the number of bytes, data
and/or DSC(s), that must be in the FIFO before an
interrupt is generated. The Threshold feature pre­vents the Host from being interrupted each time the
FIFO needs to load or unload one byte of data. The
thresholds, therefore, allow the FIFO’s operation to
be adjusted to the speed of the Host, optimizing the
overall interface performance.

NOTE:

DSC’s should be allowed to be written into the out­put FIFO by the UPI-452 code only when the serv­ice request is law. The service request can be mon­itored by b7 of OTHR. This guideline will elimate
the possibility of a DSC being written to the output
FIFO with the intention of setting the service re­quest while having the number of bytes in the out­put FIFO below the threshold. This condition can
occur if the FIFO contains at least two bytes, the
service request is being asserted, and the host
reads from the output FIFO until one byte remains.

Immediate Commands

The UPI-452 provides, in addition to data and DSCs,
a third direct means of communication between the
external Host and internal CPU called Immediate
Commands. As the name implies, an Immediate
Command is available to the receiving CPU immedi­ately, via an interrupt, without being entered into the
FIFO as are Data Stream Commands. Like Data
Stream Commands, Immediate Commands are writ­ten either via a unique external address by the host
CPU, or via dedicated SFR by the internal CPU.

The DSC and/or Immediate Command interface
may be defined as either Interrupt or Polled under
user program control via the Interrupt Enable (IE),
Slave Control Register (SLCON), and Interrupt En­able Priority (IEP) Special Function Registers, for the
internal CPU and via the Host Control SFR for the
external Host CPU.

DMA

The UPI-452 contains a two channel internal DMA
controller which allows transfer of data between any
of the three writeable memory spaces: Internal Data
Memory, External Load Expansion Bus Data Memo­ry and the Special Function Register array. The Spe­cial Function Register array appears as a set of
unique dedicated memory addresses which may be
used as either the source or destination address of a
DMA transfer. Each DMA channel is independently
programmable via dedicated Special Function Reg­isters for mode, source and destination addresses,
and byte count to be transferred. Each DMA channel
has four programmable modes:

Ð Alternate Cycle Mode

Ð Burst Mode

Ð FIFO or Serial Channel Demand Mode

Ð External Demand Mode

A complete description of each mode and DMA op­eration may be found in the section titled ‘‘General
Purpose DMA Channels’’.

FIFO/SLAVE INTERFACE
FUNCTIONAL DESCRIPTION

Overview

The FIFO is a 128 Byte RAM array with recirculating
pointers to manage the read and write accesses.
The FIFO consists of an Input and an Output chan­nel. Access cycles to the FIFO by the internal CPU
and external Host are interleaved and appear to be
occurring concurrently to both the internal CPU and
external Host. Interleaving access cycles ensures
efficient use of this shared resource. The internal
CPU accesses the FIFO in the same way it would
access any of the Special Function Registers e.g.,
direct and register indirect addressing as well as ar­ithmetric and logical instructions.

12

UPI-452

Input FIFO Channel

The Input FIFO Channel provides for data transfer from the external Host to the internal CPU (Figure 5). The
registers associated with the Input Channel during normal operation are listed in Table 1*.

Table 1. Input FIFO Channel Registers*

Register Name Description

1) Input Buffer Latch Host CPU Write only

2) FIFO IN SFR Internal CPU Read only

3) COMMAND IN SFR Internal CPU Read only

4) Input FIFO Read Pointer SFR Internal CPU Read only

5) Input FIFO Write Pointer SFR Internal CPU Read only

6) Input FIFO Threshold SFR Internal CPU Read only

*See ‘‘FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE’’ section for FIFO DMA Freeze Mode SFR characteristics description.

231428– 9

Figure 5. Input FIFO Channel Functional Block Diagram

13

UPI-452

The host CPU writes data and Data Stream Com­mands into the Input Buffer Latch on the rising edge
of the external WR signal. External addressing de­termines whether the byte is a data byte or Data
Stream Command and the FIFO logic sets the ninth
bit of the FIFO accordingly as the byte is moved
from the Input Buffer Latch into the FIFO. A ‘‘1’’ in
the ninth bit indicates that the incoming byte is a
Data Stream Command. The internal CPU reads
data bytes via the FIFO IN SFR, and Data Stream
Commands via the COMMAND IN SFR.

A Data Stream Command will generate an interrupt
to the internal CPU prior to being read and after
completion of the previous operation. The DSC can
then be read via the COMMAND IN SFR. Data can
only be read via the FIFO IN SFR and Data Stream
Commands via the COMMAND IN SFR. Attempting
to read Data Stream Commands as data by address­ing the FIFO IN SFR will result in ‘‘0FFH’’ being
read, and the Input FIFO Read Pointer will remain
intact. (This prevents accidental misreading of Data
Stream Commands.) Attempting to read data as
Data Stream Commands will have the same conse­quence.

The Input FIFO Channel addressing is controlled by
the Input FIFO Read and Write Pointer SFRs. These
SFRs are read only registers during normal opera­tion. However, during FIFO DMA Freeze Mode (See
FIFO-External Host Interface FIFO DMA Freeze
Mode description), the internal CPU has write ac­cess to them. Any write to these registers in normal
mode will have no effect. The Input Write Pointer
SFR contains the address location to which data/
commands are written from the Input Buffer Latch.
The write pointer is automatically incremented after
each write and is reset to zero if equal to the CBP,
as the Input FIFO operates as a circular buffer.

If a write is performed on an empty FIFO, the first
byte is also written into the FIFO IN or COMMAND
IN SFR. If the Host continues writing while the Input

FIFO is full, an external interrupt, if enabled, is sent
to the host to signal the overrun condition. The
writes are ignored by the FIFO control logic. Similar­ly, an internal CPU read of an empty FIFO will cause
an underrun error interrupt to be generated to the
internal CPU and a value of ‘‘0FFH’’ will be read by
the internal CPU.

The Read Pointer SFR holds the address of the next
byte to be read from the Input FIFO. An Input FIFO
read operation post-increments the Input Read
Pointer SFR and loads a new data byte into the
FIFO IN SFR or a Data Stream Command into the
COMMAND IN SFR at the end of the read cycle.

An Input FIFO Request for Service (via DMA, Inter­rupt or a flag) is generated to the Host whenever
more data can be written into the Input FIFO. For
efficient utilization of the Host, a ‘‘threshold’’ value
can be programmed into the Input FIFO Threshold
SFR. The range of values of the Input FIFO Thresh­old SFR can be from 0 to (CBP-3). The Request for
Service Interrupt is generated only after the Input
FIFO has room to accommodate a threshold number
of bytes or more. The threshold is equal to the total
number of bytes assigned to the Input FIFO (CBP)
minus the number of bytes programmed in the Input
FIFO Threshold SFR. With this feature the Host is
assured that it can write at least a threshold number
of bytes to the Input FIFO channel without worrying
about an overrun condition. Once the Request for
Service is generated it remains active until the Input
FIFO becomes full.

Output FIFO Channel

The Output FIFO Channel provides data transfer
from the UPI-452 internal CPU to the external Host
(Figure 6).

The registers associated with the Output Channel
during normal operation are listed in Table 2*.

14

UPI-452

231428– 10

Figure 6. Output FIFO Channel Functional Block Diagram

Table 2. Output FIFO Channel Registers

Register Name Description

1) Output Buffer Latch Host CPU Read only

2) FIFO OUT SFR Internal CPU Read and Write

3) COMMAND OUT SFR Internal CPU Read and Write

4) Output FIFO Read Pointer SFR Internal CPU Read only

5) Output FIFO Write Pointer SFR Internal CPU Read only

6) Output FIFO Threshold SFR Internal CPU Read only

*See ‘‘FIFO-EXTERNAL HOST INTERFACE FIFO DMA FREEZE MODE’’ section for FIFO DMA Freeze Mode register characteristics description.

15

UPI-452

The UPI-452 internal CPU transfers data to the Out­put FIFO via the FIFO OUT SFR and commands via
the COMMAND OUT SFR. If the byte is written to
the COMMAND OUT SFR, the ninth bit is automati­cally set (

e

1) to indicate a Data Stream Command.
If the byte is written to the FIFO OUT SFR the ninth
bit is cleared (

e

0). Thus the FIFO OUT and COM­MAND OUT SFRs are the same but the address de­termines whether the byte entered in the FIFO is a
DSC or data byte.

The Output FIFO preloads a byte into the Output
Buffer Latch. When the Host issues a RD/ signal,
the data is immediately read from the Output Buffer
Latch. The next data byte is then loaded into the
Output Buffer Latch, a flag is set and an interrupt, if
enabled, is generated if the byte is a DSC (ninth bit
is set). The operation is carefully timed such that an
interrupt can be generated in time for it to be recog­nized by the Host before its next read instruction.
Internal CPU write and external Host read opera­tions are interleaved at the FIFO so that they appear
to be occurring concurrently.

The Output FIFO read and write pointer operation is
the same as for the Input Channel. Writing to the
FIFO OUT or COMMAND OUT SFRs will increment
the Output Write Pointer SFR but reading from it will
leave the write pointer unchanged. A rollover of the
Output FIFO Write Pointer causes the pointer to be
reset to the value in the Channel Boundary Pointer
(CBP) SFR.

If the external host attempts to read a Data Stream
Command as a data byte it will result in invalid data
(0FFH) being read. The DSC is not lost because the
invalid read does not increment the pointer. Similarly
attempting to read a data byte as a Data Stream
Command has the same result.

A Request for Service is generated to the external
Host under the following two conditions:

1.) Whenever the internal CPU has written a thresh-

old number of bytes or more into the Output FIFO
(threshold

e

(OTHR)a1). The threshold num­ber should be chosen such that the bus latency
time for the external Host does not result in a
FIFO overrun error condition on the internal CPU
side. The threshold limit should be large enough
to make a bus request by the UPI-452 to the ex­ternal host CPU worthwhile. Once a request for
service is generated, the request remains active
until the Output FIFO becomes empty. The range
of values of the FIFO Output Threshold (OTHR)
SFR is from 2 to

À

(80H-CBP)-1Ó. The threshold

number can be programmed via the OTHR SFR.

2.) The second type of Request for Service is called
‘‘Flush Mode’’ and occurs when the internal CPU
writes a Data Stream Command into the Output
FIFO. Its purpose is to ensure that a data block
entered into the Output FIFO, which is less than
the programmed threshold, will generate a Re­quest for Service interrupt, if enabled, and be
read, or ‘‘Flushed’’ from the Output FIFO, by the
external host CPU regardless of the status of the
OTHR SFR.

NOTE:

The host port read or write strobe (TPW) should be
limited to a maximum of 4 TCLCL. This guideline
will eliminate a potential output FIFO Request lock­up from occurring if the host reads the last byte
from the output FIFO while the UPI-452 is begin­ning to write another byte to the output FIFO.

Immediate Commands

Immediate Commands provide direct communica­tion between the external Host and UPI-452. Unlike
Data Stream Commands which are entered into the
FIFO, the Immediate Command is available to the
receiving CPU directly, bypassing the FIFO. The Im­mediate Command can serve as a program vector
pointing into a jump table in the recipients software.
Immediate Command Interrupts are generated, if en­abled, and a bit in the appropriate Status Register is
set when an Immediate Command is input or output.
A similar bit is provided to acknowledge when an
Immediate Command has been read and whether
the register is available to receive another com­mand. The bits are reset when the Immediate Com­mands are read. Two Special Function Registers are
dedicated to the Immediate Command interface. Ex­ternal addressing determines whether the Host is
accessing the Input FIFO or the Immediate Com­mand IN (IMIN) SFR. The internal CPU writes Imme­diate Commands to the Immediate Command OUT
(IMOUT) SFR.

Both processors have the ability to enable or disable
Immediate Command Interrupts. By disabling the in­terrupt, the recipient of the Immediate Command
can poll the status SFR and read the Immediate
Command at its convenience. Immediate Com­mands should only be written when the appropriate
Immediate Command SFR is empty (as indicated in
the appropriate status SFR:HSTAT/SSTAT). Simi­larly, the Immediate Command SFR should only be
read when there is data in the Register.

The flowcharts in Figure 7a and 7b illustrate the
proper handshake mechanisms between the exter­nal Host and internal CPU when handling Immediate
Commands.

16