Intel Corporation N80960SA-10, N80960SA-20, N80960SA-16, S80960SA-10, S80960SA-16 Datasheet
...
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1993 November 1993 Order Number: 272206-002
80960SA
EMBEDDED 32-BIT MICROPROCESSOR
WITH 16-BIT BURST DATA BUS
The 80960SA is a member of Intel’s i960® 32-bit processor family, which is designed especially for low cost
embedded applications. It includes a 512-byte instruction cache and a built-in interrupt controller. The 80960SA
has a large register set, multiple parallel execution units and a 16-bit burst bus. Using advanced RISC
technology, this high performance processor is capable of execution rates in excess of 7.5 million instructions
per second
*
. The 80960SA is well-suited for a wide range of cost sensitive embedded applications including
non-impact printers, network adapters and I/O controllers.
Figure 1. The 80960SA Processor’s Highly Parallel Architecture
* Relative to Digital Equipment Corporation’s VAX-11/780 at 1 MIPS (VAX-11™ is a trademark of Digital Equipment
Corporation)
■ High-Performance Embedded
Architecture
— 20 MIPS* Burst Execution at 20 MHz
— 7.5 MIPS Sustained Execution
at 20 MHz
■ 512-Byte On-Chip Instruction Cache
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
■ Multiple Register Sets
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip
— Register Scoreboarding
■ Pin Compatible with 80960SB
■ Built-in Interrupt Controller
— 4 Direct Interrupt Pins
— 31 Priority Levels, 256 Vectors
■ Easy to Use, High Bandwidth 16-Bit Bus
— 32 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
■ 32-Bit Address Space, 4 Gigabytes
■ 80-Lead Quad Flat Pack (EIAJ QFP)
— 84-Lead Plastic Leaded Chip Carrier
(PLCC)
■ Software Compatible with
80960KA/KB/CA/CF Processors
INSTRUCTION
FETCH UNIT
512-BYTE
INSTRUCTION
CACHE
INSTRUCTION
DECODER
MICRO-
INSTRUCTION
SEQUENCER
MICRO-
INSTRUCTION
ROM
32-BIT
BUS
CONTROL
LOGIC
32-BIT
INSTRUCTION
EXECUTION
UNIT
64- BY 32-BIT
LOCAL
REGISTER
CACHE
SIXTEEN
32-BIT GLOBAL
REGISTERS
32-BIT
ADDRESS
16-BIT
BURST
BUS
ii
CONTENTS PAGE
1.0 THE i960® PROCESSOR ........................................................................................................................... 1
1.1 Key Performance Features ................................................................................................................. 2
1.1.1 Memory Space And Addressing Modes ...................................................................................4
1.1.2 Data Types ...............................................................................................................................4
1.1.3 Large Register Set ...................................................................................................................4
1.1.4 Multiple Register Sets ..............................................................................................................5
1.1.5 Instruction Cache .....................................................................................................................6
1.1.6 Register Scoreboarding ...........................................................................................................6
1.1.7 High Bandwidth Bus ................................................................................................................6
1.1.8 Interrupt Handling ....................................................................................................................6
1.1.9 Debug Features .......................................................................................................................6
1.1.10 Fault Detection .......................................................................................................................7
1.1.11 Built-in Testability .................................................................................................................... 7
1.1.12 CHMOS .................................................................................................................................. 7
2.0 ELECTRICAL SPECIFICATIONS............................................................................................................. 11
2.1 Power and Grounding .......................................................................................................................11
2.2 Power Decoupling Recommendations .............................................................................................. 11
2.3 Connection Recommendations ......................................................................................................... 11
2.4 Characteristic Curves ....................................................................................................................... 11
2.5 Test Load Circuit ...............................................................................................................................13
2.6 ABSOLUTE MAXIMUM RATINGS* ..................................................................................................14
2.7 DC Characteristics ............................................................................................................................14
2.8 AC Specifications ..............................................................................................................................15
3.0 MECHANICAL DATA................................................................................................................................21
3.1 Packaging .........................................................................................................................................21
3.2 Pin Assignment .................................................................................................................................21
3.3 Pinout ................................................................................................................................................23
3.4 Package Thermal Specifications ...................................................................................................... 27
3.5 Stepping Register Information ..........................................................................................................27
4.0 WAVEFORMS...........................................................................................................................................28
5.0 REVISION HISTORY ................................................................................................................................34
80960SA
EMBEDDED 32-BIT MICROPROCESSOR
WITH 16-BIT BURST DATA BUS
iii
LIST OF FIGURES PAGE
Figure 1 The 80960SA Processor’s Highly Parallel Architecture ................................................................0
Figure 2 80960SA Programming Environment ...........................................................................................1
Figure 3 Instruction Formats ......................................................................................................................4
Figure 4 Multiple Register Sets Are Stored On-Chip ..................................................................................5
Figure 5 Connection Recommendation for LOCK
....................................................................................11
Figure 6 Typical Supply Current vs. Case Temperature ...........................................................................12
Figure 7 Typical Current vs. Frequency (Room Temp) ............................................................................. 12
Figure 8 Typical Current vs. Frequency (Hot Temp) ................................................................................. 13
Figure 9 Capacitive Derating Curve ......................................................................................................... 13
Figure 10 Test Load Circuit for Three-State Output Pins ............................................................................ 13
Figure 11 Drive Levels and Timing Relationships for 80960SA Signals ..................................................... 15
Figure 12 Processor Clock Pulse (CLK2) ...................................................................................................19
Figure 13 RESET
Signal Timing .................................................................................................................19
Figure 14 HOLD Timing ..............................................................................................................................20
Figure 15 80-Lead EIAJ Quad Flat Pack (QFP) Package ..........................................................................21
Figure 16 84-Lead Plastic Leaded Chip Carrier (PLCC) Package .............................................................22
Figure 17 Non-Burst Read and Write Transactions Without Wait States ....................................................28
Figure 18 Quad Word Burst Read Transaction With 1, 0, 0, 0, 0, 0, 0, 0 Wait States ................................29
Figure 19 Burst Write Transaction With 2, 1, 1, 1 Wait States (6-8 Bytes Transferred) .............................. 30
Figure 20 Accesses Generated by Quad Word Read Bus Request,
Misaligned One Byte from Quad Word Boundary 1, 0, 0, 0, 0, 0, 0, 0 Wait States.....................31
Figure 21 Interrupt Acknowledge Cycle ......................................................................................................32
Figure 22 Cold Reset Waveform ................................................................................................................ 33
LIST OF TABLES
Table 1 80960SA Instruction Set ..............................................................................................................3
Table 2 Memory Addressing Modes .........................................................................................................4
Table 3 80960SA Pin Description: Bus Signals ........................................................................................8
Table 4 80960SA Pin Description: Support Signals ................................................................................10
Table 5 DC Characteristics .....................................................................................................................14
Table 6 80960SA AC Characteristics (10 MHz) ......................................................................................16
Table 7 80960SA AC Characteristics (16 MHz) ......................................................................................17
Table 8 80960SA AC Characteristics (20 MHz) ......................................................................................18
Table 9 80960SA QFP Pinout — In Pin Order ........................................................................................ 23
Table 10 80960SA QFP Pinout — In Signal Order ...................................................................................24
Table 11 80960SA PLCC Pinout — In Pin Order ......................................................................................25
Table 12 80960SA PLCC Pinout — In Signal Order ................................................................................. 26
Table 13 80960SA QFP Package Thermal Characteristics ......................................................................27
Table 14 80960SA PLCC Package Thermal Characteristics .................................................................... 27
Table 15 Die Stepping Cross Reference ...................................................................................................27
1
80960SA
1.0 THE i960® PROCESSOR
The 80960SA is a member of the 32-bit architecture
from Intel known as the i960 processor family. These
microprocessors were especially designed to serve
the needs of embedded applications. The embedded
market includes applications as diverse as industrial
automation, avionics, image processing, graphics
and networking. These types of applications require
high integration, low power consumption, quick
interrupt response times and high performance.
Since time to market is critical, embedded microprocessors need to be easy to use in both hardware and
software designs.
All members of the i960 processor family share a
common core architecture which utilizes RISC
technology so that, except for special functions, the
family members are object-code compatible. Each
new processor in the family adds its own special set
of functions to the core to satisfy the needs of a
specific application or range of applications in the
embedded market.
Figure 2. 80960SA Programming Environment
ARCHITECTURALLY
DEFINED
DATA STRUCTURES
FFFF FFFFH
INSTRUCTION
STREAM
INSTRUCTION
EXECUTION
PROCESSOR STATE
REGISTERS
INSTRUCTION
POINTER
ARITHMETIC
CONTROLS
PROCESS
CONTROLS
TRACE
CONTROLS
ADDRESS SPACE
SIXTEEN 32-BIT
GLOBAL REGISTERS
SIXTEEN 32-BIT
LOCAL REGISTERS
g0
g15
r0
r15
LOAD STORE
0000 0000H
INSTRUCTION
CACHE
FETCH
FOUR 80-BIT
CONTROL REGISTERS
FLOATING POINT REGISTERS
2
80960SA
1.1 Key Performance Features
The 80960SA architecture is based on the most
recent advances in microprocessor technology and
is grounded in Intel’s long experience in the design
and manufacture of embedded microprocessors.
Many features contribute to the 80960SA’s exceptional performance:
1. Large Register Set. Having a large number of
registers reduces the number of times that a
processor needs to access memory. Modern
compilers can take advantage of this feature to
optimize execution speed. For maximum flexibility, the 80960SA provides thirty-two 32-bit
registers. (See Figure 2.)
2. Fast Instruction Execution. Simple functions
make up the bulk of instructions in most
programs so that execution speed can be
improved by ensuring that these core instructions are executed as quickly as possible. The
most frequently executed instructions — such
as register-register moves, add/subtract,
logical operations and shifts — execute in one
to two cycles. (Table 1 contains a list of instructions.)
3. Load/Store Architecture. One way to improve
execution speed is to reduce the number of
times that the processor must access memory
to perform an operation. As with other
processors based on RISC technology, the
80960SA has a Load/Store architecture. As
such, only the LOAD and STORE instructions
reference memory; all other instructions
operate on registers. This type of architecture
simplifies instruction decoding and is used in
combination with other techniques to increase
parallelism.
4. Simple Instruction Formats. All instructions
in the 80960SA are 32 bits long and must be
aligned on word boundaries. This alignment
makes it possible to eliminate the instruction
alignment stage in the pipeline. To simplify the
instruction decoder, there are only five
instruction formats; each instruction uses only
one format. (See Figure 3.)
5. Overlapped Instruction Execution. Load
operations allow execution of subsequent
instructions to continue before the data has
been returned from memory, so that these
instructions can overlap the load. The
80960SA manages this process transparently
to software through the use of a register scoreboard. Conditional instructions also make use
of a scoreboard so that subsequent unrelated
instructions may be executed while the conditional instruction is pending.
6. Integer Execution Optimization. When the
result of an arithmetic execution is used as an
operand in a subsequent calculation, the value
is sent immediately to its destination register.
At the same time, the value is put on a bypass
path to the ALU, thereby saving the time that
otherwise would be required to retrieve the
value for the next operation.
7. Bandwidth Optimizations. The 80960SA gets
optimal use of its memory bus bandwidth
because the bus is tuned for use with the onchip instruction cache: instruction cache line
size matches the maximum burst size for
instruction fetches. The 80960SA automatically
fetches four words in a burst and stores them
directly in the cache. Due to the size of the
cache and the fact that it is continually filled in
anticipation of needed instructions in the
program flow, the 80960SA is relatively insensitive to memory wait states. The benefit is that
the 80960SA delivers outstanding performance
even with a low cost memory system.
8. Cache Bypass. If a cache miss occurs, the
processor fetches the needed instruction then
sends it on to the instruction decoder at the
same time it updates the cache. Thus, no extra
time is spent to load and read the cache.
3
80960SA
Table 1. 80960SA Instruction Set
Data Movement Arithmetic Logical Bit and Bit Field
Load
Store
Move
Load Address
Add
Subtract
Multiply
Divide
Remainder
Modulo
Shift
Extended Multiply
Extended Divide
And
Not And
And Not
Or
Exclusive Or
Not Or
Or Not
Nor
Exclusive Nor
Not
Nand
Rotate
Set Bit
Clear Bit
Not Bit
Check Bit
Alter Bit
Scan For Bit
Scan Over Bit
Extract
Modify
Comparison Branch Call/Return Fault
Compare
Conditional Compare
Compare and Increment
Compare and Decrement
Unconditional Branch
Conditional Branch
Compare and Branch
Call
Call Extended
Call System
Return
Branch and Link
Conditional Fault
Synchronize Faults
Debug Miscellaneous Decimal
Modify Trace Controls
Mark
Force Mark
Atomic Add
Atomic Modify
Flush Local Registers
Modify Arithmetic
Controls
Scan Byte for Equal
Test Condition Code
Move
Add with Carry
Subtract with Carry
Synchronous
Synchronous Load
Synchronous Move
4
80960SA
Figure 3. Instruction Formats
Control
Compare and
Branch
Register to
Register
Memory Access--Short
Memory Access--Long
Opcode Displacement
Opcode DisplacementReg/Lit Reg M
Displacement
Opcode
Opcode
Opcode Reg
Reg
Reg Reg/Lit
Base
Base
M
Modes
Mode
Ext’d Op Reg/Lit
X Offset
Scale xx Offset
1.1.1 Memory Space And Addressing Modes
The 80960SA offers a linear programming
environment so that all programs running on the
processor are contained in a single address space.
Maximum address space size is 4 Gigabytes (2
32
bytes).
For ease of use the 80960SA has a small number of
addressing modes, but includes all those necessary
to ensure efficient execution of high-level languages
such as C. Table 2 lists the memory addressing
modes.
Table 2. Memory Addressing Modes
• 12-Bit Offset
• 32-Bit Offset
• Register-Indirect
• Register + 12-Bit Offset
• Register + 32-Bit Offset
• Register + (Index-Register x Scale-Factor)
• Register x Scale Factor + 32-Bit Displacement
• Register + (Index-Register x Scale-Factor) + 32Bit Displacement
Scale-Factor is 1, 2, 4, 8 or 16
1.1.2 Data Types
The 80960SA recognizes the following data types:
Numeric:
• 8-, 16-, 32- and 64-bit ordinals
• 8-, 16-, 32- and 64-bit integers
Non-Numeric:
• Bit
• Bit Field
• Triple Word (96 bits)
• Quad-Word (128 bits)
1.1.3 Large Register Set
The 80960SA programming environment includes a
large number of registers. In fact, 32 registers are
available at any time. The availability of this many
registers greatly reduces the number of memory
accesses required to perform algorithms, which
leads to greater instruction processing speed.
There are two types of general-purpose register:
local and global. The global registers consist of
sixteen 32-bit registers (g0 though g15). These
registers perform the same function as the general-
5
80960SA
purpose registers provided in other popular microprocessors. The term global refers to the fact that
these registers retain their contents across
procedure calls.
The local registers, on the other hand, are procedure
specific. For each procedure call, the 80960SA
allocates 16 local registers (r0 through r15). Each
local register is 32 bits wide.
1.1.4 Multiple Register Sets
To further increase the efficiency of the register set,
multiple sets of local registers are stored on-chip
(See Figure 4). This cache holds up to four local
register frames, which means that up to three
procedure calls can be made without having to
access the procedure stack resident in memory.
Although programs may have procedure calls nested
many calls deep, a program typically oscillates back
and forth between only two to three levels. As a
result, with four stack frames in the cache, the probability of having a free frame available on the cache
when a call is made is very high. In fact, runs of
representative C-language programs show that 80%
of the calls are handled without needing to access
memory.
If four or more procedures are active and a new
procedure is called, the 80960SA moves the oldest
local register set in the stack-frame cache to a
procedure stack in memory to make room for a new
set of registers. Global register g15 is the frame
pointer (FP) to the procedure stack.
Global registers are not exchanged on a procedure
call, but retain their contents, making them available
to all procedures for fast parameter passing.
Figure 4. Multiple Register Sets Are Stored On-Chip
r
15
r
0
31
0
ONE OF FOUR
LOCAL
REGISTER SETS
REGISTER
CACHE
LOCAL REGISTER SET
6
80960SA
1.1.5 Instruction Cache
To further reduce memory accesses, the 80960SA
includes a 512-byte on-chip instruction cache. The
instruction cache is based on the concept of locality
of reference; most programs are not usually
executed in a steady stream but consist of many
branches, loops and procedure calls that lead to
jumping back and forth in the same small section of
code. Thus, by maintaining a block of instructions in
cache, the number of memory references required to
read instructions into the processor is greatly
reduced.
To load the instruction cache, instructions are
fetched in 16-byte blocks; up to four instructions can
be fetched at one time. An efficient prefetch
algorithm increases the probability that an instruction
will already be in the cache when it is needed.
Code for small loops often fits entirely within the
cache, leading to a great increase in processing
speed since further memory references might not be
necessary until the program exits the loop. Similarly,
when calling short procedures, the code for the
calling procedure is likely to remain in the cache so it
will be there on the procedure’s return.
1.1.6 Register Scoreboarding
The instruction decoder is optimized in several ways.
One optimization method is the ability to overlap
instructions by using register scoreboarding.
Register scoreboarding occurs when a LOAD moves
a variable from memory into a register. When the
instruction initiates, a scoreboard bit on the target
register is set. Once the register is loaded, the bit is
reset. In between, any reference to the register
contents is accompanied by a test of the scoreboard
bit to ensure that the load has completed before
processing continues. Since the processor does not
need to wait for the LOAD to complete, it can execute
additional instructions placed between the LOAD
and the instruction that uses the register contents, as
shown in the following example:
ld data_2, r4
ld data_2, r5
Unrelated instruction
Unrelated instruction
add r4, r5, r6
In essence, the two unrelated instructions between
LOAD and ADD are executed “for free” (i.e., take no
apparent time to execute) because they are
executed while the register is being loaded. Up to
three load instructions can be pending at one time
with three corresponding scoreboard bits set. By
exploiting this feature, system programmers and
compiler writers have a useful tool for optimizing
execution speed.
1.1.7 High Bandwidth Bus
The 80960SA CPU resides on a high-bandwidth
address/data bus. The bus provides a direct communication path between the processor and the
memory and I/O subsystem interfaces. The
processor uses the bus to fetch instructions,
manipulate memory and respond to interrupts. Bus
features include:
• 16-bit data path multiplexed onto the lower bits of
the 32-bit address path
• Eight 16-bit half-word burst capability which
allows transfers from 1 to 16 bytes at a time
• High bandwidth reads and writes with 32
Mbytes/s burst (at 20 MHz)
Table 3 defines bus signal names and functions;
Table 4 defines other component-support signals
such as interrupt lines.
1.1.8 Interrupt Handling
The 80960SA can be interrupted in one of two ways:
by the activation of one of four interrupt pins or by
sending a message on the processor’s data bus.
The 80960SA is unusual in that it automatically
handles interrupts on a priority basis and can keep
track of pending interrupts through its on-chip
interrupt controller. Two of the interrupt pins can be
configured to provide 8259A-style handshaking for
expansion beyond four interrupt lines.
1.1.9 Debug Features
The 80960SA has built-in debug capabilities. There
are two types of breakpoints and six trace modes.
Debug features are controlled by two internal 32-bit
registers, the Process-Controls Word and the TraceControls Word. By setting bits in these control words,
a software debug monitor can closely control how
the processor responds during program execution.
7
80960SA
The 80960SA provides two hardware breakpoint
registers on-chip which, by using a special
command, can be set to any value. When the
instruction pointer matches either breakpoint register
value, the breakpoint handling routine is automatically called.
The 80960SA also provides software breakpoints
through the use of two instructions: MARK and
FMARK. These can be placed at any point in a
program and cause the processor to halt execution
at that point and call the breakpoint handling routine.
The breakpoint mechanism is easy to use and
provides a powerful debugging tool.
Tracing is available for instructions (single step
execution), calls and returns and branching. Each
trace type may be enabled separately by a special
debug instruction. In each case, the 80960SA
executes the instruction first and then calls a trace
handling routine (usually part of a software debug
monitor). Further program execution is halted until
the routine completes, at which time execution
resumes at the next instruction. The 80960SA’s
tracing mechanisms, implemented completely in
hardware, greatly simplify the task of software test
and debug.
1.1.10 Fault Detection
The 80960SA has an automatic mechanism to
handle faults. Fault types include trace and
arithmetic faults. When the processor detects a fault,
it automatically calls the appropriate fault handling
routine and saves the current instruction pointer and
necessary state information to make efficient
recovery possible. Like interrupt handling routines,
fault handling routines are usually written to meet the
needs of specific applications and are often included
as part of the operating system or kernel.
For each of the fault types, there are numerous
subtypes that provide specific information about a
fault. The fault handler can use this specific information to respond correctly to the fault.
1.1.11 Built-in Testability
Upon reset, the 80960SA automatically conducts an
exhaustive internal test of its major blocks of logic.
Then, before executing its first instruction, it does a
zero check sum on the first eight words in memory to
ensure that the memory image was programmed
correctly. If a problem is discovered at any point
during the self-test, the 80960SA asserts its FAIL
pin
and will not begin program execution. Self test takes
approximately 24,000 cycles to complete.
System manufacturers can use the 80960SA’s selftest feature during incoming parts inspection. No
special diagnostic programs need to be written. The
test is both thorough and fast. The self-test capability
helps ensure that defective parts are discovered
before systems are shipped and, once in the field,
the self-test makes it easier to distinguish between
problems caused by processor failure and problems
resulting from other causes.
1.1.12 CHMOS
The 80960SA is fabricated using Intel’s CHMOS IV
(Complementary High Speed Metal Oxide Semiconductor) process. The 80960SA is available at 10 and
16 MHz in the QFP package and at 10, 16 and 20
MHz in the PLCC package.
8
80960SA
Table 3. 80960SA Pin Description: Bus Signals (Sheet 1 of 2)
NAME TYPE DESCRIPTION
CLK2 I SYSTEM CLOCK provides the fundamental timing for 80960SA systems. It is
divided by two inside the 80960SA to generate the internal processor clock.
A31:16 O
T.S.
ADDRESS BUS carries the upper 16 bits of the 32-bit physical address to memory.
It is valid throughout the burst cycle; no latch is required.
AD15:1, D0 I/O
T.S.
ADDRESS/DATA BUS carries the low order 32-bit addresses and 16-bit data to
and from memory. AD15:4 must be latched since the cycle following the address
cycle carries data on the bus.
A3:1 O
T.S.
ADDRESS BUS carries the word addresses of the 32-bit address to memory.
These three bits are incremented during a burst access indicating the next word
address of the burst access. Note that A3:1 are duplicated with AD3:1 during the
address cycle.
ALE O
T.S.
ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is
asserted during a T
a
cycle and deasserted before the beginning of the Td state. It is
active HIGH and floats to a high impedance state during a hold cycle (T
h
).
AS
O
T.S.
ADDRESS STATUS indicates an address state. AS is asserted every Ta state and
deasserted during the following T
d
state. AS is driven HIGH during reset.
W/R
O
T.S.
WRITE/READ specifies, during a Ta cycle, whether the operation is a write or read.
It is latched on-chip and remains valid during T
d
cycles.
DEN
O
T.S.
DATA ENABLE is asserted during Td cycles and indicates transfer of data on the
AD lines. The AD lines should not be driven by an external source unless DEN
is
asserted. When DEN
is asserted, outputs from the previous cycle are guaranteed
to be three-stated. In addition, DEN
deasserted indicates inputs have been
captured; therefore input hold times can be disregarded. DEN
is driven HIGH
during reset.
DT/R
O
T.S.
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from
the bus. It is low during T
a
and Td cycles for a read or interrupt acknowledgment; it
is high during T
a
and Td cycles for a write. DT/R never changes state when DEN is
asserted. DT/R
is driven HIGH during reset.
READY
I READY indicates that data on AD lines can be sampled or removed. If READY is
not asserted during a T
d
cycle, the Td cycle is extended to the next cycle by
inserting a wait state (T
w
).
I/O = Input/Output, O = Output, I = Input, O.D. = Open Drain, T.S. = Three-state
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