Intel Corporation MR87C51FC-1, MR87C51FC, MD87C51FC-1, MD87C51FC Datasheet
January 1994 Order Number: 271114-004
M87C51FC
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER
WITH 32 KBYTES USER PROGRAMMABLE EPROM
Military
M87C51FCÐ3.5 MHz to 12 MHz, V
CC
e
5Vg20%
M87C51FC-1Ð3.5 MHz to 16 MHz, V
CC
e
5Vg20%
Y
High Performance CHMOS EPROM
Y
Three 16-Bit Timer/Counters
Y
Programmable Clock Out
Y
Programmable Counter Array with:
Ð High Speed Output,
Ð Compare/Capture,
Ð Pulse Width Modulator,
Ð Watchdog Timer Capabilities
Y
Up/Down Timer/Counter
Y
Three Level Program Lock System
Y
32K On-Chip EPROM
Y
256 Bytes of On-Chip Data RAM
Y
Improved Quick Pulse Programming
Algorithm
Y
Boolean Processor
Y
Available in 40-pin Cerdip and 44-pin
LCC Packages
Y
32 Programmable I/O Lines
Y
7 Interrupt Sources
Y
Programmable Serial Channel with:
Ð Framing Error Detection
Ð Automatic Address Recognition
Y
TTL and CMOS Compatible Logic
Levels
Y
64K External Program Memory Space
Y
64K External Data Memory Space
Y
MCSÉ-51 Fully Compatible Instruction
Set
Y
Power Saving Idle and Power Down
Modes
Y
ONCE (On-Circuit Emulation) Mode
Y
Available in Two Product Grades:
Ð MIL-STD-883,
b
55§Ctoa125§C(TC)
Ð Military Temperature Only (MTO)
b
55§Ctoa125§C(TC)
MEMORY ORGANIZATION
PROGRAM MEMORY: Up to 32 Kbytes of the program memory can reside in the on-chip EPROM. In addition
the device can address up to 64K of program memory external to the chip.
DATA MEMORY: This microcontroller has a 256 x 8 on-chip RAM. In addition it can address up to 64 Kbytes of
external data memory.
The Intel M87C51FC is a single-chip control-oriented microcontroller which is fabricated on Intel’s reliable
CHMOS III-E technology. Being a member of the MCS-51 family, the M87C51FC uses the same powerful
instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS-51 family of
products. The M87C51FC is an enhanced version of the 87C51. Its added features make it an even more
powerful microcontroller for applications that require Pulse Width Modulation, High Speed I/O, and up/down
counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications.
M87C51FC
271114–1
Figure 1. M87C51FC Block Diagram
2
M87C51FC
PACKAGES
Part Prefix Package Type
87C51FC D 40-Pin CERDIP
R 44-Pin LCC
271114–2
DIP
271114–3
LCC
Figure 2. Pin Connections
PIN DESCRIPTIONS
VCC: Supply voltage.
VSS: Circuit ground.
Port 0: Port 0 is an 8-bit, open drain, bidirectional I/O
port. As an output port each pin can sink several LS
TTL inputs. Port 0 pins that have 1’s written to them
float, and in that state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting1’s, and can source and
sink several LS TTL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
current (I
IL
, on the data sheet) because of the inter-
nal pullups.
In addition, Port 1 serves the functions of the following special features of the M87C51FC:
Port Pin Alternate Function
P1.0 T2 (External Count Input to Timer/
Counter 2), Clock-Out
P1.1 T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
P1.2 ECI (External Count Input to the PCA)
P1.3 CEX0 (External I/O for Compare/
Capture Module 0)
P1.4 CEX1 (External I/O for Compare/
Capture Module 1)
P1.5 CEX2 (External I/O for Compare/
Capture Module 2)
P1.6 CEX3 (External I/O for Compare/
Capture Module 3)
P1.7 CEX4 (External I/O for Compare/
Capture Module 4)
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (I
IL
, on the data sheet) because of the inter-
nal pullups.
3
M87C51FC
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX
@
DPTR). In this application it
uses strong internal pullups when emitting 1’s. During accesses to external Data Memory that use 8-bit
addresses (MOVX
@
Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
current (I
IL
, on the data sheet) because of the pull-
ups.
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Port Pin Alternate Function
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0
(external interrupt 0)
P3.3 INT1
(external interrupt 1)
P3.4 T0 (Timer 0 external input)
P3.5 T1 (Timer 1 external input)
P3.6 WR (external data memory write strobe)
P3.7 RD
(external data memory read strobe)
Some Port 3 pins receive the high-order address bits
during EPROM programming and program verification.
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. An internal pulldown resistor permits a poweron reset with only a capacitor connected to V
CC
.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG
) is also the
program pulse input during EPROM programming for
the M87C51FC.
In normal operation ALE is emitted at a constant
rate of (/6 the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
PSEN
: Program Store Enable is the read strobe to
external Program Memory.
When the M87C51FC is executing code from external Program Memory, PSEN
is activated twice each
machine cycle, except that two PSEN
activations
are skipped during each access to external Data
Memory.
EA
/VPP: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFFH. Note, however, that if either of
the Program Lock bits are programmed, EA
will be
internally latched on reset.
EA should be strapped to VCCfor internal program
executions.
This pin also receives the programming supply voltage (V
PP
) during EPROM programming.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, ‘‘Oscillators for Microcontrollers.’’
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the V
IL
and VIHspecifications the capacitance will not exceed 20 pF.
271114–4
C1, C2
e
30 pFg10 pF for Crystals
e
10 pF for Ceramic Resonators
Figure 3. Oscillator Connections
4
M87C51FC
271114–5
Figure 4. External Clock Drive Configuration
IDLE MODE
The user’s software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs. The PCA timer/counter can
optionally be left running or paused during Idle
Mode.
POWER DOWN MODE
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
On the M87C51FC either a hardware reset or an
external interrupt can cause an exit from Power
Down. Reset redefines all the SFRs but does not
change the on-chip RAM. An external interrupt allows both the SFRs and on-chip RAM to retain their
values.
To properly terminate Power down the reset or external interrupt should not be executed before V
CC
is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
With an external interrupt, INT0 and INT1 must be
enabled and configured as level-sensitive. Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
DESIGN CONSIDERATION
#
The window on the M87C51FC must be covered
by an opaque label. Otherwise, the DC and AC
characteristics may not be met, and the device
may functionally be impaired.
#
When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing and debugging of systems using the
M87C51FC without the M87C51FC having to be removed from the circuit. The ONCE Mode is invoked
by:
1) Pull ALE low while the device is in reset and
PSEN
is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
go into a float state, and the other port pins and ALE
and PSEN
are weakly pulled high. The oscillator circuit remains active. While the M87C51FC is in this
mode, an emulator or test CPU can be used to drive
the circuit. Normal operation is restored when a normal reset is applied.
Table 1. Status of the External Pins during Idle and Power Down
Mode
Program
ALE PSEN PORT0 PORT1 PORT2 PORT3
Memory
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data
NOTE:
For more detailed information on the reduced power modes refer to Application Note AP-255, ‘‘Military CHMOS: Designing
with the M80C51BH.’’
5
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