Intel Corporation MQ80C196KB Datasheet

October 1993 Order Number: 271089-006

M80C196KB

16-BIT HIGH PERFORMANCE CHMOS

MICROCONTROLLER

Military

Y

232 Byte Register File

Y

Register-to-Register Architecture

Y

28 Interrupt Sources/16 Vectors

Y

2.3 ms 16 x 16 Multiply (12 MHz)

Y

4.0 ms 32/16 Divide (12 MHz)

Y

Powerdown and Idle Modes

Y

Five 8-Bit I/O Ports

Y

16-Bit Watchdog Timer

Y

Dynamically Configurable 8-Bit or
16-Bit Buswidth

Y

Available in 68-Lead PGA and 68-Lead
Ceramic Quad Flat Pack

Y

Full Duplex Serial Port

Y

High Speed I/O Subsystem

Y

16-Bit Timer

Y

16-Bit Up/Down Counter with Capture

Y

Pulse-Width-Modulated Output

Y

Four 16-Bit Software Timers

Y

10-Bit A/D Converter with S/H

Y

12 MHz Version Ð M80C196KB

Y

Available in Two Product Grades:
Ð MIL-STD-883,b55§Ctoa125§C(TC)
Ð Military Temperature Only (MTO),

b

55§Ctoa125§C(TC)

The M80C196KB 16-bit microcontroller is a high performance member of the MCSÉ-96 microcontroller family.
The M80C196KB is pin-for-pin compatible and uses a true superset of the M8096 instructions. Intel’s CHMOS
process provides a high performance processor along with low power consumption. To further reduce power
requirements, the processor can be placed into Idle or Powerdown Mode.

Bit, byte, word and some 32-bit operations are available on the M80C196KB. With a 12 MHz oscillator a 16-bit
addition takes 0.66 ms, and the instruction times average 0.5 ms to 1.5 ms in typical applications.

Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are
available for pulse or waveform generation. The high-speed output can also generate four software timers or
start an A/D conversion. Events can be based on the timer or up/down counter.

Also provided on-chip are an A/D converter with Sample and Hold, serial port, watchdog timer, and a pulse­width-modulated output signal.

271089–1

Figure 1. M80C196KB Block Diagram

M80C196KB

ARCHITECTURE

The M80C196KB is a member of the MCSÉ-96 family, and as such has the same architecture and uses the
same instruction set as the M8096. Many new features have been added on the M80C196KB including:

CPU FEATURES

Divide by 2 instead of divide by 3 clock for 1.5X performance

Faster instructions, especially indexed/indirect data operations

2.33 ms16

c

16 multiply with 12 MHz clock (was 6.25 ms) on the 8096

Faster interrupt response (almost twice as fast as 8096)

Powerdown and Idle Modes

6 new instructions including Compare Long and Block Move

8 new interrupt vectors/6 new interrupt sources

PERIPHERAL FEATURES

SFR Window switching allows read-only registers to be written and vice-versa

Timer2 can count up or down by external selection

Timer2 has an independent capture register

HSO line events are stored in a register

HSO has CAM Lock and CAM Clear commands

New Baud Rate values are needed for serial port, higher speeds possible in all modes

Double buffered serial port transmit register

Serial Port Receive Overrun and Framing Error Detection

PWM has a Divide-by-2 Prescaler

2

M80C196KB

NEW INSTRUCTIONS

PUSHA Ð PUSHes the PSW, IMASK, IMASK1, and WSR

(Used instead of PUSHF when new interrupts and registers are used.)

assembly language format: PUSHA

object code format:

k

11110100

l

bytes: 1

states: on-chip stack: 12

off-chip stack: 18

POPA Ð POPs the PSW, IMASK, IMASK1, and WSR

(Used instead of POPF when new interrupts and registers are used.)

assembly language format: POPA

object code format:

k

11110101

l

bytes: 1

states: on-chip stack: 12

off-chip stack:18

IDLPD Ð Sets the part into Idle or Powerdown Mode

assembly language format: IDLPD

Ý

key (keye1 for Idle, keye2 for Powerdown.)

object code format:k11110110lkkey

l

bytes: 2

states: legal key: 8

illegal key: 25

DJNZW Ð Decrement Jump Not Zero using a Word counter

assembly language format: DJNZW wreg, cadd

object code format:

k

11100001

lk

wreglkdisp

l

bytes: 3

states: jump not taken: 6

jump taken: 10

CMPL Ð Compare 2 long direct values

assembly language format: DST SRC

CMPL Lreg, Lreg

object code format:

k

11000101lksrc Lreglkdst Lreg

l

bytes: 3

states: 7

BMOV Ð Block move using 2 auto-incrementing pointers and a counter

assembly language format: PTRS CNTREG

BMOV Lreg, wreg

object code format:

k

11000001lkwreglkLreg

l

bytes: 3

states: internal/internal: 8 per transfera6

external/internal: 11 per transfer

a

6

external/external: 14 per transfer

a

6

3

M80C196KB

SFR OPERATION

All of the registers that were present on the M8096 work the same way as they did, except that the baud rate
value is different. The new registers shown in the memory map control new functions. The most important new
register is the Window Select Register (WSR) which allows reading of the formerly write-only registers and
vice-versa. Using the WSR is described later in this data sheet.

4

M80C196KB

PACKAGING

The M80C196KB is available in a ceramic pin grid array, shown in Figure 2, and a leaded ceramic quad pack
shown in Figure 3. A comparison of the pinouts for both of these package types is shown in Tables 1a – 1c.

271089–2

Figure 2. Pin Grid Array Pinout

5

M80C196KB

271089–3

Figure 3. 68-Lead Ceramic Quad Flat Pack Pinout

Table 1a. M80C196KB Pinout Ð in PGA Pin Order

PGA Signal

1 ACH7/P0.7
2 ACH6/P0.6
3 ACH2/P0.2
4 ACH0/P0.0
5 ACH1/P0.1
6 ACH3/P0.3
7 NMI
8EA
9V

CC

10 V

SS

11 XTAL1
12 XTAL2
13 CLKOUT
14 BUSWIDTH
15 INST
16 ALE/ADV
17 RD
18 AD0/P3.0
19 AD1/P3.1
20 AD2/P3.2
21 AD3/P3.3
22 AD4/P3.4
23 AD5/P3.5

PGA Signal

24 AD6/P3.6
25 AD7/P3.7
26 AD8/P4.0
27 AD9/P4.1
28 AD10/P4.2
29 AD11/P4.3
30 AD12/P4.4
31 AD13/P4.5
32 AD14/P4.6
33 AD15/P4.7
34 T2CLK/P2.3
35 READY
36 T2RST/P2.4/AINC
37 BHE/WRH
38 WR/WRL
39 PWM/P2.5
40 T2CAPTURE/P2.7/PACT
41 V

PP

42 V

SS

43 HS0.3
44 HS0.2
45 T2UP-DN/P2.6
46 P1.7

PGA Signal

47 P1.6
48 P1.5
49 HSO.1
50 HSO.0
51 HSO.5/HSI.3
52 HSO.4/HSI.2
53 HSI.1
54 HSI.0
55 P1.4
56 P1.3
57 P1.2
58 P1.1
59 P1.0
60 TXD/P2.0
61 RXD/P2.1
62 RESET
63 EXTINT/P2.2
64 V

SS

65 V

REF

66 ANGND
67 ACH4/P0.4
68 ACH5/P0.5

6

M80C196KB

Table 1b. M80C196KB Pinout Ð in CQFP Pin Order

CQFP Signal

1V

CC

2EA

3 NMI

4 ACH3/P0.3

5 ACH1/P0.1

6 ACH0/P0.0

7 ACH2/P0.2

8 ACH6/P0.6

9 ACH7/P0.7

10 ACH5/P0.5

11 ACH4/P0.4

12 ANGND

13 V

REF

14 V

SS

15 EXTINT/P2.2

16 RESET

17 RXD/P2.1

18 TXD/P2.0

19 P1.0

20 P1.1

21 P1.2

22 P1.3

23 P1.4

CQFP Signal

24 HSI.0

25 HSI.1

26 HSO.4/HSI.2

27 HSO.5/HSI.3

28 HSO.0

29 HSO.1

30 P1.5

31 P1.6

32 P1.7

33 T2UP-DN/P2.6

34 HSO.2

35 HSO.3

36 V

SS

37 V

PP

38 T2CAPTURE/P2.7/PACT

39 PWM/P2.5

40 WR

/WRL

41 BHE/WRH

42 T2RST/P2.4/AINC

43 READY

44 T2CLK/P2.3

45 AD15/P4.7

46 AD14/P4.6

CQFP Signal

47 AD13/P4.5

48 AD12/P4.4

49 AD11/P4.3

50 AD10/P4.2

51 AD9/P4.1

52 AD8/P4.0

53 AD7/P3.7

54 AD6/P3.6

55 AD5/P3.5

56 AD4/P3.4

57 AD3/P3.3

58 AD2/P3.2

59 AD1/P3.1

60 AD0/P3.0

61 RD

62 ALE/ADV

63 INST

64 BUSWIDTH

65 CLKOUT

66 XTAL2

67 XTAL1

68 V

SS

Table 1c. M80C196KB Pinout Ð in Signal Order

Signal PGA CQFP

ACH0/P0.0 4 6

ACH1/P0.1 5 5

ACH2/P0.2 3 7

ACH3/P0.3 6 4

ACH4/P0.4 67 11

ACH5/P0.5 68 10

ACH6/P0.6 2 8

ACH7/P0.7 1 9

P1.0 59 19

P1.1 58 20

P1.2 57 21

P1.3 56 22

P1.4 55 23

P1.5 48 30

P1.6 47 31

P1.7 46 32

TXD/P2.0 60 18

RXD/P2.1 61 17

EXTINT/P2.2 63 15

T2CLK/P2.3 34 44

T2RST/P2.4/AINC 36 42

PWM/P2.5 39 39

T2UP-DN/P2.6 45 33

Signal PGA CQFP

T2CAPTURE/P2.7/PACT

40 38

AD0/P3.0 18 60

AD1/P3.1 19 59

AD2/P3.2 20 58

AD3/P3.3 21 57

AD4/P3.4 22 56

AD5/P3.5 23 55

AD6/P3.6 24 54

AD7/P3.7 25 53

AD8/P4.0 26 52

AD9/P4.1 27 51

AD10/P4.2 28 50

AD11/P4.3 29 49

AD12/P4.4 30 48

AD13/P4.5 31 47

AD14/P4.6 32 46

AD15/P4.7 33 45

HSO.0 50 28

HSO.1 49 29

HSO.2 44 34

HSO.3 43 35

HSO.4/HSI.2 52 26

HSO.5/HSI.3 51 27

Signal PGA CQFP

HSI.0 54 24

HSI.1 53 25

RD

17 61

WR

/WRL 38 40

BHE

/WRH 37 41

BUSWIDTH 14 64

ALE/ADV

16 62

EA

82

INST 15 63

READY 35 43

NMI 7 3

RESET

62 16

XTAL1 11 67

XTAL2 12 66

CLKOUT 13 65

ANGND 66 12

V

REF

65 13

V

PP

41 37

V

CC

91

V

SS

10 68

V

SS

42 36

V

SS

64 14

7

M80C196KB

PIN DESCRIPTIONS

Symbol Name and Function

V

CC

Main supply voltage (5V).

V

SS

Digital circuit ground (0V). There are three VSSpins, all of which must be connected.

V

REF

Reference voltage for the A/D converter (5V). V

REF

is also the supply voltage to the
analog portion of the A/D converter and the logic used to read Port 0. Must be connected
for A/D and Port 0 to function.

ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as

V

SS

.

V

PP

Timing pin for the return from powerdown circuit. Connect this pin with a 1 mF capacitor to
V

SS

anda1MXresistor to VCC. If this function is not used VPPmay be tied to VCC. This

pin was V

BB

on the 8X9X-90 parts and is the programming voltage on EPROM part.

XTAL1 Input of the oscillator inverter and of the internal clock generator.

XTAL2 Output of the oscillator inverter.

CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator

frequency. It has a 50% duty cycle.

RESET Reset input to the chip. Input low for at least 4 state times to reset the chip. The

subsequent low-to-high transition re- synchronizes CLKOUT and commences a 10-state­time sequence in which the PSW is cleared, a byte read from 2018H loads CCR, and a
jump to location 2080H is executed. Input high for normal operation. RESET has an
internal pullup.

BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus

cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH isa0an
8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. This pin is the TEST
pin on 8X9X-90 parts. Systems with TEST tied to VCCdo not need to change.

8

M80C196KB

PIN DESCRIPTIONS (Continued)

Symbol Name and Function

NMI A positive transition causes a vector through 203EH.

INST Output high during an external memory read indicates the read is an instruction fetch. INST

is valid throughout the bus cycle. INST is activated only during external memory accesses
and output low for a data fetch.

EA EA must be equal to a TTL-low to cause address locations 2000H through 3FFFH to be

directed to off-chip memory.

ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options

provide a latch to demultiplex the address from the address/data bus. When the pin is
ADV

, it goes inactive high at the end of the bus cycle. ADV can be used as a chip select for

external memory. ALE/ADV

is activated only during external memory accesses.

RD Read signal output to external memory. RD is activated only during external memory

reads.

WR/WRL Write and Write Low output to external memory, as selected by the CCR. WR will go low

for every external write, while WRL

will go low only for external writes where an even byte

is being written. WR

/WRL is activated only during external memory writes.

BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE

e

0 selects the bank of memory that is connected to the high byte of the data bus. A0e0
selects the bank of memory that is connected to the low byte of the data bus. Thus
accesses to a 16-bit wide memory can be to the low byte only (A0e0, BHEe1), to the
high byte only (A0

e

1, BHEe0), or both bytes (A0e0, BHEe0). If the WRH function

is selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE

/

WRH

is valid only during 16-bit external memory write cycles.

READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic

memory, or for bus sharing. If the pin is high, CPU operation continues in a normal manner.
If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait
mode until the next positive transition in CLKOUT occurs with READY high. When the
external memory is not being used, READY has no effect. Internal control of the number of
wait states inserted into a bus cycle held not ready is available through configuration of
CCR.

HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2, and

HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit.

HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2,

HSO.3, HSO.4, and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit.

Port 0 8-bit high impedance input-only port. Three pins can be used as digital inputs and/or as

analog inputs to the on-chip A/D converter.

Port 1 8-bit quasi-bidirectional I/O port.

Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the M80C196KB.

Ports 3 and 4 8-bit bi-directional I/O ports with open drain outputs. These pins are shared with the

multiplexed address/data bus which has strong internal pullups.

9