Intel Corporation MC80C86, MC80C86-2 Datasheet
November 1989 Order Number: 271058-005
M80C86/M80C86-2
16-BIT CHMOS MICROPROCESSOR
MILITARY
Y
Pin-for-Pin and Functionally Compatible
to Industry Standard HMOS M8086
Y
Fully Static Design with Frequency
Range from D.C. to:
Ð 5 MHz for M80C86
Ð 8 MHz for M80C86-2
Y
Low Power Operation
Ð Operating I
CC
e
10 mA/MHz
Ð Standby I
CCS
e
500 mA max
Y
Bus-Hold Circuitry Eliminates Pull-Up
Resistors
Y
Direct Addressing Capability of
1 MByte of Memory
Y
Architecture Designed for Powerful
Assembly Language and Efficient High
Level Languages
Y
24 Operand Addressing Modes
Y
Byte, Word and Block Operations
Y
8 and 16-Bit Signed and Unsigned
Arithmetic
Ð Binary or Decimal
Ð Multiply and Divide
Y
Military Temperature Range:
b
55§Ctoa125§C(TC)
The Intel M80C86 is a high performance, CHMOS version of the industry standard HMOS M8086 16-bit CPU. It
is available in 5 and 8 MHz clock rates. The M80C86 offers two modes of operation: MINimum for small
systems and MAXimum for larger applications such as multiprocessing. It is available in 40-pin DIP package.
271058–1
Figure 1. M80C86 CPU Block Diagram
271058–2
Figure 2. M80C86 40-Lead DIP Configuration
M80C86/M80C86-2
Table 1. Pin Description
The following pin function descriptions are for M80C86 systems in either minimum or maximum mode. The
‘‘Local Bus’’ in these descriptions is the direct multiplexed bus interface connection to the M80C86 (without
regard to additional bus buffers).
Symbol Pin No. Type Name and Function
AD15–AD
0
2– 16, 39 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed
memory/IO address (T
1
) and data (T2,T3,TW,T4) bus. A0is
analogous to BHE
for the lower byte of the data bus, pins D7–D0.It
is LOW during T
1
when a byte is to be transferred on the lower
portion of the bus in memory or I/O operations. Eight-bit oriented
devices tied to the lower half would normally use A0to condition
chip select functions. (See BHE
.) These lines are active HIGH and
float to 3-state OFF
(1)
during interrupt acknowledge and local bus
‘‘hold acknowledge.’’
A19/S6, 35–38 O ADDRESS/STATUS: During T1these are the four most significant
A
18/S5
, address lines for memory operations. During I/O operations
A
17/S4
, these lines are LOW. During memory and I/O operations,
A16/S
3
status information is available on these lines during T2,T3,TW,
and T
4
. The status of the interrupt enable FLAG bit (S5) is updated
at the beginning of each CLK cycle. A
17/S4
and A16/S3are
encoded as shown.
This information indicates which relocation register is presently
being used for data accessing.
These lines float to 3-state OFF
(1)
during local bus ‘‘hold
acknowledge.’’
A17/S
4
A16/S
3
Characteristics
0 (LOW) 0 Alternate Data
0 1 Stack
1 (HIGH) 0 Code or None
1 1 Data
S
6
is 0
(LOW)
BHE/S
7
34 O BUS HIGH ENABLE/STATUS: During T1the bus high enable signal
(BHE
) should be used to enable data onto the most significant half
of the data bus, pins D
15–D8
. Eight-bit oriented devices tied to the
upper half of the bus would normally use BHE
to condition chip
select functions. BHE is LOW during T1for read, write, and interrupt
acknowledge cycles when a byte is to be transferred on the high
portion of the bus. The S
7
status information is available during T2,
T
3
, and T4. The signal is active LOW, and floats to 3-state OFF
(1)
in
‘‘hold.’’ It is LOW during T
1
for the first interrupt acknowledge cycle.
BHE A
0
Characteristics
0 0 Whole word
0 1 Upper byte from/
to odd address
1 0 Lower byte from/
to even address
1 1 None
2
M80C86/M80C86-2
Table 1. Pin Description (Continued)
Symbol Pin No. Type Name and Function
RD 32 O READ: Read strobe indicates that the processor is performing a
memory of I/O read cycle, depending on the state of the S
2
pin.
This signal is used to read devices which reside on the M80C86
local bus. RD is active LOW during T2,T3and TWof any read cycle,
and is guaranteed to remain HIGH in T
2
until the M80C86 local bus
has floated.
This floats to 3-state OFF in ‘‘hold acknowledge.’’
READY 22 I READY: is the acknowledgement from the addressed memory or
I/O device that it will complete the data transfer. The READY signal
from memory/IO is synchronized by the M82C84A Clock Generator
to form READY. This signal is active HIGH. The M80C86 READY
input is not synchronized. Correct operation is not guaranteed if the
setup and hold times are not met.
INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled
during the last clock cycle of each instruction to determine if the
processor should enter into an interrupt acknowledge operation. A
subroutine is vectored to via an interrupt vector lookup table
located in system memory. It can be internally masked by software
resetting the interrupt enable bit. INTR is internally synchronized.
This signal is active HIGH.
TEST 23 I TEST: input is examined by the ‘‘Wait’’ instruction. If the TEST input
is LOW execution continues, otherwise the processor waits in an
‘‘Idle’’ state. This input is synchronized internally during each clock
cycle on the leading edge of CLK.
NMI 17 I NON-MASKABLE INTERRUPT: an edge triggered input which
causes a type 2 interrupt. A subroutine is vectored to via an
interrupt vector lookup table located in system memory. NMI is not
maskable internally by software. A transition from a LOW to HIGH
initiates the interrupt at the end of the current instruction. This input
is internally synchronized.
RESET 21 I RESET: causes the processor to immediately terminate its present
activity. The signal must be active HIGH for at least four clock
cycles. It restarts execution, as described in the Instruction Set
description, when RESET returns LOW. RESET is internally
synchronized.
CLK 19 I CLOCK: provides the basic timing for the processor and bus
controller. It is asymmetric with a 33% duty cycle to provide
optimized internal timing.
V
CC
40 VCC:a5V power supply pin.
GND 1, 20 GROUND: Both must be connected.
MN/MX 33 I MINIMUM/MAXIMUM: indicates what mode the processor is to
operate in. The two modes are discussed in the following sections.
3
M80C86/M80C86-2
Table 1. Pin Description (Continued)
The following pin function descriptions are for the M80C86/M82C88 system in maximum mode (i.e.,
MN/MX
e
VSS). Only the pin functions which are unique to maximum mode are described; all other pin func-
tions are as described above.
Symbol Pin No. Type Name and Function
S2,S1,S
0
26–28 O STATUS: active during T4,T1, and T2and is returned to the passive
state (1,1,1) during T
3
or during TWwhen READY is HIGH. This
status is used by the M82C88 Bus Controller to generate all memory
and I/O access control signals. Any change by S
2,S1,S0
during T
4
is used to indicate the beginning of a bus cycle, and the return to the
passive state in T3or TWis used to indicate the end of a bus cycle.
These signals float to 3-state OFF
(1)
in ‘‘hold acknowledge.’’ These
status lines are encoded as shown.
S
2
S
1
S
0
Characteristics
0 (LOW) 0 0 Interrupt
Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1 (HIGH) 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
RQ/GT
0,
30, 31 I/O REQUEST/GRANT: pins are used by other local bus masters to
RQ
/GT
1
force the processor to release the local bus at the end of the
processor’s current bus cycle. Each pin is bidirectional with RQ
/GT
0
having higher priority than RQ/GT1.RQ/GT has an internal pull-up
resistor so may be left unconnected. The request/grant sequence is
as follows (see timing diagram):
1. A pulse of 1 CLK wide from another local bus master indicates a
local bus request (‘‘hold’’) to the M80C86 (pulse 1).
2. During a T4or T1clock cycle, a pulse 1 CLK wide from the
M80C86 to the requesting master (pulse 2), indicates that the
M80C86 has allowed the local bus to float and that it will enter the
‘‘hold acknowledge’’ state at the next CLK. The CPU’s bus interface
unit is disconnected logically from the local bus during ‘‘hold
acknowledge.’’
3. A pulse 1 CLK wide from the requesting master indicates to the
M80C86 (pulse 3) that the ‘‘hold’’ request is about to end and that
M80C86 can reclaim the local bus at the next CLK.
Each master-master exchange of the local bus is a sequence of 3
pulses. There must be one dead CLK cycle after each bus exchange.
Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle, it
will release the local bus during T
4
of the cycle when all the following
conditions are met:
1. Request occurs on or before T
2
.
2. Current cycle is not the low byte of a word (on an odd address).
3. Current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
4. A locked instruction is not currently executing.
4
M80C86/M80C86-2
Table 1. Pin Description (Continued)
Symbol Pin No. Type Name and Function
If the local bus is idle when the request is made the two possible
events will follow:
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a
currently active memory cycle apply with condition number 1 already
satisfied.
LOCK 29 O LOCK: output indicates that other system bus masters are not to gain
control of the system bus while LOCK
is active LOW. The LOCK
signal is activated by the ‘‘LOCK’’ prefix instruction and remains
active until the completion of the next instruction. This signal is active
LOW, and floats to 3-state OFF
(1)
in ‘‘hold acknowledge.’’
QS1,QS
0
24, 25 O QUEUE STATUS: The queue status is valid during the CLK cycle
after which the queue operation is performed.
QS
1
and QS0provide status to allow external tracking of the internal
M80C86 instruction queue.
QS
1
QS
0
Characteristics
0 (LOW) 0 No Operation
0 1 First Byte of Op Code from Queue
1 (HIGH) 0 Empty the Queue
1 1 Subsequent Byte from Queue
The following pin function descriptions are for the M80C86 in minimum mode (i.e., MN/MXeVCC). Only the
pin functions which are unique to minimum mode are described; all other pin functions are described above.
M/IO 28 O STATUS LINE: logically equivalent to S2in the maximum mode. It
is used to distinguish a memory access from an I/O access. M/IO
becomes valid in the T4preceding a bus cycle and remains valid
until the final T
4
of the cycle (MeHIGH, IOeLOW). M/IO floats to
3-state OFF
(1)
in local bus ‘‘hold acknowledge.’’
WR 29 O WRITE: indicates that the processor is performing a write memory
or write I/O cycle, depending on the state of the M/IO signal. WR is
active for T
2,T3
and TWof any write cycle. It is active LOW, and
floats to 3-state OFF
(1)
in local bus ‘‘hold acknowledge.’’
INTA 24 O INTA is used as a read strobe for interrupt acknowledge cycles. It is
active LOW during T
2,T3
and TWof each interrupt acknowledge
cycle.
ALE 25 O ADDRESS LATCH ENABLE: provided by the processor to latch
the address into an address latch. It is a HIGH pulse active during
T
1
of any bus cycle. Note that ALE is never floated.
DT/R 27 O DATA TRANSMIT/RECEIVE: needed in minimum system that
desires to use a data bus transceiver. It is used to control the
direction of data flow through the transceiver. Logically DT/R is
equivalent to S
1
in the maximum mode, and its timing is the same
as for M/IO.(TeHIGH, ReLOW.) This signal floats to 3-state
OFF
(1)
in local bus ‘‘hold acknowledge.’’
5
M80C86/M80C86-2
Table 1. Pin Description (Continued)
Symbol Pin No. Type Name and Function
DEN 26 O DATA ENABLE: provided as an output enable for the transceiver in
a minimum system which uses the transceiver. DEN
is active LOW
during each memory and I/O access and for INTA cycles. For a
read or INTA cycle it is active from the middle of T2until the middle
of T
4
, while for a write cycle it is active from the beginning of T
2
until the middle of T4. DEN floats to 3-state OFF
(1)
in local bus
‘‘hold acknowledge.’’
HOLD, 31, 30 I/O HOLD: indicates that another master is requesting a local bus
HLDA ‘‘hold.’’ To be acknowledged, HOLD must be active HIGH. The
processor receiving the ‘‘hold’’ request will issue HLDA (HIGH) as
an acknowledgement in the middle of a T
1
clock cycle.
Simultaneous with the issuance of HLDA the processor will float the
local bus and control lines. After HOLD is detected as being LOW,
the processor will LOWer the HLDA, and when the processor
needs to run another cycle, it will again drive the local bus and
control lines.
The same rules as for RQ/GT apply regarding when the local bus
will be released.
HOLD is not an asynchronous input. External synchronization
should be provided if the system cannot otherwise guarantee the
setup time.
NOTE:
1. See the section on Bus Hold Circuitry.
FUNCTIONAL DESCRIPTION
STATIC OPERATION
All M80C86 circuitry is of static design. Internal registers, counters and latches are static and require no
refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction
placed on other microprocessors. The CMOS
M80C86 can operate from DC to the appropriate upper frequency limit. The processor clock may be
stopped in either state (high/low) and held there indefinitely. This type of operation is especially useful
for system debug or power critical applications.
The M80C86 can be single stepped using only the
CPU clock. This state can be maintained as long as
is necessary. Single step clock operation allows simple interface circuitry to provide critical information
for bringing up your system.
Static design also allows very low frequency operation. In a power critical situation, this can provide
extremely low power operation since M80C86 power
dissipation is directly related to operating frequency.
As the system frequency is reduced, so is the operating power until, ultimately, at a DC input frequency,
the M80C86 power requirement is the standby current.
6
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