December 1990 Order Number: 271029-005
M80287
80-BIT HMOS*
NUMERIC PROCESSOR EXTENSION
Military
Y
High Performance 80-Bit Internal
Architecture
Y
Implements Proposed IEEE Floating
Point Standard 754
Y
Expands M80286/10 Datatypes to
Include 32-, 64-, 80-Bit Floating Point,
32-, 64-Bit Integers and 18-Digit BCD
Operands
Y
Object Code Compatible with M8087
Y
Built-In Exception Handling
Y
Operates in Both Real and Protected
Mode M80286 Systems
Y
Available in a 40-Pin Cerdip Package
Y
Protected Mode Operation Completely
Conforms to the M80286 Memory
Management and Protection
Mechanisms
Y
Directly Extends M80286/10 Instruction
Set to Trigonometric, Logarithmic,
Exponential and Arithmetic Instructions
for All Datatypes
Y
8 x 80-Bit, Individually Addressable,
Numeric Register Stack
Y
6, 8, 10 MHz
Y
Military Temperature Range:
b
55§Ctoa125§C(TC)
The Intel M80287 is a high performance numerics processor extension that extends the M80286/10 architecture with floating point, extended integer and BCD data types. The M80286/20 computing system (M80286
and M80287) fully conforms to the proposed IEEE Floating Point Standard. Using a numerics oriented architecture, the M80287 adds over fifty mnemonics to the M80286/20 instruction set, making the M80286/20 a
complete solution for high performance numeric processing. The M80287 is implemented in N-channel, depletion load, silicon gate technology (HMOS) and packaged in a 40-pin ceramic package. The M80286/20 is
object code compatible with the M80286/20 and M8088/20. Intel’s HMOS III process provides superior
radiation tolerance for applications with stringent radiation requirements.
*HMOS is a patented process of Intel Corporation.
271029–1
Figure 1. M80287 Block Diagram 271029–2
NOTE:
N.C. pins must not be connected.
Figure 2. M80287 Pin
Configuration
M80287
Table 1. M80287 Pin Description
Symbol Type Name and Function
CLK I CLOCK INPUT: This clock provides the basic timing for internal M80287
operations. Special MOS level inputs are required. The M82284 or M8284A
CLK outputs are compatible to this input.
CKM I CLOCK MODE SIGNAL: Indicates whether CLK input is to be divided by 3
or used directly. A HIGH input will select the latter option. This input may be
connected to V
CC
or VSSas appropriate. This input must be either HIGH or
LOW 20 CLK cycles before RESET goes LOW.
RESET I SYSTEM RESET: Causes the M80287 to immediately terminate its present
activity and enter a dormant state. RESET is required to be HIGH for more
than 4 M80287 CLK cycles. For proper initialization the HIGH-LOW
transition must occur no sooner than 50 ms after V
CC
and CLK meet their
D.C. and A.C. specifications.
D15– D0 I/O DATA: 16-bit bidirectional data bus. Inputs to these pins may be applied
asynchronous to the M80287 clock.
BUSY O BUSY STATUS: Asserted by the M80287 to indicate that it is currently
executing a command.
ERROR O ERROR STATUS: Reflects the ES bit of the status word. This signal
indicates that an unmasked error condition exists.
PEREQ O PROCESSOR EXTENSION DATA CHANNEL OPERAND TRANSFER
REQUEST: A HIGH on this output indicates that the M80287 is ready to
transfer data. PEREQ will be disabled upon assertion of PEACK or upon
actual data transfer, whichever occurs first, if no more transfers are required.
PEACK I PROCESSOR EXTENSION DATA CHANNEL OPERAND TRANSFER
ACKNOWLEDGE: Acknowledges that the request signal (PEREQ) has been
recognized. Will cause the request (PEREQ) to be withdrawn in case there
are no more transfers required. PEACK
may be asynchronous to the
M80287 clock.
NPRD I NUMERIC PROCESSOR READ: Enables transfer of data from the M80287.
This input may be asynchronous to the M80287 clock.
NPWR I NUMERIC PROCESSOR WRITE: Enables transfer of data to the M80287.
This input may be asynchronous to the M80287 clock.
NPS1, NPS2 I NUMERIC PROCESSOR SELECTS: Indicates the CPU is performing an
ESCAPE instruction. Concurrent assertion of these signals (i.e., NPS1
is
LOW and NPS2 is HIGH) enables the M80287 to perform floating point
instructions. No data transfers involving the M80287 will occur unless the
device is selected via these lines. These inputs may be asynchronous to the
M80287 clock.
CMD1, CMD0 I COMMAND LINES: These, along with select inputs, allow the CPU to direct
the operation of the M80287. No actions will occur if these signals are both
HIGH. These inputs may be asynchronous to the M80287 clock.
CLK286 I CPU CLOCK: This input provides a sampling edge for the M80287 inputs
S1
,S0, COD/INTA, READY, and HLDA. It must be connected to the
M80286 CLK input.
S1,S0 I STATUS: These inputs allow the M80287 to monitor the execution of
COD/INTA
ESCAPE instructions by the M80286. They must be connected to the
corresponding M80286 pins.
HLDA I HOLD ACKNOWLEDGE: This input informs the M80287 when the M80286
controls the local bus. It must be connected to the M80286 HLDA output.
READY I READY: The end of a bus cycle is signaled by this input. It must be
connected to the M80286 READY input.
V
SS
I GROUND: System ground, both pins must be connected to ground.
V
CC
I POWER:a5V supply.
2
M80287
FUNCTIONAL DESCRIPTION
The M80287 Numeric Processor Extension (NPX)
provides arithmetic instructions for a variety of numeric data types in M80286/20 systems. It also executes numerous built-in transcendental functions
(e.g., tangent and log functions). The M80287 executes instructions in parallel with an M80286. It effectively extends the register and instruction set of
an M80286/10 system for existing M80286 data
types and adds several new data types as well. Figure 3 presents the program visible register model of
the M80286/20. Essentially, the M80287 can be
treated as an additional resource or an extension to
the M80286/10 that can be used as a single unified
system, the M80286/20.
The M80287 has two operating modes similar to the
two modes of the M80286. when reset, M80287 is in
the real address mode. It can be placed in the protected virtual address mode by executing the
SETPM ESC instruction. The M80287 cannot be
switched back to the real address mode except by
reset. In the real address mode, the M80286/20 is
completely software compatible with M8086, 88/20.
Once in protected mode, all references to memory
for numerics data or status information, obey the
M80286 memory management and protection rules
giving a fully protected extension of the M80286
CPU. In the protected mode, M80286/20 numerics
software is also completely compatible with
M8086/20 and M8088/20.
The M80287 has two operating modes similar to the
two modes of the M80286. When reset, M80287 is
in the real address mode. It can be placed in the
protected virtual address mode by executing the
SETPM ESC instruction. The M80287 cannot be
switched back to the real address mode except by
reset. In the real address mode, the
M80286/M80287 is completely software compatible
with M8086/M8087 and M8088/M8087.
Once in protected mode, all references to memory
for numerics data or status information, obey the
M80286 memory management and protection rules
giving a fully protected extension of the M80286
CPU. In the protected mode, M80286/M80287 numerics software is also completely compatible with
M8086/M8087 and M8088/M8087.
271029–3
Figure 3. M80286/20 Architecture
3
M80287
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature under Biasb65§Ctoa150§C
Case Temperature АААААААААААААb55§Ctoa125§C
Voltage on any Pin with
Respect to Ground ААААААААААААААА
b
1.0 toa7V
Power Dissipation ААААААААААААААААААААААА3.0 Watt
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
*
WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Operating Conditions
Symbol Description Min Max Units
T
C
Case Temperature (Instant On)
b
55
a
125
§
C
V
CC
Digital Supply Voltage 4.75 5.25 V
D.C. CHARACTERISTICS (Over Specified Operating Conditions)
Symbol Parameter Min Max Unit Test Conditions
V
IL
Input LOW Voltage
b
0.5 0.8 V
V
IH
Input HIGH Voltage 2.0 V
CC
a
0.5 V
V
ILC
Clock Input LOW Voltage
CKM
e
1: 2.0 V
CC
a
1V
CKMe0: 3.8 V
CC
a
1V
VOLOutput LOW Voltage 0.45 V I
OL
e
3.0 mA
V
OH
Output HIGH Voltage 2.4 V I
OH
eb
400 mA
I
LI
Input Leakage Current
g
10 mA0V
s
V
IN
s
V
CC
I
LO
Output Leakage Current
g
10 mA 0.45VsV
OUT
s
V
CC
I
CC
Power Supply Current 600 mA T
C
eb
55§C
C
IN
Input Capacitance 10 pF F
C
e
1 MHz
C
O
Input/Output Capacitance 20 pF F
C
e
1 MHz
(D0– D15)
C
CLK
CLK Capacitance 12 pF F
C
e
1 MHz
4
M80287
A.C. CHARACTERISTICS (Over Specified Operating Conditions)
TIMING REQUIREMENTS
A.C. timings are referenced to 0.8V and 2.0V points on signals unless otherwise noted.
Symbol Parameter
6 MHz 8 MHz 10 MHz
Unit Comments
-6 Min -6 Max -8 Min -8 Max -10 Min -10 Max
T
CLCL
CLK Period
CKM
e
1 165 500 125 500 100 500 ns
CKM
e
0 62.5 166 50 166 40 166 ns
T
CLCH
CLK LOW Time
CKMe1 100 343 68 343 53 343 ns At 0.8V
CKMe0 15 146 15 146 11 146 ns At 0.6V
T
CHCL
CLK HIGH Time
CKM
e
1 50 230 43 230 28 230 ns At 2.0V
CKM
e
0 20 151 20 151 18 151 ns At 3.6V
T
CH1CH2
CLK Rise Time 10 10 10 ns 1.0V to 3.6V
if CKMe1
T
CL2CL1
CLK Fall Time 10 10 10 ns 3.6V to 1.0V
if CKM
e
1
T
DVWH
Data Setup to NPWR Inactive 75 75 75 ns
T
WHDX
Data Hold from NPWR Inactive 30 18 18 ns
T
WLWH
NPWR NPRD Active Time 95 90 90 ns At 0.8V
T
RLRH
T
AVRL
Command Valid to NPWR or 0 0 0 ns
T
AVWL
NPRD Active
T
MHRL
Minimum Delay from PEREQ 130 130 100 ns
Active to NPRD
Active
T
KLKH
PEAK Active Time 85 85 60 ns At 0.8V
T
KHKL
PEAK Inactive Time 250 250 200 ns At 2.0V
T
KHCH
PEAK Inactive to NPWR,50 40 40 ns
NPRD
Inactive
T
CHKL
NPWR NPRD Inactive to
b
30
b
30
b
30 ns
PEAK
Inactive
T
WHAX
Command Hold from NPWR 30 30 22 ns
T
RHAX
NPRD Inactive
T
KLCL
PEAK Active Setup to NPWR 50 40 40 ns
NPRD
Active
T
IVCL
NPWR, NPRD, RESET 70 70 53 ns
to CLK Setup Time
T
CLIH
NPWR, NPRD, RESET 45 45 37 ns
from CLK Hold Time
T
RSCL
RESET to CLK Setup Time 20 20 20 ns
T
CLRS
RESET from CLK Hold Time 20 20 20 ns
NOTE:
T
ja
e
41§C/W
T
jc
e
14§C/W
5
M80287
A.C. CHARACTERISTICS (Over Specified Operating Conditions)
TIMING RESPONSES
Symbol Parameter
6 MHz 8 MHz 10 MHz
Unit Comments
-6 Min -6 Max -8 Min -8 Max -10 Min -10 Max
T
RHQZ
NPRD Inactive to Data Float 37.5 35 25 ns (Note 2)
T
RLQV
NPRD Active to Data Valid 60 60 60 ns (Note 3)
T
ILBH
ERROR Active to BUSY 100 100 100 ns (Note 4)
Inactive
T
WLBV
NPWR Active to BUSY Active 100 100 100 ns (Note 5)
T
KLML
PEACK Active to PEREQ 127 127 127 ns (Note 6)
Inactive
T
CMDI
Command Inactive Time
Write-to-Write 95 95 75 ns At 2.0V
Read-to-Read 95 95 75 ns At 2.0V
Write-to-Read 95 95 75 ns At 2.0V
Read-to-Write 95 95 75 ns At 2.0V
T
RHCH
Data Hold from NPRD 3 3 3 ns (Note 7)
Inactive
NOTES:
2. Float condition occurs when output current is less than I
LO
on D0– D15.
3. D0– D15 loading: CL
e
100 pF.
4. BUSY
loading: CLe100 pF.
5. BUSY
loading: CLe100 pF.
6. On last data transfer of numeric instruction.
7. D0– D15 loading: CL
e
100 pF.
6
M80287
WAVEFORMS
DATA TRANSFER TIMING (Initiated by M80286)
271029–16
DATA CHANNEL TIMING (Initiated by M80287)
271029–17
7
M80287
WAVEFORMS (Continued)
ERROR OUTPUT TIMING
271029–18
CLK, RESET TIMING (CKMe1)
271029–19
NOTE:
Reset, NPWR
, NPRD are inputs asynchronous to CLK. Timing requirements for RESET, NPWR, and NPRD are given for
testing purposes only, to assure recognition at a specific CLK edge.
8