Intel Corporation MC28F008, MF28F008 Datasheet

*Other brands and names are the property of their respective owners.

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.

November 1994COPYRIGHT©INTEL CORPORATION, 1995 Order Number: 271232-004

M28F008

8 MBIT (1 MBIT x 8) FLASH MEMORY

Y

High-Density Symmetrically Blocked
Architecture
Ð Sixteen 64 Kbyte Blocks

Y

Extended Cycling Capability
Ð 10K Block Erase Cycles Minimum
Ð 160K Block Erase Cycles per Chip

Y

Automated Byte Write and Block Erase
Ð Command User Interface
Ð Status Register

Y

System Performance Enhancements
Ð RY/BY

Status Output

Ð Erase Suspend Capability

Y

SRAM-Compatible Write Interface

Y

Very High-Performance Read
Ð 100 ns Maximum Access Time

Y

Hardware Data Protection Feature
Ð Erase/Write Lockout during Power

Transitions

Y

Industry Standard Packaging
Ð 40-Lead Sidebrazed DIP
Ð 42-Lead Flatpack

Y

ETOXTMNonvolatile Flash Technology
Ð 12V Byte Write/Block Erase

Y

Independent Software Vendor Support
Ð Microsoft* Flash File System (FFS)

Intel’s M28F008 8-Mbit FlashFile Memory is the highest density nonvolatile read/write solution for solid state
storage. The M28F008’s extended cycling, symmetrically blocked architecture, fast access time, write automa­tion and low power consumption provide a more reliable, lower power, lighter weight and higher performance
alternative to traditional rotating disk technology. The M28F008 brings new capabilities to portable computing.
Application and operating system software stored in resident flash memory arrays provide instant-on, rapid
execute-in-place and protection from obsolescence through in-system software updates. Resident software
also extends system battery life and increases reliability by reducing disk drive accesses.

For high-density data acquisition applications, the M28F008 offers a more cost-effective and reliable alterna­tive to SRAM and battery. Traditional high density embedded applications, such as telecommunications, can
take advantage of the M28F008’s nonvolatility, blocking and minimal system code requirements for flexible
firmware and modular software designs.

The M28F008 is offered in 40-lead sidebrazed DIP and 42-lead Flatpack packages. This device uses an
integrated Command User Interface and state machine for simplified block erasure and byte write. The
M28F008 memory map consists of 16 separately erasable 64 Kbyte blocks.

Intel’s M28F008 employs advanced CMOS circuitry for systems requiring low power consumption and noise
immunity. Its 100 ns access time provides superior performance when compared with magnetic storage media.
A deep powerdown mode lowers power consumption to 500 mW maximum thru V

CC

. The RP power control

input also provides absolute data protection during system powerup/down.

Manufactured on Intel’s ETOX process technology, the M28F008 provides the highest levels of quality, reliabil­ity and cost-effectiveness.

*Microsoft is a trademark of Microsoft Corporation.

M28F008

PRODUCT OVERVIEW

The M28F008 is a high-performance 8 Mbit
(8,388,608 bit) memory organized as 1 Mbyte
(1,048,576 bytes) of 8 bits each. Sixteen 64 Kbyte
(65,536 byte) blocks are included on the M28F008.
A memory map is shown in Figure 4 of this specifica­tion. A block erase operation erases one of the six­teen blocks of memory in typically 1.6 seconds, in­dependent of the remaining blocks. Each block can
be independently erased and written 10,000 cycles.
Erase Suspend mode allows system software to
suspend block erase to read data or execute code
from any other block of the M28F008.

The M28F008 is available in 40-lead sidebrazed
DIP and 42-lead Flatpack packages. Pinouts are
shown in Figures 2a and 2b of this specification.

The Command User Interface serves as the inter­face between the microprocessor or microcontroller
and the internal operation of the M28F008.

Byte Write and Block Erase Automation allow
byte write and block erase operations to be execut­ed using a two-write command sequence to the
Command User Interface. The internal Write State
Machine (WSM) automatically executes the algo­rithms and timings necessary for byte write and
block erase operations, including verifications,
thereby unburdening the microprocessor or micro­controller. Writing of memory data is performed in
byte increments typically within 9 ms, an 80% im­provement over current flash memory products. I

PP

byte write and block erase currents are 30 mA
maximum. V

PP

byte write and block erase volt-

age is 11.4V to 12.6V.

The Status Register indicates the status of the
WSM and when the WSM successfully completes
the desired byte write or block erase operation.

The RY/BY

output gives an additional indicator of
WSM activity, providing capability for both hardware
signal of status (versus software polling) and status
masking (interrupt masking for background erase,
for example). Status polling using RY/BY minimizes
both CPU overhead and system power consump­tion. When low, RY/BY

indicates that the WSM is
performing a block erase or byte write operation.
RY/BY

high indicates that the WSM is ready for new
commands, block erase is suspended or the device
is in deep powerdown mode.

Maximum access time is 100 ns (t

ACC

) over the mili-

tary temperature range (

b

55§Ctoa125§C) and

over V

CC

supply voltage range 4.5V to 5.5V. ICCac-

tive current (CMOS Read) is 35 mA maximum at
8 MHz.

When the CE

and RP pins are at VCC, the ICCCMOS

Standby mode is enabled.

A Deep Powerdown mode is enabled when the RP
pin is at GND, minimizing power consumption and
providing write protection. I

CC

current in deep pow-

erdown is 100 mA maximum. Reset time of 400 ns
is required from RP

switching high until outputs are
valid to read attempts. Equivalently, the device has a
wake time of 1 m s from RP

high until writes to the
Command User Interface are recognized by the
M28F008. With RP

at GND, the WSM is reset and

the Status Register is cleared.

2

M28F008

271232– 1

Figure 1. Block Diagram

Table 1. Pin Description

Symbol Type Name and Function

A0–A

19

INPUT ADDRESS INPUTS for memory addresses. Addresses are internally

latched during a write cycle.

DQ0–DQ7INPUT/OUTPUT DATA INPUT/OUTPUTS: Inputs data and commands during Command

User Interface write cycles; outputs data during memory array, Status
Register and Identifier read cycles. The data pins are active high and
float to tri-state off when the chip is deselected or the outputs are
disabled. Data is internally latched during a write cycle.

CE INPUT CHIP ENABLE: Activates the device’s control logic, input buffers,

decoders, and sense amplifiers. CE

is active low; CE high deselects the

memory device and reduces power consumption to standby levels.

RP INPUT RESET/DEEP POWERDOWN: Puts the device in deep powerdown

mode. RP

is active low; RP high gates normal operation. RP also locks
out block erase or byte write operations when active low, providing data
protection during power transitions. RP

active resets internal

automation. Exit from Deep Powerdown sets device to read-array mode.

OE INPUT OUTPUT ENABLE: Gates the device’s outputs through the data buffers

during a read cycle. OE

is active low.

WE INPUT WRITE ENABLE: Controls writes to the Command User Interface and

array blocks. WE

is active low. Addresses and data are latched on the

rising edge of the WE pulse.

3

M28F008

Table 1. Pin Description (Continued)

Symbol Type Name and Function

RY/BY OUTPUT READY/BUSY: Indicates the status of the internal Write State Machine. When

low, it indicates that the WSM is performing a block erase or byte write operation.
RY/BY

high indicates that the WSM is ready for new commands, block erase is

suspended or the device is in deep powerdown mode. RY/BY

is always active and
does NOT float to tri-state off when the chip is deselected or data outputs are
disabled.

V

PP

BLOCK ERASE/BYTE WRITE POWER SUPPLY for erasing blocks of the array
or writing bytes of each block.

NOTE:

With V

PP

k

V

PPLMAX

, memory contents cannot be altered.

V

CC

DEVICE POWER SUPPLY (5Vg10%)

GND GROUND

271232– 2

Figure 2a. DIP Pinout

271232– 14

Figure 2b. Flatpack Pinout

4

M28F008

271232– 3

Figure 3. M28F008 Array Interface to Intel386TMSL Microprocessor Superset through PI Bus

(Including RY/BY

Masking and Selective Powerdown), for DRAM Backup during System SUSPEND,

Resident O/S and Applications and Motherboard Solid-State Disk.

PRINCIPLES OF OPERATION

The M28F008 includes on-chip write automation to
manage write and erase functions. The Write State
Machine allows for: 100% TTL-level control inputs,
fixed power supplies during block erasure and byte
write, and minimal processor overhead with RAM­like interface timings.

After initial device powerup, or after return from
deep powerdown mode (see Bus Operations), the
M28F008 functions as a read-only memory. Manipu­lation of external memory-control pins allow array
read, standby and output disable operations. Both
Status Register and intelligent identifier can

also be accessed through the Command User Inter­face when V

PP

e

V

PPL

.

This same subset of operations is also available
when high voltage is applied to the V

PP

pin. In addi-

tion, high voltage on V

PP

enables successful block
erasure and byte writing of the device. All functions
associated with altering memory contentsÐbyte
write, block erase, status and intelligent identifierÐ
are accessed via the Command User Interface and
verified thru the Status Register.

Commands are written using standard microproces­sor write timings. Command User Interface contents
serve as input to the WSM, which controls the block

5

M28F008

erase and byte write circuitry. Write cycles also inter­nally latch addresses and data needed for byte write
or block erase operations. With the appropriate com­mand written to the register, standard microproces­sor read timings output array data, access the intelli­gent identifier codes, or output byte write and block
erase status for verification.

Interface software to initiate and poll progress of in­ternal byte write and block erase can be stored in
any of the M28F008 blocks. This code is copied to,
and executed from, system RAM during actual flash
memory update. After successful completion of byte
write and/or block erase, code/data reads from the
M28F008 are again possible via the Read Array
command. Erase suspend/resume capability allows
system software to suspend block erase to read
data and execute code from any other block.

FFFFF

64 Kbyte Block

EFFFF

F0000

64 Kbyte Block

DFFFF

E0000

64 Kbyte Block

CFFFF

D0000

64 Kbyte Block

BFFFF

C0000

64 Kbyte Block

AFFFF

B0000

64 Kbyte Block

9FFFF

A0000

64 Kbyte Block

8FFFF

90000

64 Kbyte Block

7FFFF

80000

64 Kbyte Block

6FFFF

70000

64 Kbyte Block

5FFFF

60000

64 Kbyte Block

4FFFF

50000

64 Kbyte Block

3FFFF

40000

64 Kbyte Block

2FFFF

30000

64 Kbyte Block

1FFFF

20000

64 Kbyte Block

0FFFF

10000

64 Kbyte Block

00000

Figure 4. Memory Map

Command User Interface and Write
Automation

An on-chip state machine controls block erase and
byte write, freeing the system processor for other
tasks. After receiving the Erase Setup and Erase
Confirm commands, the state machine controls
block pre-conditioning and erase, returning progress
via the Status Register and RY/BY

output. Byte
write is similarly controlled, after destination address
and expected data are supplied. The program and
erase algorithms of past Intel Flash memories are
now regulated by the state machine, including pulse
repetition where required and internal verification
and margining of data.

Data Protection

Depending on the application, the system designer
may choose to make the V

PP

power supply switcha­ble (available only when memory byte writes/block
erases are required) or hardwired to V

PPH

. When

V

PP

e

V

PPL

, memory contents cannot be altered.
The M28F008 Command User Interface architecture
provides protection from unwanted byte write or
block erase operations even when high voltage is
applied to V

PP

. Additionally, all functions are dis-

abled whenever V

CC

is below the write lockout volt-

age V

LKO

, or when RP is at VIL. The M28F008 ac­commodates either design practice and encourages
optimization of the processor-memory interface.

The two-step byte write/block erase Command User
Interface write sequence provides additional soft­ware write protection.

BUS OPERATION

Flash memory reads, erases and writes in-system
via the local CPU. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.

Read

The M28F008 has three read modes. The memory
can be read from any of its blocks, and information
can be read from the intelligent identifier or Status
Register. V

PP

can be at either V

PPL

or V

PPH

.

The first task is to write the appropriate read mode
command to the Command User Interface (array, in­telligent identifier, or Status Register). The M28F008
automatically resets to Read Array mode upon initial
device powerup or after exit from deep powerdown.
The M28F008 has four control pins, two of which

6

M28F008

Table 2. Bus Operations

Mode Notes RP CE OE WE A0V

PP

DQ

0–7

RY/BY

Read 1, 2, 3 V

IHVIL

V

ILVIH

XXD

OUT

X

Output Disable 3 V

IHVILVIHVIH

X X High Z X

Standby 3 V

IHVIH

X X X X High Z X

PowerDown V

IL

X X X X X High Z V

OH

Intelligent Identifier (Mfr) V

IHVILVIL

V

IH

V

IL

X 89H V

OH

Intelligent Identifier (Device) V

IHVILVIL

V

IH

V

IH

X A2H V

OH

Write 3, 4, 5 V

IHVILVIHVIL

XX DINX

NOTES:

1. Refer to DC Characteristics. When V

PP

e

V

PPL

, memory contents can be read but not written or erased.

2. X can be V

IL

or VIHfor control pins and addresses, and V

PPL

or V

PPH

for VPP. See DC Characteristics for V

PPL

and V

PPH

voltages.

3. RY/BY

is VOLwhen the Write State Machine is executing internal block erase or byte write algorithms. It is VOHwhen the

WSM is not busy, in Erase Suspend mode or deep powerdown mode.

4. Command writes involving block erase or byte write are only successfully executed when V

PP

e

V

PPH

.

5. Refer to Table 3 for valid D

IN

during a write operation.

must be logically active to obtain data at the outputs.
Chip Enable (CE

) is the device selection control, and
when active enables the selected memory device.
Output Enable (OE

) is the data input/output (DQ0–

DQ

7

) direction control, and when active drives data

from the selected memory onto the I/O bus. RP

and

WE

must also be at VIH. Figure 8 illustrates read bus

cycle waveforms.

Output Disable

With OE at a logic-high level (VIH), the device out­puts are disabled. Output pins (DQ

0

–DQ7) are

placed in a high-impedance state.

Standby

CE at a logic-high level (VIH) places the M28F008 in
standby mode. Standby operation disables much of
the M28F008’s circuitry and substantially reduces
device power consumption. The outputs (DQ

0

–DQ7)
are placed in a high-impedence state independent of
the status of OE

. If the M28F008 is deselected dur­ing block erase or byte write, the device will continue
functioning and consuming normal active power until
the operation completes.

Deep Power-Down

The M28F008 offers a deep powerdown feature, en­tered when RP

is at VIL. Current draw thru VCCis
100 mA maximum in deep powerdown mode, with
current draw through V

PP

20 mA maximum. During

read modes, RP

at a logic-low level (VIL) deselects
the memory, places output drivers in a high-impe­dence state and turns off all internal circuits. The
M28F008 requires time t

PHQV

(see AC Characteris­tics-Read-Only Operations) after return from power­down until initial memory access outputs are valid.
After this wakeup interval, normal operation is re­stored. The Command User Interface is reset to
Read Array mode, and the upper 5 bits of the Status
Register are cleared to value 10000, upon return to
normal operation.

During block erase or byte write modes, RP

at a log-

ic-low level (V

IL

) will abort either operation. Memory
contents of the block being altered are no longer
valid as the data will be partially written or erased.
Time t

PHWL

after RP goes to logic-high (VIH) is re-

quired before another command can be written.

Intelligent Identifier Operation

The intelligent identifier operation outputs the manu­facturer code, 89H; and the device code, A2H for
the M28F008. The system CPU can then automati­cally match the device with its proper block erase
and byte write algorithms.

The manufacturer and device codes are read via the
Command User Interface. Following a write of 90H
to the Command User Interface, a read from ad­dress location 00000H outputs the manufacturer
code (89H). A read from address location 00001H
outputs the device code (A2H). It is not necessary to
have high voltage applied to V

PP

to read the intelli-

gent identifier from the Command User Interface.

7

M28F008

Table 3. Command Definitions

Command Cycles

Req’d

Bus

Notes

First Bus Cycle Second Bus Cycle

Operation Address Data Operation Address Data

Read Array/Reset 1 1 Write X FFH

Intelligent Identifier 3 2, 3, 4 Write X 90H Read IA IID

Read Status Register 2 3 Write X 70H Read X SRD

Clear Status Register 1 Write X 50H

Erase Setup/Erase Confirm 2 2 Write BA 20H Write BA D0H

Erase Suspend/Erase Resume 2 Write X B0H Write X D0H

Byte Write Setup/Write 2 2, 3, 5 Write WA 40H Write WA WD

Alternate Byte Write Setup/Write 2 2, 3, 5 Write WA 10H Write WA WD

NOTES:

1. Bus operations are defined in Table 2.

2. IA

e

Identifier Address: 00H for manufacturer code, 01H for device code.

BA

e

Address within the block being erased.

WA

e

Address of memory location to be written.

3. SRD

e

Data read from Status Register. See Table 4 for a description of the Status Register bits.

WD

e

Data to be written at location WA. Data is latched on the rising edge of WE.

IID

e

Data read from intelligent identifiers.

4. Following the intelligent identifier command, two read operations access manufacture and device codes.

5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command.

6. Commands other than those shown above are reserved by Intel for future device implementations and should not be
used.

Write

Writes to the Command User Interface enable read­ing of device data and intelligent identifier. They also
control inspection and clearing of the Status Regis­ter. Additionally, when V

PP

e

V

PPH

, the Command
User Interface controls block erasure and byte write.
The contents of the interface register serve as input
to the internal write state machine.

The Command User Interface itself does not occupy
an addressable memory location. The interface reg­ister is a latch used to store the command and ad­dress and data information needed to execute the
command. Erase Setup and Erase Confirm com­mands require both appropriate command data and
an address within the block to be erased. The Byte
Write Setup command requires both appropriate
command data and the address of the location to be
written, while the Byte Write command consists of
the data to be written and the address of the loca­tion to be written.

The Command User Interface is written by bringing
WE

to a logic-low level (VIL) while CE is low. Ad­dresses and data are latched on the rising edge of
WE

. Standard microprocessor write timings are

used.

Refer to AC Write Characteristics and the AC Wave­forms for Write Operations, Figure 9, for specific tim­ing parameters.

COMMAND DEFINITIONS

When V

PPL

is applied to the VPPpin, read opera­tions from the Status Register, intelligent identifier,
or array blocks are enabled. Placing V

PPH

on V

PP

enables successful byte write and block erase oper­ations as well.

Device operations are selected by writing specific
commands into the Command User Interface. Table
3 defines the M28F008 commands.

Read Array Command

Upon initial device powerup and after exit from deep
powerdown mode, the M28F008 defaults to Read
Array mode. This operation is also initiated by writing
FFH into the Command User Interface. Microproces­sor read cycles retrieve array data. The device re­mains enabled for reads until the Command User
Interface contents are altered. Once the internal
Write State Machine has started a block erase or
byte write operation, the device will not recognize

8

M28F008

Table 4. Status Register Definitions

WSMS ESS ES BWS VPPS R R R

76543210

SR.7

e

WRITE STATE MACHINE STATUS

1

e

Ready

0

e

Busy

SR.6

e

ERASE SUSPEND STATUS

1

e

Erase Suspended

0

e

Erase in Progress/Completed

SR.5

e

ERASE STATUS

1

e

Error in Block Erasure

0

e

Successful Block Erase

SR.4

e

BYTE WRITE STATUS

1

e

Error in Byte Write

0

e

Successful Byte Write

SR.3

e

VPPSTATUS

1

e

VPPLow Detect; Operation Abort

0

e

VPPOK

SR.2–SR.0

e

RESERVED FOR FUTURE

ENHANCEMENTS
These bits are reserved for future use and
should be masked out when polling the Status
Register.

NOTES:

RY/BY

or the Write State Machine Status bit must first
be checked to determine byte write or block erase com­pletion, before the Byte Write or Erase Status bit are
checked for success.

If the Byte Write AND Erase Status bits are set to ‘‘1’’s
during a block erase attempt, an improper command se­quence was entered. Attempt the operation again.

If V

PP

low status is detected, the Status Register must be
cleared before another byte write or block erase opera­tion is attempted.

The V

PP

Status bit, unlike an A/D converter, does not

provide continuous indication of V

PP

level. The WSM in-

terrogates the V

PP

level only after the byte write or block
erase command sequences have been entered and in­forms the system if V

PP

has not been switched on. The

V

PP

Status bit is not guaranteed to report accurate feed-

back between V

PPL

and V

PPH

.

the Read Array command, until the WSM has com­pleted its operation. The Read Array command is
functional when V

PP

e

V

PPL

or V

PPH

.

Intelligent Identifier Command

The M28F008 contains an intelligent identifier oper­ation, initiated by writing 90H into the Command
User Interface. Following the command write, a read
cycle from address 00000H retrieves the manufac­turer code of 89H. A read cycle from address 01H
returns the device code of A2H. To terminate the
operation, it is necessary to write another valid com­mand into the register. Like the Read Array com­mand, the intelligent identifier command is functional
when V

PP

e

V

PPL

or V

PPH

.

Read Status Register Command

The M28F008 contains a Status Register which may
be read to determine when a byte write or block
erase operation is complete, and whether that oper­ation completed successfully. The Status Register
may be read at any time by writing the Read Status
Register command (70H) to the Command User In­terface. After writing this command, all subsequent
read operations output data from the Status Regis­ter, until another valid command is written to the

Command User Interface. The contents of the
Status Register are latched on the falling edge of OE
or CE, whichever occurs last in the read cycle. OE or
CE

must be toggled to VIHbefore further reads to
update the Status Register latch. The Read Status
Register command functions when V

PP

e

V

PPL

or

V

PPH

.

Clear Status Register Command

The Erase Status and Byte Write Status bits are set
to ‘‘1’’s by the Write State Machine and can only be
reset by the Clear Status Register Command. These
bits indicate various failure conditions (see Table 4).
By allowing system software to control the resetting
of these bits, several operations may be performed
(such as cumulatively writing several bytes or eras­ing multiple blocks in sequence). The Status Regis­ter may then be polled to determine if an error oc­curred during that sequence. This adds flexibility to
the way the device may be used.

Additionally, the V

PP

Status bit (SR.3) MUST be re­set by system software before further byte writes or
block erases are attempted. To clear the Status
Register, the Clear Status Register command (50H)
is written to the Command User Interface. The Clear
Status Register command is functional when V

PP

e

V

PPL

or V

PPH

.

9