Intel Corporation MA80C186EB-8, MA80C186EB-16, MA80C186EB-13 Datasheet

April 1990 Order Number: 271214-002

M80C186EB-16, -13, -8

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

#

Full Static Operation

#

True CMOS Inputs and Outputs

#

b

55§Ctoa125§C Operating Temperature Range

Y

Integrated Feature Set
Ð Low-Power Static CPU Core
Ð Two Independent UARTs each with

an Integral Baud Rate Generator
Ð Two 8-Bit Multiplexed I/O Ports
Ð Programmable Interrupt Controller
Ð Three Programmable 16-Bit

Timer/Counters
Ð Clock Generator
Ð Ten Programmable Chip Selects with

Integral Wait-State Generator
Ð Memory Refresh Control Unit
Ð System Level Testing Support (ONCE

Mode)

Y

Direct Addressing Capability to 1 Mbyte
Memory and 64 Kbyte I/O

Y

Speed Versions Available:
Ð 16 MHz (M80C186EB-16)
Ð 13 MHz (M80C186EB-13)
Ð 8 MHz (M80C186EB-8)

Y

Low-Power Operating Modes:
Ð Idle Mode Freezes CPU Clocks but

keeps Peripherals Active

Ð Powerdown Mode Freezes All

Internal Clocks

Y

Complete System Development
Support
Ð ASM86 Assembler, PL/M 86, Pascal

86, Fortran 86, C-86, and System
Utilities

Ð In-Circuit Emulator (ICE

TM

-186EB)

Y

Supports M80C187 Numeric
Coprocessor Interface

Y

Available In:
Ð 88-Lead Pin Grid Array

(MG80C186EB)

The M80C186EB is a second generation CHMOS High-Integration microprocessor. It has features that are
new to the M80C186 family and include a STATIC CPU core, an enhanced Chip Select decode unit, two
independent Serial Channels, I/O ports, and the capability of Idle or Powerdown low power modes.

271214–1

M80C186EB-16, -13, -8

16-Bit High-Integration Embedded Processor

CONTENTS PAGE

INTRODUCTION ААААААААААААААААААААААААААА 4

OVERVIEW АААААААААААААААААААААААААААААААА 4

M80C186EB Core Architecture ААААААААААААА 4

Register Set ААААААААААААААААААААААААААААА 4
Instruction Set АААААААААААААААААААААААААА 5
Memory Organization ААААААААААААААААААА 5
Addressing Modes АААААААААААААААААААААА 5
Data Types ААААААААААААААААААААААААААААА 7
Interrupts ААААААААААААААААААААААААААААААА 7
Bus Interface Unit ААААААААААААААААААААААА 9
Clock Generator АААААААААААААААААААААААА 9

M80C186EB Peripheral Architecture ААААААА 10

Interrupt Control Unit ААААААААААААААААААА 10
Timer/Counter Unit АААААААААААААААААААА 10
Serial Communications Unit АААААААААААА 12
Chip-Select Unit АААААААААААААААААААААААА 12
I/O Port Unit ААААААААААААААААААААААААААА 13
Refresh Control Unit ААААААААААААААААААА 13
Power Management Unit ААААААААААААААА 13

M80C187 Interface АААААААААААААААААААААААА 13
ONCE Test Mode ААААААААААААААААААААААААА 13

PACKAGE INFORMATION ААААААААААААААА 14

Pin Descriptions ААААААААААААААААААААААААААА 14

M80C186EB PINOUT ААААААААААААААААААААА 19

ELECTRICAL SPECIFICATIONS ААААААААА 21

Absolute Maximum Ratings ААААААААААААААА 21

OPERATING CONDITIONS ААААААААААААААА 21

RECOMMENDED CONNECTIONS АААААААА 21

DC SPECIFICATIONS АААААААААААААААААААА 22

ICCversus Frequency and Voltage ААААААААА 23
PDTMR Pin Delay Calculation ААААААААААААА 23

CONTENTS PAGE

AC SPECIFICATIONS АААААААААААААААААААА 24

AC CharacteristicsÐM80C186EB-16 АААААА 24
AC CharacteristicsÐM80C186EB-13 АААААА 25
AC CharacteristicsÐM80C186EB-8 ААААААА 26
Relative Timings

(M80C186EB-16, -13, -8)

АААААААААААААААА 27

Serial Port Mode 0 Timings

(M80C186EB-16, -13, -8) АААААААААААААААА 28

AC TEST CONDITIONS АААААААААААААААААА 29

AC TIMING WAVEFORMS ААААААААААААААА 29

DERATING CURVES ААААААААААААААААААААА 32

RESET ААААААААААААААААААААААААААААААААААА 33

COLD RESET WAVEFORMS ААААААААААААА 34

WARM RESET WAVEFORMS АААААААААААА 35

BUS CYCLE WAVEFORMS АААААААААААААА 36

REGISTER BIT SUMMARY ААААААААААААААА 44

M80C186EB EXECUTION TIMINGS АААААА 48

INSTRUCTION SET SUMMARY АААААААААА 49

FOOTNOTES ААААААААААААААААААААААААААААА 54

88-LEAD CERAMIC PIN GRID ARRAY

PACKAGE

ААААААААААААААААААААААААААААА 55

ERRATA ААААААААААААААААААААААААААААААААА 56

REVISION HISTORY ААААААААААААААААААААА 56

2

M80C186EB

271214–2

Figure 1. M80C186EB Block Diagram

3

M80C186EB

INTRODUCTION

The M80C186EB is the first product in a new gener­ation of low-power, high-integration microproces­sors. It enhances the existing 186 family by offering
new features and new operating modes. The
M80C186EB is object code compatible with the
M80C186/M80C188 microprocessors.

The feature set of the M80C186EB meets the needs
of low power, space critical applications. Low-Power
applications benefit from the static design of the
CPU core and the integrated peripherals. Minimum
current consumption is achieved by providing a Pow­erdown mode that halts operation of the device, and
freezes the clock circuits. Peripheral design en­hancements ensure that non-initialized peripherals
consume little current.

Space critical applications benefit from the inte­gration of commonly used system peripherals. Two
serial channels are provided for services such as
diagnostics, inter-processor communication, modem
interface, terminal display interface, and many oth­ers. A flexible chip select unit simplifies memory and
peripheral interfacing. The interrupt unit provides
sources for up to 129 external interrupts and will pri­oritize these interrupts with those generated from
the on-chip peripherals. Three general purpose tim­er/counters and sixteen multiplexed I/O port pins
round out the feature set of the M80C186EB.

OVERVIEW

Figure 1 shows a block diagram of the M80C186EB.
The Execution Unit (EU) is an enhanced M8086
CPU core that includes: dedicated hardware to
speed up effective address calculations, enhance
execution speed for multiple-bit shift and rotate in­structions and for multiply and divide instructions,
string move instructions that operate at full bus
bandwidth, ten new instruction, and full static opera­tion. The Bus Interface Unit (BIU) is the same as that
found on the original 186 family products, except the
queue-status mode has been deleted and buffer in­terface control has been changed to ease system
design timings. An independent internal bus is used
to allow communication between the BIU and inter­nal peripherals.

M80C186EB Core Architecture

REGISTER SET

The M8086, M8088, M80186, M80C186 and
M80C188 all contain the same basic set of registers,
instructions, and addressing modes. The
M80C186EB is upward compatible with all of these
microprocessors.

The M80C186EB base architecture has fourteen
16-bit registers as shown in Figure 2. There are eight
general purpose registers which may be used for
arithmetic and logic operands. Four of these regis­ters (AX, BX, CX and DX) can be used as 16-bit
registers or split into pairs of separate 8-bit registers.
The other four registers (BP, SI, DI and SP) may also
be used to determine offset addresses of operands
in memory. These registers may contain base ad­dresses or indexes to particular locations within a
segment. The addressing mode selects the specific
registers for operand and address calculations.

Another four 16-bit registers (CS, DS, ES, SS) select
the segments of memory that are immediately ad­dressable for code, stack, and data. There are two
remaining special purpose registers (IP and F) that
record or alter certain aspects of the M80C186EB
processor state.

15 0

AH AL AX

BH BL BX

CH CL CX

DH DL DX

Source Index SI

Destination Index DI

Base Pointer BP

Stack Pointer SP

Code Segment CS

Stack Segment SS

Data Segment DS

Extra Segment ES

Instruction Pointer IP

Flags F

Figure 2. M80C186EB Register Set

4

M80C186EB

INSTRUCTION SET

The instruction set is divided into seven categories:
data transfer, arithmetic, shift/rotate/logical, string
manipulation, control transfer, high-level instruc­tions, and processor control. These categories are
summarized in Figure 4.

An M80C186EB instruction can reference anywhere
from zero to several operands. An operand can
reside in a register, in the instruction itself, or in
memory.

MEMORY ORGANIZATION

Memory is organized in sets of segments. Each seg­ment is a linear contiguous sequence of up to 64K
(2

16

) 8-bit bytes. Memory is addressed using a two­component address (a pointer) that consists of a
16-bit base segment and a 16-bit offset. The 16-bit
base segment values are contained in one of four
internal segment registers (code, data stack, extra).
The physical address is calculated by shifting the
base value left by four bits and adding the 16-bit
offset value to yield a 20-bit physical address (see
Figure 3). The resulting 20-bit address allows for a
1 Mbyte address range.

271214–3

Figure 3. Two Component Address

All instructions that address operands in memory
must specify the base segment and the 16-bit offset
value. For speed and compact instruction encoding,
the segment register used for a physical address
generation is implied by the addressing mode used
(see Table 1). Special segment override instruction
prefixes allow the implicit segment register selection
rules to be overridden for special cases. The code,
stack, data, and extra segments may coincide for
simple programs.

Table 1. Segment Register Selection Rules

Memory Segment

Implicit Segment

Reference Register

Selection Rule

Needed Used

Instructions Code (CS) Instruction prefetch and

immediate data

Stack Stack (SS) All stack pushes and pops;

any memory references
which use the BP register
as a base

External Extra (ES) All String instruction

references which use the
DI register as an index

Local Data Data (DS) All other data references

ADDRESSING MODES

The M80C186EB provides eight categories of ad­dressing modes to specify operands. Two address­ing modes are provided for instructions that operate
on register or immediate operands:

#

Register Operand Mode:

The operand is located

in one of the 8- or 16-bit general registers.

#

Immediate Operand Mode:

The operand is in-

cluded in the instruction.

Six modes are provided to specify the location of an
operand in a memory segment. A memory operand
address consists of two 16-bit components: a seg­ment base and an offset. The segment base is sup­plied by a 16-bit segment register either implicitly
chosen by the addressing mode or explicitly chosen
by a segment override prefix. The offset, also called
the effective address, is calculated by summing any
combination of the following three address ele­ments:

#

the

displacement

(an 8- or 16-bit immediate value

contained in the instruction);

#

the

base

(contents of either the BX or BP base

registers); and

#

the

index

(contents of either the SI or DI index

registers).

5

M80C186EB

GENERAL PURPOSE

MOV

PUSH

POP

PUSHA

POPA
XCHG

XLAT

INPUT/OUTPUT

IN

OUT

ADDRESS OBJECT

LEA

LDS

LES

FLAG TRANSFER

LAHF

SAHF

PUSHF

POPF

ADDITION

ADD

INC
AAA
DAA

SUBSTRACTION

SUB
SBB
DEC

NEG
CMP

AAS
DAS

MULTIPLICATION

MUL

IMUL

AAM

DIVISION

DIV

IDIV

AAD
CBW
CWD

STRING OPERATIONS

MOVS

INS

OUTS

CMPS

SCAS
LODS
STOS

REP

REPE/REPZ

REPNE/REPNZ

LOGICALS

NOT

AND

OR

XOR

TEST

SHIFTS

SHL/SAL

SHR

SAR

ROTATES

ROL
ROR

RCL

RCR

FLAG OPERATIONS

STC

CLC
CMC

STD

CLD

STI
CLI

EXTERNAL

SYNCHRONIZATION

HLT

WAIT

LOCK

NO OPERATION

NOP

HIGH LEVEL INSTRUCTIONS

ENTER

LEAVE

BOUND

CONDITIONAL TRANSFERS

JA/JNBE
JAE/JNB
JB/JNAE
JBE/JNA

JC

JE/JZ
JG/JNLE
JGE/JNL
JL/JNGE
JLE/JNG

JNC

JNE/JNZ

JNO

JNP/JP0

JNS

JO

JP/JPE

JS

UNCONDITIONAL TRANSFERS

CALL

RET
JMP

ITERATION CONTROLS

LOOP

LOOPE/LOOPZ

LOOPNE/LOOPNZ

JCXZ

INTERRUPTS

INT

INTO

IRET

Figure 4. M80C186EB Instruction Set

6

M80C186EB

Any carry out from the 16-bit addition is ignored.
8-bit displacements are sign extended to 16-bit val­ues.

Combinations of these three address elements de­fine the six memory addressing modes, described
below.

#

Direct Mode:

The operand’s offset is contained in
the instruction as an 8- or 16-bit displacement el­ement.

#

Register Indirect Mode:

The operand’s offset is in

one of the registers SI, DI, BX, or BP.

#

Based Mode:

The operand’s offset is the sum of
an 8- or 16-bit displacement and the contents of
a base register (BX or BP).

#

Indexed Mode:

The operand’s offset is the sum
of an 8- or 16-bit displacement and the contents
of an index register (SI or DI).

#

Based Indexed Mode:

The operand’s offset is the
sum of the contents of a base register and an
index register.

#

Based Indexed Mode with Displacement:

The op­erand’s offset is the sum of a base register’s con­tents, an index register’s contents, and an 8- or
16-bit displacement.

DATA TYPES

The M80C186EB directly supports the following data
types:

#

Integer:

A signed binary numeric value contained
in an 8-bit byte or 16-bit word. All operations as­sume a 2’s complement representation. Signed
32- and 64-bit integers are supported using the
M80C187 Numerics Coprocessor.

#

Ordinal:

An unsigned binary numeric value con-

tained in an 8-bit byte or 16-bit word.

#

Pointer:

A 16- or 32-bit quantity, composed of a
16-bit offset component, or a 16-bit segment
base component and a 16-bit offset component.

#

String:

A contiguous sequence of bytes or words.

A string may contain from 1 Kbyte to 64 Kbytes.

#

ASCII:

A byte representation of alphanumeric and
control characters using the ASCII standard of
character representation.

#

BCD:

A byte (unpacked) representation of the

decimal digits 0 – 9.

#

Packed BCD:

A byte (packed) representation of
two decimal digits (0 –9). One digit is stored in
each nibble (4 bits) of the byte.

#

Floating Point:

A signed 32-, 64- or 80-bit real
number representation. Floating point operands
are supported when using the M80C187 Numeric
Coprocessor.

In general, individual data elements must fit within
defined segment limits.

INTERRUPTS

An interrupt transfers execution to a new program
location. The old program address (CS:IP) and ma­chine state (F) are saved on the stack to allow re­sumption of the interrupted program. Interrupts fall
into three classes: hardware initiated, software (pro­gram) initiated, and instruction exception initiated.
Hardware initiated interrupts occur in response to an
external or internal input and are classified as non­maskable or maskable.

Programs may cause an interrupt by executing the
‘‘INT’’ instruction. Instruction exceptions occur when
an illegal opcode has been fetched into the queue
and is read by the execution unit. Another type of
exception can be generated when executing an
‘‘ESC’’ instruction.

For all cases except the ‘‘ESC’’ exception, the return
address from an exception will point at the instruc­tion immediately following the instruction causing
the exception. The return address after an ‘‘ESC’’
exception will point back to the ESC instruction
causing the exception, or to the segment override
prefix immediately preceding the ESC instruction if
the prefix was present.

A table containing up to 256 pointers defines the
proper interrupt service routine for each interrupt. In­terrupts 0– 31 are reserved by Intel. Table 2 shows
the M80C186EB predefined type and default priority
levels. For each interrupt, an 8-bit vector (Vector
Type) identifies the appropriate table entry. Multiply­ing the 8-bit vector by 4 defines the vector address.
INT instructions contain or imply the vector type and
allow access to all 256 interrupts.

7

M80C186EB

Table 2. M80C186EB Interrupt Vectors

Interrupt Vector Vector Default Related

Name Type Address Priority Instructions

Divide Error 0 00H 1 DIV, IDIV

Single Step Interrupt 1 04H 1A All

Non-Maskable Interrupt 2 08H 1 INT 2 or NMI

One Byte Interrupt 3 0CH 1 INT

Interrupt on Overflow 4 10H 1 INT0

Array Bounds Check 5 14H 1 BOUND

Invalid OP-Code 6 18H 1 Illegal Inst

ESC OP-Code Interrupt 7 1CH 1 ESC OP-Codes

Timer 0 Interrupt 8 20H 2

Reserved 9– 11 24H–2CH

INT0 Interrupt 12 30H 5

INT1 Interrupt 13 34H 6

INT2 Interrupt 14 38H 7

INT3 Interrupt 15 3CH 8

Numerics Exception 16 40H 1 ESC OP-Codes

INT4 Interrupt 17 44H 4

Timer1 Interrupt 18 48H 2A

Timer2 Interrupt 19 4CH 2B

UART 0 Receive Interrupt 20 50H 3

UART 0 Transmit Interrupt 21 54H 3A

Reserved 22– 31 58H– 7CH

8

M80C186EB

BUS INTERFACE UNIT

The M80C186EB core incorporates a bus controller
that generates local bus control signals. In addition,
it employs a HOLD/HLDA protocol to share the local
bus with other bus masters.

The bus controller is responsible for generating 20
bits of address, read and write strobes, bus cycle
status information, and data (for write operations) in­formation. It is also responsible for reading data off
the local bus during a read operation. A READY in­put pin is provided to extend a bus cycle beyond the
minimum four states (clocks).

A HOLD/HLDA protocol is provided by the local bus
controller to allow multiple bus masters to share the
same local bus. When the M80C186EB relinquishes
control of the local bus, it floats certain bus control
signals to allow another bus master to drive these
pins directly. Refer to the Pin Description section to
determine which pins the M80C186EB will float dur­ing a HOLD/HLDA bus exchange.

The M80C186EB local bus controller also generates
two control signals (DEN

and DT/R) when interfac­ing to external transceiver chips. This capability al­lows the addition of transceivers for simple buffering
of the mulitplexed address/data bus.

CLOCK GENERATOR

The M80C186EB provides an on-chip clock genera­tor for both internal and external clock generation.
The clock generator features a crystal oscillator, a
divide-by-two counter, and two low-power operating
modes.

The oscillator circuit is designed to be used with ei­ther a parallel resonant fundamental or third-over­tone mode crystal network. Alternatively, the oscilla­tor circuit may be driven from an external clock
source. Figure 5 shows the various operating modes
of the M80C186EB oscillator circuit.

The crystal or clock frequency chosen must be twice
the required processor operating frequency due to
the internal divide-by-two counter. This counter is
used to drive all internal phase clocks and the exter­nal CLKOUT signal. CLKOUT is a 50% duty cycle
processor clock and can be used to drive other sys­tem components. All AC timings are referenced to
CLKOUT.

The following parameters are recommended when
choosing a crystal:

Temperature Range: Application Specific
ESR (Equivalent Series Resistance): 40X max
C0 (Shunt Capacitance of Crystal): 7.0 pF max
C

L

(Load Capacitance): 20 pFg2pF

Drive Level: 1 mW max

271214–4

(A) Crystal Connection

NOTE:

The L

1C1

network is only required when using a third-

overtone crystal.

271214–5

(B) Clock Connection

Figure 5. M80C186EB Clock Configurations

9

M80C186EB

M80C186EB Peripheral Architecture

The M80C186EB has integrated several common
system peripherals with a CPU core to create a com­pact, yet powerful system. The integrated peripher­als are designed to be flexible and provide logical
interconnections between supporting units (e.g., the
interrupt control unit supports interrupt requests
from the timer/counters or serial channels).

The list of integrated peripherals include:

#

7-Input Interrupt Control Unit

#

3-Channel Timer/Counter Unit

#

2-Channel Serial Communications Unit

#

10-Output Chip-Select Unit

#

I/O Port Unit

#

Refresh Control Unit

#

Power Management Unit

The registers associated with each integrated peri­heral are contained within a 128 x 16 register file
called the Peripheral Control Block (PCB). The PCB
can be located in either memory or I/O space on
any 256 Byte address boundary. During bus cycles
that access the PCB, the bus controller will signal
the operation externally (i.e., the RD,WR, status,
address, data, etc., lines will be driven as in a normal
bus cycle). However, READY is ignored and the con­tents of the data bus during a read operation is ig­nored.

The starting address of the PCB is controlled by a
relocation register and can overlap any of the mem­ory or I/O regions programmed into the Chip Select
Unit. In this case, the overlapped chip select will not
go active when the PCB is read or written.

Figure 6 provides a list of the registers associated
with the PCB. The Register Bit Summary at the end
of this specification individually lists all of the regis­ters and identifies each of their programming attri­butes.

INTERRUPT CONTROL UNIT

The M80C186EB can receive interrupts from a num­ber of sources, both internal and external. The inter­rupt control unit serves to merge these requests on
a priority basis, for individual service by the CPU.
Each interrupt source can be independently masked
by the Interrupt Control Unit (ICU) or all interrupts
can be globally masked by the CPU.

Internal interrupt sources include the Timers and Se­rial channel 0. External interrupt sources come from
the five input pins INT4:0. The NMI interrupt pin is
not controlled by the ICU and is passed directly to
the CPU. Although the Timer and Serial channel
each have only one request input to the ICU, sepa­rate vector types are generated to service individual
interrupts within the Timer and Serial channel units.

The M80C186EB ICU provides a mechanism for ex­panding the number of external interrupt sources.
Two pairs of pins can be independently configured
to support an external slave interrupt controller
(82C59A). Each pair of external pins can be expand­ed to support 64 interrupts, making it possible for the
M80C186EB to support a total of 129 external inter­rupts.

The ICU may be used in a polled mode if interrupts
are undesirable. When polling, the processor dis­ables interrupts and then polls the ICU whenever it is
convenient.

TIMER/COUNTER UNIT

The M80C186EB Timer/Counter Unit (TCU) pro­vides three 16-bit programmable timers. Two of
these are highly flexible and are connected to exter­nal pins for control or clocking. A third timer is not
connected to any external pins and can only be
clocked internally. However, it can be used to clock
the other two timer channels. The TCU can be used
to count external events, time external events, gen­erate non-repetitive waveforms, generate timed in­terrupts, etc.

Each timer has at least one 16-bit compare register
and one 16-bit count register. Timers 0 and 1 each
have an additional 16-bit compare register. The
count register is incremented every fourth CPU clock
cycle (internal clocking), every time Timer2 expires
(Timers 0 and 1 only), or every Low-to-High tran­sition on the timer input pin (Timers 0 and 1 only).
The input clock to Timers 0 and 1 must not exceed
one fourth the operating frequency of the
M80C186EB. When the count register matches the
value programmed into the compare register, sever­al operations may happen.

All three timers can generate an interrupt when the
compare register matches the value in the count
register. Additionally, Timers 0 and 1 have an output
pin that can change state or pulse when the com­pare condition occurs.

10

M80C186EB

PCB

Function

Offset

00H Reserved

02H End Of Interrupt

04H Poll

06H Poll Status

08H Interrupt Mask

0AH Priority Mask

0CH In-Service

0EH Interrupt Request

10H Interrupt Status

12H Timer Control

14H Serial Control

16H INT4 Control

18H INT0 Control

1AH INT1 Control

1CH INT2 Control

1EH INT3 Control

20H Reserved

22H Reserved

24H Reserved

26H Reserved

28H Reserved

2AH Reserved

2CH Reserved

2EH Reserved

30H Timer0 Count

32H Timer0 Compare A

34H Timer0 Compare B

36H Timer0 Control

38H Timer1 Count

3AH Timer1 Compare A

3CH Timer1 Compare B

3EH Timer1 Control

PCB

Function

Offset

40H Timer2 Count

42H Timer2 Compare

44H Reserved

46H Timer2 Control

48H Reserved

4AH Reserved

4CH Reserved

4EH Reserved

50H Reserved

52H Port0 Pin

54H Port0 Control

56H Port0 Latch

58H Port1 Direction

5AH Port1 Pin

5CH Port1 Control

5EH Port1 Latch

60H Serial0 Baud

62H Serial0 Count

64H Serial0 Control

66H Serial0 Status

68H Serial0 RBUF

6AH Serial0 TBUF

6CH Reserved

6EH Reserved

70H Serial1 Baud

72H Serial1 Count

74H Serial1 Control

76H Serial1 Status

78H Serial1 RBUF

7AH Serial1 TBUF

7CH Reserved

7EH Reserved

PCB

Function

Offset

80H GCS0 Start

82H GCS0 Stop

84H GCS1 Start

86H GCS1 Stop

88H GCS2 Start

8AH GCS2 Stop

8CH GCS3 Start

8EH GCS3 Stop

90H GCS4 Start

92H GCS4 Stop

94H GCS5 Start

96H GCS5 Stop

98H GCS6 Start

9AH GCS6 Stop

9CH GCS7 Start

9EH GCS7 Stop

A0H LCS Start

A2H LCS Stop

A4H UCS Start

A6H UCS Stop

A8H Relocation

AAH Reserved

ACH Reserved

AEH Reserved

B0H Refresh Base

B2H Refresh Time

B4H Refresh Control

B6H Refresh Address

B8H Power Control

BAH Reserved

BCH Step ID

BEH Reserved

PCB

Function

Offset

C0H Reserved

C2H Reserved

C4H Reserved

C6H Reserved

C8H Reserved

CAH Reserved

CCH Reserved

CEH Reserved

D0H Reserved

D2H Reserved

D4H Reserved

D6H Reserved

D8H Reserved

DAH Reserved

DCH Reserved

DEH Reserved

E0H Reserved

E2H Reserved

E4H Reserved

E6H Reserved

E8H Reserved

EAH Reserved

ECH Reserved

EEH Reserved

F0H Reserved

F2H Reserved

F4H Reserved

F6H Reserved

F8H Reserved

FAH Reserved

FCH Reserved

FEH Reserved

Figure 6. M80C186EB Peripheral Control Block Registers

11

M80C186EB

Other timer programming options include:

#

All three timers can be set to halt or continue
after a compare match.

#

Timers 0 and 1 can be reset or retriggered using
their respective input pins.

#

TCU registers can be read or written at any time.

SERIAL COMMUNICATIONS UNIT

The Serial Control Unit (SCU) of the M80C186EB
contains two independent channels. Each channel is
identical in operation except that only channel 0 is
supported by the integrated interrupt controller
(channel 1 has an external interrupt pin). Each
channel has its own baud rate generator that is in­dependent of the Timer/Counter Unit, and can be
internally or externally clocked at up to one half the
M80C186EB operating frequency.

Each serial channel supports one synchronous and
four asynchronous modes of operation and is com­patible with the serial ports of the MCS

É

-51 and

MCS

É

-96 family of products. Data field length can
be 7-, 8-, or 9-bits with optional odd or even parity
(generated and checked) and one stop bit (generat­ed and checked). The 9-bit mode has an optional
‘‘addressing’’ feature to simplify interprocessor com­munication. Each serial port is doubled buffered in
both transmit and receive operation (data can be
read or written to a buffer register while data is shift­ed into or out of a shifting register, respectively).

A Clear-To-Send input pin can be programmed to
prevent data transmission if the pin is sampled inac­tive. Serial channel 0 is supported by the integrated
interrupt controller, providing separate receive and
transmit vector types. Serial channel 1 has an exter­nal interrupt pin which OR’s the receive and transmit
interrupts. This external interrupt pin can be routed
to either the external pins of the ICU, the NMI pin, or
any other external system interrupt controller. Status
bits are provided to allow polling of the serial chan­nels if interrupts are not desired.

Independent baud rate generators are provided for
each of the serial channels. For the asynchronous
modes, the generator supplies an 8x baud clock to
both the receive and transmit register logic. A 1x
baud clock is provided in the synchronous mode.

Additional features of the SCU include:

#

Framing error, receive buffer overrun error, and
parity error detection.

#

Break detect.

#

Break send.

CHIP-SELECT UNIT

The M80C186EB Chip-Select Unit (CSU) integrates
logic which provides up to ten programmable chip­selects to access both memories and peripherals. In
addition, each chip-select can be programmed to
automatically insert additional clocks (wait-states)
into the current bus cycle and automatically termi­nate a bus cycle independent of the condition of the
READY input pin.

Each of the chip-selects can be programmed to go
active for either memory or I/O accesses. UCS

is
the only chip-select that is active after a reset and is
enabled for memory addresses in the range
0FFC00H to 0FFFFFH (this allows a boot-ROM to
be accessed using UCS

). Every chip-select has a
programmable start and stop register that defines
the active region for the chip-select, and the ready
characteristics for the region.

The start and stop address fields are 10 bits in
length and are matched against the upper 10 bits of
either the memory or I/O address. A 10-bit compare
results in a granularity of 1 Kbytes for memory ac­cesses and 64 bytes for I/O accesses. Each chip
select can be disabled by programming its start ad­dress greater than its stop address or by clearing its
enable bit.

Each chip-select can be programmed to automati­cally insert wait-states, and to control whether the
external READY input is to be ignored or used. The
M80C186EB bus controller will wait the programmed
number of wait-states before the external READY
pin can be used to extend or terminate the bus cy­cle.

Overlapping of chip-selects is allowed. However,
each one that overlaps will go active. If any overlap­ping chip-select has been programmed to use exter­nal ready, the bus control unit will insert the least
amount of programmed wait-states programmed be­fore the external ready pin is used. If all overlapped
chip-selects ignore external ready, the bus controller
will insert the maximum number of programmed
wait-states. Any chip-select that overlaps the Periph­eral Control Block (PCB) will not go active for that
portion of the address range allocated to the PCB.

12

M80C186EB

The Generic Chip-Selects (GCS7:0) are multiplexed
with an output only Port function. Any channel that is
being used as a chip-select must be disabled as a
port pin by correctly programming the port pin con­trol registers (see the following section).

I/O PORT UNIT

The I/O Port Unit (IPU) on the M80C186EB supports
two 8-bit channels of input, output, or input/output
operation. Port 1 is multiplexed with the chip select
pins and is output only. Most of Port 2 is multiplexed
with the serial channel pins. Port 2 pins are limited to
either an output or input function depending on the
operation of the serial pin it is multiplexed with.

Two bits of Port 2 are not multiplexed with any other
peripheral functions and can be used as either an
input or an output function. A port direction register
is used to define the function of the port pin. The
output for these two pins are open drain.

Besides a direction register, each port channel has a
data latch register, port pin register, and a port multi­plexer control register.

REFRESH CONTROL UNIT

The Refresh Control Unit (RCU) automatically gen­erates a periodic memory read bus cycle to keep
dynamic or pseudo-static memory refreshed. A 9-bit
counter controls the number of clocks between re­fresh requests.

A 12-bit address generator is maintained by the RCU
and is presented on the A12:1 address lines during
the refresh bus cycle. The address generator is in­cremented only after the refresh bus cycle is run.
This ensures that all address combinations will be
presented to the memory array even if the refresh
bus cycle is not run before another request is gener­ated. Address bits A19:13 are programmable to al­low the refresh address block to be located on any 8
Kbyte boundary.

The chip-select unit is active during refresh bus cy­cles. This means that a chip-select will go active if
the refresh address is within the limits specified for
the channel. In addition, BHE

and A0 are both driven
high during refresh bus cycles (this is normally an
invalid bus condition). Data on the AD15:0 bus is
ignored.

A pending refresh request will attempt to abort a
HOLD/HLDA bus exchange. HLDA is deasserted
when a refresh request is pending and a bus HOLD
is already in progress. HOLD must then be released
in order for the M80C186EB to execute the refresh
bus cycle.

POWER MANAGEMENT UNIT

The M80C186EB Power Management Unit (PMU) is
provided to control the power consumption of the
device. The PMU provides three power modes: Ac­tive, Idle, and Powerdown.

Active Mode indicates that all units on the
M80C186EB are functional and the device con­sumes maximum power (depending on the level of
peripheral operation). Idle Mode freezes the clocks
of the Execution and Bus units at a logic zero state
(all peripherals continue to operate normally). An un­masked interrupt, NMI, or reset will cause the
M80C186EB to exit the Idle mode.

The Powerdown mode freezes all internal clocks at
a logic zero level and disables the crystal oscillator.
All internal registers hold their values provided V

CC

is maintained. Current consumption is reduced to
just transistor junction leakage. An NMI or processor
reset will cause the M80C186EB to exit the Power­down Mode. A timing pin is provided to establish the
length of time between exiting Powerdown and re­suming device operation. (Length of time depends
on startup time of crystal oscillator and is application
dependent.)

M80C187 Interface

The M80C186EB supports the direct connection of
the M80C187 Numerics Coprocessor.

ONCE Test Mode

To facilitate testing and inspection of devices when
fixed into a target system, the M80C186EB has a
test mode available which forces all output and in­put/output pins to be placed in the high-impedance
state. ONCE stands for ‘‘ON Circuit Emulation’’. The
ONCE mode is selected by forcing the A19/ONCE
pin LOW (0) during a processor reset (this pin is
weakly held to a HIGH (1) level) while RESIN

is ac-

tive.

13

M80C186EB

PACKAGE INFORMATION

This section describes the pins, pinouts, and thermal
characteristics for the M80C186EB PGA package.
For complete package specifications and informa­tion, see the Intel Packaging Outlines and Dimen­sions Guide (Order Number: 231369).

Pin Descriptions

The M80C186EB pins are described in this section.
Table 3 presents the legend for interpreting the pin
descriptions in Table 4. Figure 7 provides an exam­ple pin description entry. The ‘‘I/O’’ signifies that the
pins are bidirectional (i.e., have both an input and
output function). The ‘‘S’’ indicates that, as an input,
the signal is synchronized to CLKOUT for proper op­eration. The ‘‘H(Z)’’ indicates that these pins will
float while the processor is in the Hold Acknowledge
state. R(Z) indicates that these pins will float while
RESIN

is low. P(X) Indicates that these pins will re­tain its current value when Idle or Powerdown
Modes are entered.

All pins float while the processor is in the ONCE
Mode, except OSCOUT (OSCOUT is required for
crystal operation).

Name Type Description

AD15:0 I/O These pins provide a multiplexed

S(L) ADDRESS and DATA bus. During
H(Z) the address phase of the bus
R(Z) cycle, address bits 0 through 15
P(X) are presented on the bus and can

be latched using ALE. 8- or 16-bit
data information are transferred
during the data phase of the bus
cycle.

Figure 7. Example Pin Description Entry

Table 3. Pin Description Nomenclature

Symbol Description

I Input Only Pin

O Output Only Pin

I/O Pin can be either input or output

Ð Pin ‘‘must be’’ connected as described

S(..) Synchronous. Input must meet setup and

hold times for proper operation of the
processor. The pin is:

S(E) edge sensitive
S(L) level sensitive

A(..) Asynchronous. Input must meet setup and

hold only to guarantee recognition. The
pin is:

A(E) edge sensitive
A(L) level sensitive

H(..) While the processor’s bus is in the Hold

Acknowledge state, the pin:

H(1) is driven to V

CC

H(0) is driven to V

SS

H(Z) floats
H(Q) remains active
H(X) retains current state

R(..) While the processor’s RES line is low, the

pin:

R(1) is driven to V

CC

R(0) is driven to V

SS

R(Z) floats
R(WH) weak pullup
R(WL) weak pulldown

P(..) While Idle or Powerdown modes are

active, the pin:

P(1) is driven to V

CC

P(0) is driven to V

SS

P(Z) floats
P(Q) remains active

(1)

P(X) retains current state

NOTE:

1. Any pin that specifies P(Q) are valid for Idle
Mode. All pins are P(X) for Powerdown Mode.

14

M80C186EB

Table 4. M80C186EB Pin Descriptions

Name Type Description

V

CC

POWER connections consist of four pins which must be shorted
externally to a V

CC

board plane.

V

SS

GROUND connections consist of six pins which must be shorted
externally to a V

SS

board plane.

CLKIN I CLocK INput is an input for an external clock. An external oscillator

operating at two times the required M80C186EB operating frequency

A(E)

can be connected to CLKIN. For crystal operation, CLKIN (along with
OSCOUT) are the crystal connections to an internal Pierce oscillator.

OSCOUT O OSCillator OUTput is only used when using a crystal to generate the

external clock. OSCOUT (along with CLKIN) are the crystal

H(Q)

connections to an internal Pierce oscillator. This pin is not to be used

R(Q)

as 2X clock output for non-crystal applications (i.e., this pin is N.C. for

P(Q)

non-crystal applications). OSCOUT does not float in ONCE mode.

CLKOUT O CLocK OUTput provides a timing reference for inputs and outputs of

the processor, and is one-half the input clock (CLKIN) frequency.

H(Q)

CLKOUT has a 50% duty cycle and transistions every falling edge of

R(Q)

CLKIN.

P(Q)

RESIN I RESet IN causes the M80C186EB to immediately terminate any bus

cycle in progress and assume an initialized state. All pins will be

A(L)

driven to a known state, and RESOUT will also be driven active. The
rising edge (low-to-high) transition synchronizes CLKOUT with CLKIN
before the M80C186EB begins fetching opcodes at memory location
0FFFF0H.

RESOUT O RESet OUTput that indicates the M80C186EB is currently in the

reset state. RESOUT will remain active as long as RESIN

remains

H(0)

active.

R(1)
P(0)

PDTMR I/O Power-Down TiMeR pin (normally connected to an external

capacitor) that determines the amount of time the M80C186EB waits

A(L)

after an exit from power down before resuming normal operation. The

H(WH)

duration of time required will depend on the startup characteristics of

R(Z)

the crystal oscillator.

P(1)

NMI I Non-Maskable Interrupt input causes a TYPE-2 interrupt to be

serviced by the CPU. NMI is latched internally.

A(E)

TEST/BUSY I TEST is used during the execution of the WAIT instruction to

suspend CPU operation until the pin is sampled active (LOW). TEST

A(E)

is alternately known as BUSY when interfacing with an M80C187
numerics coprocessor.

AD15:0 I/O These pins provide a multiplexed Address and Data bus. During the

address phase of the bus cycle, address bits 0 through 15 are

S(L)

presented on the bus and can be latched using ALE. 8- or 16-bit data

H(Z)

information is transferred during the data phase of the bus cycle.

R(Z)
P(X)

A18:16 These pins provide multiplexed Address during the address phase of

the bus cycle. Address bits 16 through 19 are presented on these

A19/ONCE

H(Z)

pins and can be latched using ALE. These pins are driven to a logic 0

R(WH)

during the data phase of the bus cycle. During a processor reset

P(X)

(RESIN active), A19/ONCE is used to enable ONCE mode. A18:16
must not be driven low during reset or improper M80C186EB
operation may result.

15

M80C186EB

Table 4. M80C186EB Pin Descriptions (Continued)

Name Type Description

S2:0 O Bus cycle Status are encoded on these pins to provide bus transaction

information. S2:0

are encoded as follows:

H(Z)
R(Z)

S2 S1 S0 Bus Cycle Initiated

P(1)

0 0 0 Interrupt Acknowledge
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 Processor HALT
1 0 0 Queue Instruction Fetch
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive (no bus activity)

ALE O Address Latch Enable output is used to strobe address information into a

transparent type latch during the address phase of the bus cycle.

H(0)
R(0)

P(0)

BHE O Byte High Enable output to indicate that the bus cycle in progress is

transferring data over the upper half of the data bus. BHE

and A0 have the

H(Z)

following logical encoding:

R(Z)

A0 BHE

Encoding

P(X)

0 0 Word Transfer
0 1 Even Byte Transfer
1 0 Odd Byte Transfer
1 1 Refresh Operation

RD O ReaD output signals that the accessed memory or I/O device must drive

data information onto the data bus.

H(Z)
R(Z)

P(1)

WR O WRite output signals that data available on the data bus are to be written

into the accessed memory or I/O device.

H(Z)
R(Z)

P(1)

READY I READY input to signal the completion of a bus cycle. READY must be

active to terminate any M80C186EB bus cycle, unless it is ignored by

A(L)

correctly programming the Chip-Select Unit.

S(L)

DEN O Data ENable output to control the enable of bi-directional transceivers

when buffering a M80C186EB system. DEN

is active only when data is to be

H(Z)

transferred on the bus.

R(Z)

P(1)

DT/R O Data Transmit/Receive output controls the direction of a bi-directional

buffer when buffering an M80C186EB system.

H(Z)
R(Z)
P(X)

LOCK I/O LOCK output indicates that the bus cycle in progress is not to be

interrupted. The M80C186EB will not service other bus requests (such as

H(Z)

HOLD) while LOCK

is active. This pin is configured as a weakly held high

R(WH)

input while RESIN is active and must not be driven low.

P(1)

16

M80C186EB

Table 4. M80C186EB Pin Descriptions (Continued)

Name Type Description

HOLD I HOLD request input to signal that an external bus master wishes to gain

control of the local bus. The M80C186EB will relinquish control of the local

A(L)

bus between instruction boundaries not conditioned by a LOCK prefix.

HLDA O HoLD Acknowledge output to indicate that the M80C186EB has relinquish

control of the local bus. When HLDA is asserted, the M80C186EB will (or

H(1)

has) floated its data bus and control signals allowing another bus master to

R(0)

drive the signals directly.

P(0)

NCS O Numerics Coprocessor Select output is generated when accessing a

numerics coprocessor.

H(1)
R(1)

P(1)

ERROR I ERROR input that indicates the last numerics coprocessor operation

resulted in an exception condition. An interrupt TYPE 16 is generated if

A(L)

ERROR

is sampled active at the beginning of a numerics operation.

PEREQ I CoProcessor REQuest signals that a data transfer between an External

Numerics Coprocessor and Memory is pending.

A(L)

UCS O Upper Chip Select will go active whenever the address of a memory or I/O

bus cycle is within the address limitations programmed by the user. After

H(1)

reset, UCS is configured to be active for memory accesses between

R(1)

0FFC00H and 0FFFFFH.

P(1)

LCS O Lower Chip Select will go active whenever the address of a memory bus

cycle is within the address limitations programmed by the user. LCS

is

H(1)

inactive after a reset.

R(1)

P(1)

P1.0/GCS0 O These pins provide a multiplexed function. If enabled, each pin can provide

a Generic Chip Select output which will go active whenever the address of

P1.1/GCS1

H(X)/H(1)

a memory or I/O bus cycle is within the address limitations programmed by

P1.2/GCS2

R(1)

the user. When not programmed as a Chip-Select, each pin may be used as

P1.3/GCS3

P(X)/P(1)

a general purpose output Port. As an output port pin, the value of the pin

P1.4/GCS4

can be read internally.

P1.5/GCS5
P1.6/GCS6
P1.7/GCS7

T0OUT O Timer OUTput pins can be programmed to provide a single clock or

continuous waveform generation, depending on the timer mode selected.

T1OUT H(Q)

R(1)
P(Q)

T0IN I Timer INput is used either as clock or control signals, depending on the

timer mode selected.

T1IN A(L)

A(E)

17