Intel Corporation LD8088-2, LD8088 Datasheet

August 1990 Order Number: 231456-006

8088

8-BIT HMOS MICROPROCESSOR

8088/8088-2

Y

8-Bit Data Bus Interface

Y

16-Bit Internal Architecture

Y

Direct Addressing Capability to 1 Mbyte
of Memory

Y

Direct Software Compatibility with 8086
CPU

Y

14-Word by 16-Bit Register Set with
Symmetrical Operations

Y

24 Operand Addressing Modes

Y

Byte, Word, and Block Operations

Y

8-Bit and 16-Bit Signed and Unsigned
Arithmetic in Binary or Decimal,
Including Multiply and Divide

Y

Two Clock Rates:
Ð 5 MHz for 8088
Ð 8 MHz for 8088-2

Y

Available in EXPRESS
Ð Standard Temperature Range
Ð Extended Temperature Range

The Intel 8088 is a high performance microprocessor implemented in N-channel, depletion load, silicon gate
technology (HMOS-II), and packaged in a 40-pin CERDIP package. The processor has attributes of both 8­and 16-bit microprocessors. It is directly compatible with 8086 software and 8080/8085 hardware and periph­erals.

231456– 1

Figure 1. 8088 CPU Functional Block Diagram

231456– 2

Figure 2. 8088 Pin Configuration

8088

Table 1. Pin Description

The following pin function descriptions are for 8088 systems in either minimum or maximum mode. The ‘‘local
bus’’ in these descriptions is the direct multiplexed bus interface connection to the 8088 (without regard to
additional bus buffers).

Symbol Pin No. Type Name and Function

AD7–AD0 9–16 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed

memory/IO address (T1) and data (T2, T3, Tw, T4) bus. These lines are
active HIGH and float to 3-state OFF during interrupt acknowledge and
local bus ‘‘hold acknowledge’’.

A15–A8 2–8, 39 O ADDRESS BUS: These lines provide address bits 8 through 15 for the

entire bus cycle (T1 – T4). These lines do not have to be latched by ALE
to remain valid. A15 – A8 are active HIGH and float to 3-state OFF
during interrupt acknowledge and local bus ‘‘hold acknowledge’’.

A17/S4, A16/S3

A19/S6, A18/S5, 35–38 O ADDRESS/STATUS: During T1, these are the four most significant

address lines for memory operations. During I/O operations, these lines
are LOW. During memory and I/O operations, status information is
available on these lines during T2, T3, Tw, and T4. S6 is always low.
The status of the interrupt enable flag bit (S5) is updated at the
beginning of each clock cycle. S4 and S3 are encoded as shown.

This information indicates which segment register is presently being
used for data accessing.

These lines float to 3-state OFF during local bus ‘‘hold acknowledge’’.

S4 S3 Characteristics

0 (LOW) 0 Alternate Data
0 1 Stack
1 (HIGH) 0 Code or None
1 1 Data
S6 is 0 (LOW)

RD 32 O READ: Read strobe indicates that the processor is performing a

memory or I/O read cycle, depending on the state of the IO/M

pin or
S2. This signal is used to read devices which reside on the 8088 local
bus. RD

is active LOW during T2, T3 and Tw of any read cycle, and is

guaranteed to remain HIGH in T2 until the 8088 local bus has floated.
This signal floats to 3-state OFF in ‘‘hold acknowledge’’.

READY 22 I READY: is the acknowledgement from the addressed memory or I/O

device that it will complete the data transfer. The RDY signal from
memory or I/O is synchronized by the 8284 clock generator to form
READY. This signal is active HIGH. The 8088 READY input is not
synchronized. Correct operation is not guaranteed if the set up and hold
times are not met.

INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled

during the last clock cycle of each instruction to determine if the
processor should enter into an interrupt acknowledge operation. A
subroutine is vectored to via an interrupt vector lookup table located in
system memory. It can be internally masked by software resetting the
interrupt enable bit. INTR is internally synchronized. This signal is active
HIGH.

TEST 23 I TEST: input is examined by the ‘‘wait for test’’ instruction. If the TEST

input is LOW, execution continues, otherwise the processor waits in an
‘‘idle’’ state. This input is synchronized internally during each clock
cycle on the leading edge of CLK.

2

8088

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

NMI 17 I NON-MASKABLE INTERRUPT: is an edge triggered input which causes a

type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup
table located in system memory. NMI is not maskable internally by
software. A transition from a LOW to HIGH initiates the interrupt at the end
of the current instruction. This input is internally synchronized.

RESET 21 I RESET: causes the processor to immediately terminate its present activity.

The signal must be active HIGH for at least four clock cycles. It restarts
execution, as described in the instruction set description, when RESET
returns LOW. RESET is internally synchronized.

CLK 19 I CLOCK: provides the basic timing for the processor and bus controller. It is

asymmetric with a 33% duty cycle to provide optimized internal timing.

V

CC

40 VCC: is thea5Vg10% power supply pin.

GND 1, 20 GND: are the ground pins.

MN/MX 33 I MINIMUM/MAXIMUM: indicates what mode the processor is to operate in.

The two modes are discussed in the following sections.

The following pin function descriptions are for the 8088 minimum mode (i.e., MN/MXeVCC). Only the pin
functions which are unique to minimum mode are described; all other pin functions are as described above.

Symbol Pin No. Type Name and Function

IO/M 28 O STATUS LINE: is an inverted maximum mode S2 . It is used to distinguish a

memory access from an I/O access. IO/M

becomes valid in the T4 preceding a

bus cycle and remains valid until the final T4 of the cycle (I/O

e

HIGH, M

e

LOW). IO/M floats to 3-state OFF in local bus ‘‘hold acknowledge’’.

WR 29 O WRITE: strobe indicates that the processor is performing a write memory or write

I/O cycle, depending on the state of the IO/M

signal. WR is active for T2, T3, and
Tw of any write cycle. It is active LOW, and floats to 3-state OFF in local bus
‘‘hold acknowledge’’.

INTA 24 O INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW

during T2, T3, and Tw of each interrupt acknowledge cycle.

ALE 25 O ADDRESS LATCH ENABLE: is provided by the processor to latch the address

into an address latch. It is a HIGH pulse active during clock low of T1 of any bus
cycle. Note that ALE is never floated.

DT/R 27 O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use

a data bus transceiver. It is used to control the direction of data flow through the
transceiver. Logically, DT/R

is equivalent to S1 in the maximum mode, and its

timing is the same as for IO/M

(TeHIGH, ReLOW). This signal floats to

3-state OFF in local ‘‘hold acknowledge’’.

DEN 26 O DATA ENABLE: is provided as an output enable for the data bus transceiver in a

minimum system which uses the transceiver. DEN

is active LOW during each
memory and I/O access, and for INTA cycles. For a read or INTA cycle, it is
active from the middle of T2 until the middle of T4, while for a write cycle, it is
active from the beginning of T2 until the middle of T4. DEN

floats to 3-state OFF

during local bus ‘‘hold acknowledge’’.

3

8088

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

HOLD,
HLDA

31, 30 I, O HOLD: indicates that another master is requesting a local bus ‘‘hold’’. To be

acknowledged, HOLD must be active HIGH. The processor receiving the ‘‘hold’’
request will issue HLDA (HIGH) as an acknowledgement, in the middle of a T4 or
Ti clock cycle. Simultaneous with the issuance of HLDA the processor will float
the local bus and control lines. After HOLD is detected as being LOW, the
processor lowers HLDA, and when the processor needs to run another cycle, it
will again drive the local bus and control lines. HOLD and HLDA have internal
pull-up resistors.

Hold is not an asynchronous input. External synchronization should be provided if
the system cannot otherwise guarantee the set up time.

SSO 34 O STATUS LINE: is logically equivalent to SO in the maximum mode. The

combination of SSO

, IO/M and DT/R allows the system to completely decode the

current bus cycle status.

IO/M DT/R SSO Characteristics

1(HIGH) 0 0 Interrupt Acknowledge
1 0 1 Read I/O Port
1 1 0 Write I/O Port
1 1 1 Halt
0(LOW) 0 0 Code Access
0 0 1 Read Memory
0 1 0 Write Memory
0 1 1 Passive

The following pin function descriptions are for the 8088/8288 system in maximum mode (i.e., MN/MX

e

GND). Only the pin functions which are unique to maximum mode are described; all other pin functions are as
described above.

Symbol Pin No. Type Name and Function

S2,S1,S0 26–28 O STATUS: is active during clock high of T4, T1, and T2, and is returned to the

passive state (1,1,1) during T3 or during Tw when READY is HIGH. This status is
used by the 8288 bus controller to generate all memory and I/O access control
signals. Any change by S2

,S1,orS0during T4 is used to indicate the beginning
of a bus cycle, and the return to the passive state in T3 and Tw is used to
indicate the end of a bus cycle.
These signals float to 3-state OFF during ‘‘hold acknowledge’’. During the first
clock cycle after RESET becomes active, these signals are active HIGH. After
this first clock, they float to 3-state OFF.

S2 S1 S0 Characteristics

0(LOW) 0 0 Interrupt Acknowledge
0 0 1 Read I/O Port
0 1 0 Write I/O Port
0 1 1 Halt
1(HIGH) 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive

4

8088

Table 1. Pin Description (Continued)

Symbol Pin No. Type Name and Function

RQ/GT0,
RQ

/GT1

30, 31 I/O REQUEST/GRANT: pins are used by other local bus masters to force the

processor to release the local bus at the end of the processor’s current bus
cycle. Each pin is bidirectional with RQ

/GT0 having higher priority than RQ/

GT1

.RQ/GT has an internal pull-up resistor, so may be left unconnected.

The request/grant sequence is as follows (See Figure 8):

1. A pulse of one CLK wide from another local bus master indicates a local
bus request (‘‘hold’’) to the 8088 (pulse 1).

2. During a T4 or TI clock cycle, a pulse one clock wide from the 8088 to the
requesting master (pulse 2), indicates that the 8088 has allowed the local
bus to float and that it will enter the ‘‘hold acknowledge’’ state at the next
CLK. The CPU’s bus interface unit is disconnected logically from the local
bus during ‘‘hold acknowledge’’. The same rules as for HOLD/HOLDA apply
as for when the bus is released.

3. A pulse one CLK wide from the requesting master indicates to the 8088
(pulse 3) that the ‘‘hold’’ request is about to end and that the 8088 can
reclaim the local bus at the next CLK. The CPU then enters T4.

Each master-master exchange of the local bus is a sequence of three
pulses. There must be one idle CLK cycle after each bus exchange. Pulses
are active LOW.

If the request is made while the CPU is performing a memory cycle, it will
release the local bus during T4 of the cycle when all the following conditions
are met:

1. Request occurs on or before T2.

2. Current cycle is not the low bit of a word.

3. Current cycle is not the first acknowledge of an interrupt acknowledge
sequence.

4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will

follow:

1. Local bus will be released during the next clock.

2. A memory cycle will start within 3 clocks. Now the four rules for a currently
active memory cycle apply with condition number 1 already satisfied.

LOCK 29 O LOCK: indicates that other system bus masters are not to gain control of the

system bus while LOCK

is active (LOW). The LOCK signal is activated by
the ‘‘LOCK’’ prefix instruction and remains active until the completion of the
next instruction. This signal is active LOW, and floats to 3-state off in ‘‘hold
acknowledge’’.

QS1, QS0 24, 25 O QUEUE STATUS: provide status to allow external tracking of the internal

8088 instruction queue.
The queue status is valid during the CLK cycle after which the queue
operation is performed.

QS1 QS0 Characteristics

0(LOW) 0 No Operation
0 1 First Byte of Opcode from Queue
1(HIGH) 0 Empty the Queue
1 1 Subsequent Byte from Queue

Ð 34 O Pin 34 is always high in the maximum mode.

5

8088

231456– 3

Figure 3. Memory Organization

FUNCTIONAL DESCRIPTION

Memory Organization

The processor provides a 20-bit address to memory
which locates the byte being referenced. The memo­ry is organized as a linear array of up to 1 million
bytes, addressed as 00000(H) to FFFFF(H). The
memory is logically divided into code, data, extra
data, and stack segments of up to 64K bytes each,
with each segment falling on 16-byte boundaries
(See Figure 3).

All memory references are made relative to base ad­dresses contained in high speed segment registers.
The segment types were chosen based on the ad-

dressing needs of programs. The segment register
to be selected is automatically chosen according to
the rules of the following table. All information in one
segment type share the same logical attributes (e.g.
code or data). By structuring memory into relocat­able areas of similar characteristics and by automati­cally selecting segment registers, programs are
shorter, faster, and more structured.

Word (16-bit) operands can be located on even or
odd address boundaries. For address and data oper­ands, the least significant byte of the word is stored
in the lower valued address location and the most
significant byte in the next higher address location.
The BIU will automatically execute two fetch or write
cycles for 16-bit operands.

Memory Segment

Segment Selection Rule

Reference Used Register Used

Instructions CODE (CS) Automatic with all instruction prefetch.

Stack STACK (SS) All stack pushes and pops. Memory references

relative to BP base register except data references.

Local Data DATA (DS) Data references when: relative to stack, destination

of string operation, or explicity overridden.

External (Global) Data EXTRA (ES) Destination of string operations: Explicitly selected

using a segment override.

6

8088

Certain locations in memory are reserved for specific
CPU operations (See Figure 4). Locations from ad­dresses FFFF0H through FFFFFH are reserved for
operations including a jump to the initial system ini­tialization routine. Following RESET, the CPU will al­ways begin execution at location FFFF0H where the
jump must be located. Locations 00000H through
003FFH are reserved for interrupt operations. Four­byte pointers consisting of a 16-bit segment address
and a 16-bit offset address direct program flow to
one of the 256 possible interrupt service routines.
The pointer elements are assumed to have been
stored at their respective places in reserved memory
prior to the occurrence of interrupts.

Minimum and Maximum Modes

The requirements for supporting minimum and maxi­mum 8088 systems are sufficiently different that
they cannot be done efficiently with 40 uniquely de­fined pins. Consequently, the 8088 is equipped with
a strap pin (MN/MX) which defines the system con-

231456– 4

Figure 4. Reserved Memory Locations

figuration. The definition of a certain subset of the
pins changes, dependent on the condition of the
strap pin. When the MN/MX

pin is strapped to GND,
the 8088 defines pins 24 through 31 and 34 in maxi­mum mode. When the MN/MX

pin is strapped to

V

CC

, the 8088 generates bus control signals itself on

pins 24 through 31 and 34.

The minimum mode 8088 can be used with either a
multiplexed or demultiplexed bus. The multiplexed
bus configuration is compatible with the MCS-85
multiplexed bus peripherals. This configuration (See
Figure 5) provides the user with a minimum chip
count system. This architecture provides the 8088
processing power in a highly integrated form.

The demultiplexed mode requires one latch (for 64K
addressability) or two latches (for a full megabyte of
addressing). A third latch can be used for buffering if
the address bus loading requires it. A transceiver
can also be used if data bus buffering is required
(See Figure 6). The 8088 provides DEN

and DT/R to
control the transceiver, and ALE to latch the ad­dresses. This configuration of the minimum mode
provides the standard demultiplexed bus structure
with heavy bus buffering and relaxed bus timing re­quirements.

The maximum mode employs the 8288 bus control­ler (See Figure 7). The 8288 decodes status lines
S0

,S1, and S2, and provides the system with all bus
control signals. Moving the bus control to the 8288
provides better source and sink current capability to
the control lines, and frees the 8088 pins for extend­ed large system features. Hardware lock, queue
status, and two request/grant interfaces are provid­ed by the 8088 in maximum mode. These features
allow co-processors in local bus and remote bus
configurations.

7

8088

231456– 5

Figure 5. Multiplexed Bus Configuration

8

8088

231456– 6

Figure 6. Demultiplexed Bus Configuration

231456– 7

Figure 7. Fully Buffered System Using Bus Controller

9